JPH11261050A - Semiconductor device and electrostatic induction type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance and high-reliability semiconductor device of the structure, wherein a short-circuit between a gate and a cathode due to etching residues in a metal layer can be reduced. SOLUTION: In a semiconductor device of the structure, wherein metal layers 19 and 18 are respectively arranged on at least two semiconductor layers 4 and 5 of different polarities to form at least two electrode parts and these electrode parts are formed by performing an interlayer isolation using interlayer isolation films 6 and 15, an insulating isolation part 21a of the two electrode parts 18 and 19 is arranged separately from the edges, in which etching residues 22a in the metal layer 18 are hardly generated, of the layers 18 and 19 and at the same time, the aspect ratio of the insulating isolation part 21a is set in a ratio of 1 to 0.4 or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to an improvement in electrode design on a chip such as an electrostatic induction type semiconductor device.

[0002]

2. Description of the Related Art Electrostatic induction thyristors (SI thyristors)
In the manufacture of semiconductor devices such as those described above, P-type and N-type semiconductor layers are formed in a wafer, and then an electrode layer is formed thereon. This electrode has a multilayer wiring structure in order to increase the area utilization rate of the element and to minimize the chip area, and insulates the lower electrode and the upper electrode using an interlayer insulating film such as a silicon oxide film. As shown in FIG. 4, in forming an interlayer insulating film or each electrode, an insulating film or a metal film is formed on the entire surface of the wafer, and then processed into respective patterns using a photolithography technique.

FIG. 4 shows a process of manufacturing a semiconductor device such as an electrostatic induction thyristor (SI thyristor). In FIG. 4, reference numeral 1 denotes an N-type silicon substrate, and 2 denotes a P anode formed on one surface of the substrate 1. The layers 3 and 3 are N ⁻ base layers formed on the other surface of the substrate 1, 4 is a P gate layer also formed on the other surface of the substrate 1, and 5 is an N ⁺ layer formed on the N ⁻ base layer.
It is a cathode layer. 4 is composed of photolithography (exposure process) and an electrode process. Photolithography is a process shown in FIGS. 4A to 4F, and an electrode process is shown in FIGS. 4G to 4I. It is a process of.

[0004] As shown in FIG.
An oxide film (SiO ₂ ) 6 is deposited on the exposed surface of the gate layer 4 and the exposed surface of the N ⁻ base layer 3, and a photosensitive agent (resist) 7 is applied on the oxide film 6 as shown in FIG. . Thereafter, as shown in FIG. 4 (C), light 10 is exposed to the photosensitive agent 7 through a mask 8 and a lens 9 to cause a phenomenon as shown in FIG. A groove 11 is formed. Next, the oxide film 6 exposed at the bottom of the groove 11, that is, on the P gate layer 4, is etched to form a groove 12 extending over the oxide film 6 and the photosensitive agent 7, and thereafter, as shown in FIG. The resist is removed from the photosensitive agent 7 to complete the photolithography.

After the photolithography step, FIG.
As shown in FIG. 7, aluminum is deposited over the exposed surfaces of the P gate layer 4, the N ⁻ base layer 3, the N ⁺ cathode layer 5 and the oxide film 6 to form an aluminum film 14. Thereafter, an exposure process (processing of an aluminum vapor-deposited film) is performed as shown in FIG.
Subjected to oxide film CVD (plasma CVD) as shown in (H) to form a CVD oxide film 15, N ⁺ cathode layer 5 as shown in FIG. 4 (I), the oxide film 6, an aluminum deposition film 14 and oxide An aluminum layer is formed by evaporating aluminum on the exposed surface of the film 15, and the electrode process is completed.

When the lower electrode is formed of a metal having a low melting point such as aluminum, the interlayer insulating film between the electrodes cannot be formed at a temperature higher than the melting point of the metal.

At present, plasma CVD is used to form an interlayer insulating film.
(Chemical Vapor Deposition
n) is frequently used. In this method, high-frequency power is applied to a source gas to cause a plasma reaction, and the reaction product is deposited on a wafer. The reaction product can be formed at a relatively low temperature (approximately 300 ° C.). Coverage) is good.

FIG. 5 is a plan view of the SI thyristor shown in FIG. 4 (I), in which 17 is a lower gate electrode (aluminum film 14), 18 is a cathode pad electrode (upper cathode electrode, aluminum layer 16), and 19 is Gate pad electrode (upper gate electrode, aluminum film 14), 20 is CV
A cathode contact hole provided in the D film 15 (FIG. 4), 21 is an insulating separation portion between the gate and cathode pad electrodes, and 23 is a place where aluminum residue 22 is likely to be generated.

In the SI thyristor, the lower electrode corresponds to a gate electrode, and the upper electrode corresponds to a cathode pad electrode and a lead pad electrode of a lower gate electrode. The element is turned on and off by flowing a current between the gate and the cathode.

[0010]

The above-mentioned plasma CVD
When an interlayer insulating film is formed by the method described above, if the lower gate electrode 17 has an uneven portion 17a as shown in FIG.
The reaction product is not buried, and similar uneven portions are formed on the CVD oxide film 15 as the interlayer insulating film as shown in FIG. In addition, overhang portions 15a are formed by overhanging on the side wall of the stepped portion of the uneven portion due to the good step coverage of the plasma CVD film, and the shape is as shown in FIG. This phenomenon easily occurs at the edge of the lower electrode 17.

In dry etching using gas plasma, when a submicron microstructure is formed or when the aspect ratio (depth / width) of the portion to be etched is large, aluminum residue 2
2 easily occurs.

Therefore, when a metal film is deposited and etched on the uneven shape on the CVD film, the metal that has entered the fine portion of the overhang portion is hardly etched. Although this problem does not usually occur, it may be likely to occur due to aging or variation in the performance of the etching apparatus.

In the conventional SI thyristor, the gate electrode and the cathode electrode are arranged as shown in FIG. 5, and the aspect ratio is 0.7, which is relatively large. Therefore, as shown in FIG. As a result, the upper layer cathode pad electrode 18 and the upper layer gate electrode pad 19 may be short-circuited.

In a self-extinguishing type device such as an SI thyristor, a current flows between a gate and a cathode disposed on a chip to turn the device on and off. If each electrode is short-circuited, the switching function is lost.

The present invention has been made in view of the above-mentioned problems of the prior art, and has an object to reduce a short circuit between a gate and a cathode due to a residue of etching of a metal layer. It is to provide a semiconductor device.

[0016]

In order to achieve the above object, a semiconductor device according to the present invention comprises a metal layer disposed on at least two semiconductor layers having different polarities to form at least two electrode portions. In a semiconductor device in which these electrode portions are insulated from each other by using an interlayer insulating film, the insulation separation portion of the two electrode portions may be formed by a metal etching residue of at least one of the electrode portions. It is characterized by being placed away from difficult edges. Further, the aspect ratio of the insulating isolation portion is set to 0.4 or less.

Further, the self-extinguishing type electrostatic induction semiconductor of the present invention is formed by laminating at least two semiconductor layers having mutually different polarities, and one of these semiconductor layers is provided with the other semiconductor layer. A cathode semiconductor layer of the same polarity and a gate semiconductor layer of a different polarity from the one semiconductor layer are provided, a metal layer is provided on the cathode semiconductor layer to form a cathode electrode portion, and a metal layer is provided on the gate semiconductor layer. A gate electrode portion, and an interlayer insulating portion provided between the cathode pad electrodes, wherein the cathode electrode portion includes an upper layer cathode pad electrode, and the gate electrode portion includes a lower layer gate electrode and an upper layer pad gate. Including an electrode, when the upper layer cathode pad electrode is insulated from the lower layer gate electrode and the upper layer pad gate electrode by an interlayer insulating film. Moni, characterized in that the isolation part of the upper pad electrode pattern was arranged so as to avoid the edges of the lower gate electrode.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a plan view of an SI thyristor according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG.
FIG. 3 is a sectional view taken along line BB of FIG.

1 to 3, reference numeral 1 denotes an N-type silicon substrate as a first semiconductor layer, 2 denotes a P anode layer as a second semiconductor layer formed on one surface of the substrate 1, and 3 denotes a substrate. 1
Is a third semiconductor layer formed on the other surface of the N ⁻ base layer, 4 is a fourth semiconductor layer formed on the N ⁻ base layer 3, a P gate layer, and 5 is an N ⁻ base layer 3. The N ⁺ cathode layer, which is the fifth semiconductor layer formed on the substrate.

In FIG. 1, as described above, reference numeral 17 denotes a lower gate electrode, reference numeral 18 denotes a cathode pad electrode, reference numeral 19 denotes a gate pad electrode, reference numeral 21a denotes a gate-cathode pad electrode separation portion, and reference numeral 22a denotes a residual aluminum residue. .

A feature of this embodiment is that in an SI thyristor having an electrode having an interlayer insulating structure, an insulating separation portion between a gate and a cathode pad electrode is arranged away from an edge of a lower electrode in which aluminum etching residue hardly occurs. At the same time, the aspect ratio of the insulating isolation portion is set to 0.4 or less to reduce aluminum residue.

As shown in FIG. 2, an oxide film (SiO ₂ ) 6 serving as a first insulating member is located over a part of the N ⁻ base layer 3 and a part of the P gate layer 4. A lower gate electrode is arranged over a part of the gate layer 4.
Further, a CVD oxide film 15 is provided over the oxide film 6, the lower gate electrode 17 and a part of the P gate layer 4. The cathode pad electrode 18 includes a plurality of N ⁺ cathode layers 5.
And the gate pad electrode 19 has a plurality of P gate layers 4.
Bridge. The cathode pad electrode 18 and the gate pad electrode 19 are insulated and separated via the CVD oxide film 15, and the lower gate electrode 17 and the gate pad electrode 19 serving as the upper gate electrode are insulated by the CVD oxide film 15. An insulating separation portion 21a is formed between the cathode pad electrode 18 and the gate pad electrode 19 facing each other. The aspect ratio (depth D / width W) of the insulating separation portion 21a is 0.4 or less, and specifically, D = 0.5 μm, W
= 12 microns, D / W ≒ 0.4 or less.

FIG. 3 shows an element structure including the lower layer electrode 17. The lower gate electrode 17 is formed under the CVD oxide film 15.
Is located under the lower gate electrode 17.
And the N ⁻ base layer 3 is located below the P-type gate layer 4.

According to the semiconductor device of the above embodiment, in the SI thyristor having the interlayer insulating structure, the insulating separation portion between the gate and the cathode pad electrode is arranged away from the edge of the lower electrode where the aluminum residue is hardly generated. At the same time, the aspect ratio of the insulating isolation portion is 0.4 or less,
Aluminum residue is reduced.

Therefore, the gate due to the aluminum residue
Short circuit between cathodes is reduced (short circuit rate is 50% to 20%
And the remaining aluminum is reduced by dry etching using gas plasma, and the tolerance of the etching apparatus can be increased.

[0027]

According to the present invention, as described above, at least two electrode portions are formed by disposing metal layers on at least two semiconductor layers having mutually different polarities, and an interlayer is formed between these electrode portions. In a semiconductor device in which interlayer insulation is performed by using an insulating film, an insulating separation portion of the two electrode portions is arranged away from an edge of at least one of the electrode portions where a metal etching residue hardly occurs. And the aspect ratio of the insulating isolation portion is set to 0.1.
Since the number is set to 4 or less, a short circuit between the gate and the cathode due to the metal layer etching residue can be reduced, and a high-performance and highly reliable semiconductor device can be provided.

[Brief description of the drawings]

FIG. 1 is a plan view of an electrostatic induction thyristor which is a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG. 1;

FIG. 3 is a sectional view taken along the line BB of FIG. 1;

FIG. 4 is a process chart of manufacturing an electrode portion of the semiconductor device.

FIG. 5 is a plan view of a conventional electrostatic induction thyristor.

FIG. 6 is a pattern diagram of an electrode portion of the electrostatic induction thyristor of FIG. 5;

FIG. 7 is an explanatory view showing a part of a lower gate electrode of the static induction thyristor of FIG. 5;

[Explanation of symbols]

1 ... N-type semiconductor layer 2 ... P-type semiconductor layer 3 ... N ^- -type semiconductor layer 4 ... P-type semiconductor layer 5 ... N ⁺ -type semiconductor layer 6 ... oxide film (SiO ₂₎ 14 ... aluminum layer 15 ... CVD oxide film 17 ... Lower layer gate electrode 18 ... Cathode pad electrode 19 ... Gate pad electrode 21a ... Insulation separation part between gate and cathode pad electrodes 22a ... Aluminum residue that can be generated

Claims (4)

[Claims] 1. A semiconductor comprising: a metal layer disposed on at least two semiconductor layers having different polarities to form at least two electrode portions; and an inter-layer insulation between the electrode portions using an interlayer insulating film. In the device, a semiconductor device is characterized in that an insulating separation portion of the two electrode portions is arranged apart from an edge of at least one of the electrode portions where a metal etching residue hardly occurs. 2. The method according to claim 1, wherein the aspect ratio of said insulating isolation portion is set to 0.1.
2. The semiconductor device according to claim 1, wherein the number is set to four or less. 3. A semiconductor device comprising: at least two semiconductor layers having different polarities stacked on each other; a cathode semiconductor layer having the same polarity as the one semiconductor layer and the one semiconductor layer on one of the semiconductor layers; Providing a gate semiconductor layer having a different polarity from that of the cathode pad, forming a cathode electrode portion by providing a metal layer on the cathode semiconductor layer, and forming a gate electrode portion by providing a metal layer on the gate semiconductor layer; A semiconductor device having an interlayer insulating portion provided therebetween, wherein the cathode electrode portion includes an upper-layer cathode pad electrode, and the gate electrode portion includes a lower-layer gate electrode and an upper-layer pad gate electrode; The lower layer gate electrode and the upper layer pad gate electrode are insulated by an interlayer insulating film, and the upper layer pad electrode pattern is insulated and separated. A portion is arranged so as to avoid an edge of the lower gate electrode, wherein the semiconductor device is an electrostatic induction type semiconductor device. 4. The method according to claim 1, wherein the aspect ratio of the insulating isolation portion is set to 0.1.
4. The electrostatic induction semiconductor device according to claim 3, wherein the number is four or less.