JPH11260922A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect fuses from corrosion damage even if fluorine is added to reduce permittivity, by forming a first insulating film having metal wirings, a protective film formed thereon, and a second insulating film formed further thereon and containing fluorine. SOLUTION: Fuses 12 are formed at predetermined positions in an insulating film 5 with fluorine added thereto on a semiconductor substrate 4. A nitride film 7 is formed on the insulating film 5 and an insulating film 13 with fluorine added thereto is formed thereon. Metal wirings 8 are formed at predetermined positions in the insulating film 13, and a nitride film 10 and a polyimide 11 are laminated on the insulating film 13. An aperture 14 is made to easily melt the fuses 12 with a laser. Therefore, when fluorine is added to the insulating film to reduce permittivity, the nitride film 7 formed over the fuses 12 can protect the fuses 12 made of metal from corrosion damage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to fuse reliability and, more particularly, to preventing fuse corrosion.

[0002]

2. Description of the Related Art In recent years, the size of semiconductor elements has been reduced, and the number of semiconductor elements formed in one semiconductor chip has increased. For this reason, defects such as a defect of a semiconductor element and a short circuit between wirings are increasing, which deteriorates product yield. In order to solve this, a redundant circuit technology has been put to practical use in a semiconductor memory device such as a DRAM. Redundant circuit technology means that if a memory cell connected to a word line or a bit line that is supposed to be used has a defect, a spare word line prepared in advance is used instead of using the word line. Technology for

In order not to select a word line connected to a defective memory cell, a part of the wiring may be cut in advance. Fusing by a laser is often used for cutting the wiring.

FIG. 11 shows a top view of a fuse portion. As shown in FIG. 11, the wiring 101 is
7 is connected to the fuse 114. The fuse 114 is connected to the wiring 102 via the contact 109. In addition, the wiring 103 is a contact 107
Is connected to the fuse 115 via the
11 is connected to the wiring 104. The wiring 10
5 is connected to a fuse 116 via a contact 112 and further connected to a wiring 106 via a contact 113. FIG. 12 is an enlarged view of the fuses 114 to 116. As shown in FIG.
116 has a thin portion so as to be easily blown by a laser. Further, the fuse is a part of a wiring constituting an electric circuit for selecting a word line or a bit line connected to a defective memory cell, and this circuit can be destroyed by blowing the fuse. Thus, the word line or the bit line connected to the defective memory cell is not selected.

FIG. 13 is a sectional view taken along line AA of FIG. As shown in FIG. 13, a silicon oxide film 118 is formed on a semiconductor substrate 117, and three fuses 114 to 116 are arranged on the surface thereof. An insulating film to which fluorine (F) is added is formed on the silicon oxide film 118. The metal wiring 123 is arranged at a predetermined position on the silicon oxide film 118. Further, an oxide film 120, a nitride film 121, and a protective insulating film 122 are formed on the silicon oxide film 118 in a stacked manner.

Further, three fuses 114 to 116 are arranged.
Is formed above, but the upper surfaces of the fuses 114 to 116 are not exposed. The reason why the upper surfaces of the fuses 114 to 116 are not exposed is that the fuse 1
This is for protecting the upper surfaces of the layers 00 to 102. In addition, since the laser transmits through an insulating film having a certain thickness, the laser can be sufficiently blown even if the upper surfaces of the fuses 114 to 116 are not exposed. If necessary, if a fuse at a predetermined position is blown by a laser, a word line or the like to which a defective memory cell is connected cannot be selected. In a memory such as a DRAM, a redundant circuit technique is realized as described above.

Next, a multilayer wiring in a logic such as an ASIC will be briefly described. In the field of logic and the like, multilayer wiring is used to reduce the chip area.
Specifically, an interlayer insulating film is formed on the lower wiring, and the upper wiring is formed on the interlayer insulating film. In this case, an upper layer wiring and a lower layer wiring form a (capacitance) capacitor with an interlayer insulating film interposed therebetween, and this parasitic capacitor causes a signal delay.

To reduce this parasitic capacitor, fluorine may be added to the interlayer insulating film. As a result, the dielectric constant of the interlayer insulating film can be reduced, so that signal delay can be prevented to some extent. As described above, the technique of reducing the capacity by adding fluorine to the interlayer insulating film has been known in the field of logic for some time.

On the other hand, in recent years, attention has been paid to a logic embedded DRAM in which a DRAM is embedded in a logic. Next, one of the problems of the DRAM with embedded logic will be described. Also in a logic embedded DRAM in which a DRAM is embedded in a logic, a multi-layer wiring is frequently used. Therefore, the technique of adding fluorine to the interlayer insulating film can be used to reduce the parasitic capacitance as described above. However, since fluorine is added at the same time as forming the interlayer insulating film, fluorine is added not only to the logic part but also to the memory part.

As described above, FIG. 13 is a sectional view of a fuse portion in a DRAM. FIG. 13 shows an example in which the technology for reducing the dielectric constant used in the logic field, that is, the technology for reducing the dielectric constant of an interlayer insulating film by adding fluorine, is also applied to a DRAM.

[0013] Fluorine (F) is added to the insulating film 7 shown in FIG. 13 to reduce the dielectric constant. This allows
For example, the metal wiring 123 and the fuse 11 which is a part of the wiring
4 to 116 can be reduced, and signal delay can be prevented.

[0012]

SUMMARY OF THE INVENTION As described above, the fuse 1
An interlayer insulating film 119 having a predetermined thickness is formed to protect the upper surfaces of 14 to 116. In addition, the fuse window 12
4, moisture (H 2 O) may enter the interlayer insulating film 119. Since fluorine is added to the interlayer insulating film 116, water (H2O) and fluorine (F) cause a chemical reaction to generate hydrofluoric acid (H2F) which is a strong acid. This hydrofluoric acid corrodes the fuses 114 to 116, and in the worst case, fuses that are not to be blown are blown.

The present invention has been made in view of the above problems, and provides a semiconductor device in which a fuse is not corroded even when fluorine is added in order to reduce the dielectric constant. The purpose is to provide a method.

[0014]

According to the present invention, there is provided a first insulating film having a metal wiring formed at a predetermined depth from an upper surface;
A semiconductor device mainly comprising: a protective film formed on the first insulating film; and a second insulating film formed on the protective film and containing fluorine. .

A step of forming a metal wiring on the upper surface of the first insulating film; a step of forming a second insulating film on the first insulating film; It is also a main feature that the method includes a step of forming a protective film and a step of forming a third insulating film containing fluorine on the protective film.
The invention of the present application can prevent the corrosion of the fuse by adopting the above configuration.

[0016]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a simple block diagram of a DRAM. As shown in FIG.
Is a memory cell array unit 1 in which memory cells (not shown) are arranged in a matrix, and a row decoder 2 for selecting a word line WL formed in the memory cell array unit 1.
And a column decoder 3 formed in the memory cell array unit 1 for selecting a column selection gate (not shown).

Next, FIG. 2 shows a simple equivalent circuit of the row decoder 3. As shown in FIG.
1 is connected to the node 902 at one end and the other end is connected to the power supply VC.
C, and a precharge clock is input to the gate terminal. One end of the fuse 903 is connected to the node 9.
02. One end of the current path of the transistor 904 is connected to the fuse 903, and the other end is connected to the power supply GND. One end of the fuse 903 is connected to the node 902. One end of the fuse 905 is connected to the node 902. One end of the current path of the transistor 906 is connected to the fuse 905, and the other end is connected to the power supply GND. Also, the transistor 90
Address signals A and / A are input to gate terminals 4 and 906, respectively. Here, / A means a complementary signal of A. The node 902 is connected to the inverter 90
A logic circuit 9 for selecting a spare word line via
06 and a logic circuit 907 for selecting one of the word lines WL1 and WL2.

FIG. 3A is a sectional view of a fuse portion. As shown in FIG. 3A, an insulating film (for example, a silicon oxide film) 5 to which fluorine is added is formed on the semiconductor substrate 4.
A fuse 12 is formed at a predetermined position. The reason why fluorine is added is to reduce the dielectric constant of the silicon oxide film 5. Further, a nitride film 7 is formed on the silicon oxide film 5, and an insulating film (for example, a silicon oxide film) 13 to which fluorine is added is formed thereon. The reason why fluorine is added is the same as described above.
Here, when the dielectric constant of the insulating film 5 is not large, the insulating film 5
May not contain fluorine.

At a predetermined position of the silicon oxide film 13, a metal wiring 8 made of aluminum is formed. Furthermore,
On the silicon oxide film 13, a nitride film 10 and a polyimide 11 are laminated. An opening 14 is provided so that the fuse 12 can be easily blown by a laser.
Here, the case where the opening 14 has a depth up to the middle of the silicon oxide film 13 is shown, but as shown in FIG.
The opening may be opened until the surface of the nitride film 7 is exposed.

When fluorine is added to an insulating film such as a silicon oxide film to reduce the dielectric constant, fluorine is also added to the silicon oxide film 5 on which the fuse 12 is formed. The added fluorine reacts with moisture to form highly acidic hydrofluoric acid, which corrodes the metal fuse 12. The feature of the present application is that the nitride film 7 is provided above the fuse 12 in order to prevent corrosion of the fuse 12.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 will be described. As shown in FIG. 4, an insulating film 51 (for example, a silicon oxide film) containing fluorine and having a thickness of about 40 nm is formed on the semiconductor substrate 4 by using the CVD method.
This insulating film 51 contains fluorine to reduce its dielectric constant.

Next, a groove having a depth of about 20 nm is formed in the insulating film 51 by using a photolithography method and an anisotropic etching method, and a metal fuse 12 is buried in the groove. next,
CVD is performed on the insulating film 51 (for example, a silicon oxide film).
An insulating film (for example, a silicon oxide film) 52 containing fluorine and having a thickness of about 10 nm is formed by using the method. Next, a protective film 7 (for example, a silicon nitride film) having a thickness of about 50 nm is formed on the insulating film 52 by using the CVD method.

Also, without forming the insulating film 52, the insulating film 5
The protective film 7 may be formed directly on the substrate 1. here,
Although the damascene process of embedding the fuse 12 in the groove has been described, the fuse 12 may be formed by depositing a metal on the insulating film 51 and processing the metal by an anisotropic etching method, for example, an RIE method. . When using the RIE method,
Since fluorine or the like is contained in the etchant gas, fluorine is inevitably added to the insulating film 51. Therefore, in this case, it is not necessary to intentionally add fluorine when forming the insulating film 51.

Next, as shown in FIG. 5, an insulating film 131 (for example, a silicon oxide film) containing fluorine having a thickness of about 600 nm is formed on the nitride film 7 by using the CVD method.
Next, at a predetermined position on the upper surface of the insulating film 131, a depth of 60 nm
A groove of about a degree is formed, and a metal wiring is buried in the groove.

Next, as shown in FIG. 6, a 300 nm thick film containing fluorine is formed on the insulating film 131 by CVD.
An insulating film 132 (for example, a silicon oxide film) is formed. Next, the silicon nitride film 10 having a thickness of about 300 nm is formed on the insulating film 132 by using the CVD method. Next, a photosensitive polyimide 11 is formed thereon and patterned into a predetermined shape. Finally, using the patterned polyimide 11 as a mask, an opening 14 is formed by etching and removing the silicon oxide film 13 to a predetermined thickness using an anisotropic etching method such as an RIE method. The view after this step has already been shown in FIG. Also,
FIG. 3 shows a case where the upper surface of the nitride film 3 is etched away.
This is shown in (2).

Thereafter, if necessary, the fuse is blown by irradiating the fuse with a laser. The thickness X of the silicon oxide film 13 to which fluorine is added above the fuse 12 is not limited to a predetermined thickness, as long as the thickness can be such that the fuse can be blown.

Since the nitride film 7 is a dense film, the opening 14
Of water that has entered from above can be prevented. Therefore, the film is not limited to the nitride film as long as it can prevent water from entering. Also,
Although a metal fuse has been described above as an example, a metal fuse may be used.

This embodiment is configured as described above.
In this embodiment, the dielectric constant can be reduced by adding fluorine to an insulating film such as a silicon oxide film. In this case, the moisture that has entered through the opening 14 chemically reacts with the fluorine added to the silicon oxide film 13 to generate strongly acidic fluorine. However, in this embodiment, since the nitride film 7 is provided above the fuse 12 made of metal,
Even if hydrofluoric acid is generated in the silicon oxide film 13, the fuse 12 can be protected without corrosion. Further, since the moisture that has entered through the opening 14 penetrates only to the upper surface of the dense nitride film 7, fluorine is added to the silicon oxide film 5, but hydrofluoric acid is generated in the silicon oxide film 5. Not done.

When hydrofluoric acid is generated in the silicon dioxide 13, the metal wiring 8 is eroded. However, since the metal wiring is usually thicker than the metal fuse, it is unlikely that the metal wiring will break even if it is eroded by hydrofluoric acid. Therefore, there is no problem even if the metal wiring 8 is slightly eroded by hydrofluoric acid.

Next, a second embodiment will be described with reference to the drawings. FIG. 7 shows a case where the present invention is applied to a logic-embedded DRAM. As shown in FIG. 7, a sectional view of a DRAM section, a logic section, and a fuse section is shown. In the DRAM section, diffusion layers 23 and 24 are formed adjacent to the gate electrode 16 serving as a word line. Diffusion layer 23 is electrically connected to storage node 50, and storage node 50 is electrically isolated from Pwell 55 by insulating film 56. The storage node 50 and the plate electrode 54 form a capacitor with the capacitor insulating film 59 interposed therebetween. The elements are electrically isolated by the element isolation insulating film 53. Further, the diffusion layer 24 is connected to a wiring 25 serving as a bit line. The wiring 26 is used as a backing word line, and a metal wiring 27 used as a data line is further provided thereon.

In the logic section, diffusion layers 51 and 52 are formed adjacent to the gate electrode 16, and diffusion layers 57 and 58 are formed adjacent to the gate electrode 160.
Diffusion layers 57 and 58 are used for wiring 25 used as bit lines.
And the wiring 25 may also be connected to the wiring 26. The wiring 26 is connected to the wirings 27, 28, 29. In the fuse section, the fuse 12 is formed using the wiring 28. Also, an opening 14 is formed.

When a nitride film is used for the protective film 7, the nitride film 7 has a high dielectric constant, so that a parasitic capacitance is formed. However, according to the present embodiment, since the protective film 7 is formed only in the fuse portion, no parasitic capacitance is formed in portions other than the fuse portion.

Although the nitride film 7 is located above the fuse 12 as shown in FIG. 3, the nitride film 7 may surround the fuse 12 as shown in FIG. Further, as shown in FIG. 9, the nitride film 7 is in contact with the fuse 12, and otherwise, the lower surface of the fuse 12 and the lower surface of the nitride film 7 may coincide. Further, as shown in FIG. 10, the lower surface of nitride film 7 and the upper surface of the fuse may coincide. As shown in FIGS. 8 to 10, since the fuse 12 is protected by the dense nitride film, it is not eroded by the strongly acidic hydrofluoric acid.

[0034]

According to the semiconductor device or the manufacturing method according to the present invention, it is possible to provide a semiconductor device in which a fuse is not corroded even if fluorine is added to reduce a dielectric constant, and a method of manufacturing the same. You can do it.

[Brief description of the drawings]

FIG. 1 shows a simple block diagram of a DRAM.

FIG. 2 shows a simple circuit diagram of a row decoder.

FIG. 3 is a sectional view of a fuse portion according to the first embodiment.

FIG. 4 shows a part of the manufacturing process of the present invention according to the second embodiment.

FIG. 5 shows a part of the manufacturing process of the present invention according to the second embodiment.

FIG. 6 shows a part of the manufacturing process of the present invention according to the second embodiment.

FIG. 7 shows a part of the manufacturing process of the present invention according to the second embodiment.

FIG. 8 is a sectional view of a fuse portion according to a third embodiment.

FIG. 9 is a sectional view of a fuse portion according to a fourth embodiment.

FIG. 10 is a sectional view of a fuse portion according to a fifth embodiment.

FIG. 11 is a top view of a conventional fuse portion.

FIG. 12 is a top perspective view of a conventional fuse.

FIG. 13 is a cross-sectional view of a conventional fuse portion.

[Explanation of symbols]

 Reference Signs List 4 semiconductor substrate 5, 13 silicon oxide film 7, 10 nitride film 8 metal wiring 11 polyimide 12 fuse 14 opening

Claims (10)

[Claims] A first insulating film having a metal wiring formed at a predetermined depth from an upper surface; a protective film formed on the first insulating film; and a protective film formed on the protective film. And a second insulating film containing fluorine. 2. A first insulating film having a metal wiring formed at a predetermined depth from an upper surface and containing fluorine, a protective film formed on the first insulating film, A second insulating film formed on the protective film. A first insulating film; a metal wiring formed on the first insulating film; an upper surface and a side surface of the metal wiring; and a first insulating film on which the metal wiring is not formed. A semiconductor device, comprising: a protective film formed on a film; and a second insulating film containing fluorine formed on the protective film. 4. A first insulating film containing fluorine, a metal wiring formed on the first insulating film, and upper and side surfaces of the metal wiring and the metal wiring are not formed. A semiconductor device comprising: a protective film formed on a first insulating film; and a second insulating film formed on the protective film. 5. A semiconductor device having a metal wiring formed at a predetermined depth from an upper surface, comprising: an insulating film containing fluorine; and a protective film formed to surround the metal wiring. Semiconductor device. 6. A first insulating film having a metal wiring formed at a predetermined depth from an upper surface, a protective film formed on the first insulating film, and formed on the protective film. But a second insulating film not formed above the metal wiring and containing fluorine. 7. The semiconductor device according to claim 1, wherein said metal wiring is a metal fuse. 8. The semiconductor device according to claim 1, wherein said protective film is not formed except in the vicinity of said metal wiring. 9. A step of forming a metal wiring in a groove formed on an upper surface of the first insulating film; a step of forming a second insulating film on the first insulating film; A method for manufacturing a semiconductor device, comprising: forming a protective film on an insulating film; and forming a third insulating film containing fluorine on the protective film. 10. A step of forming a metal wiring in a first insulating film; a step of forming a protective film on the first insulating film; and a second step of forming a protective film containing fluorine on the protective film. A method of manufacturing a semiconductor device, comprising: forming an insulating film, and removing the second insulating film above the metal wiring to expose the protective film.