JPH11260796A - Etching method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce damage without deteriorating etching speed and working form by etching residual polycrystalline silicon by plasma having low saturation ion current density, before a base oxide film is exposed, when plasma etching is performed with specified saturation ion current density. SOLUTION: Polycrystalline silicon 21 formed on a gate oxide film 23 is etched by using plasma having specified saturation ion current density, e.g. 2.4 mA/cm<2> . When polycrystalline silicon 21 comes to exist on an LOCOS 22 and a gate oxide film 23, the residual polycrystalline silicon 21 is etched by using plasma having saturation ion current density, e.g. 1.1 mA/cm<2> , lower than the specified saturation ion current density. Changeover of saturation ion current density is performed by experience before about 10% of time when the etching of the polycrystalline silicon 21 on the gate oxide film 23 is ended. As a result, damage can be reduced, and etching speed and form are not deteriorated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an etching method, and more particularly to a semiconductor surface treatment process using plasma, which causes damage to a wafer due to charges such as ions and electrons in plasma (hereinafter referred to as "charge-up damage"). The present invention relates to an etching method suitable for reducing the above-mentioned factor.

[0002]

2. Description of the Related Art As a method of reducing charge-up damage, as described in Japanese Patent Application Laid-Open No. H5-129094,
There is known a method of controlling a magnetic field applied to plasma to eliminate bias of the plasma and performing uniform etching in a wafer surface to reduce damage.

[0003]

The mechanism by which charge-up damage occurs is roughly classified into macroscopic damage caused by non-uniform electric potential in the wafer surface and electric potential in a fine pattern formed on the wafer. There is microscopic damage caused by non-uniformity. In the method disclosed in Japanese Patent Application Laid-Open No. 5-129094, in which the plasma density is made uniform on the wafer, macroscopic damage can be reduced, but microscopic damage cannot be reduced. At present, the processing dimensions of semiconductor devices are becoming smaller than 0.5 μm, and the problem of microscopic damage is increasing in semiconductor devices with such miniaturization.

[0004] A mechanism for generating microscopic damage will be described below with reference to FIG. FIG. 3 shows a cross-sectional structure of a sample which is a semiconductor wafer targeted by the present invention. In the plasma etching, the ionization accelerated in the vertical direction is made incident on the sample, thereby promoting the etching reaction and achieving anisotropic processing. On the other hand, the electrons in the plasma are not accelerated and have a small mass, so that the components of the random thermal motion are large and are incident on the sample in random directions. Therefore, for example, if there is a pattern (FIG. 3) composed of repeating fine lines and spaces corresponding to the wiring portion of the element, the electrons collide with the side wall of the photoresist 20 of the pattern and do not reach the groove bottom. Since the ions are perpendicularly incident on the sample surface, they reach the bottom of the dense pattern (polycrystalline silicon 21). Therefore, in the fine pattern, the photoresist 2
The 0 side wall is negatively charged, and the groove bottom is positively charged. Generally, the wiring portion is connected to the gate oxide film of the transistor, and when the etching of the polycrystalline silicon 21 is completed and the line and the space pattern are electrically separated from other portions,
The potential at the bottom of the groove is applied to the oxide film of the gate, and if this potential is increased to some extent, dielectric breakdown of the gate occurs, resulting in damage.

[0005] An object of the present invention is to solve the above problems and to provide an etching method capable of reducing microscopic damage.

[0006]

According to the experiments of the inventors,
It has been found that the microscopic damage depends on the saturation current density of ions incident on the wafer, and that reducing this value reduces the microscopic damage. However, the condition where the ion saturation current density is small does not always correspond to the condition where the etching speed or the shape is good. As a result of further experiments, the microscopic damage was
It has been found that the etching occurs intensively when the underlying oxide film appears after the etching of the material to be processed such as polycrystalline silicon.

From this, in order to reduce damage without impairing the etching speed and the processed shape, etching is performed by using plasma having a predetermined saturated ion current density, and the etching of the polycrystalline silicon is terminated to expose the underlying oxide film. Before you do
This is achieved by etching the remaining polycrystalline silicon with a plasma having a saturation ion current density lower than the predetermined saturation ion current density.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a diagram showing a flow of the etching process. FIG. 2 is an overall view of a plasma etching apparatus to which the present invention is applied. FIG. 3 is a diagram showing a cross-sectional structure of a sample to be etched, FIG. 4 is a diagram showing a cross-sectional shape of a sample used in the present invention during etching, and FIG. FIG. 6 is a diagram showing a cross-sectional shape at the time of completion, and FIG. 6 is a diagram showing a cross-sectional shape at the time of completion of etching of polycrystalline silicon.

FIG. 2 shows an etching apparatus utilizing a microwave and a magnetic field as means for generating plasma. In FIG. 2, 1 is a magnetron for generating microwaves, 2 is a rectangular waveguide for transmitting microwaves, 3 is a circular conversion waveguide, 4 is a cylindrical cavity, 5 is a solenoid coil for generating a magnetic field, 6 Is a microwave transmitting layer (for example, a quartz flat plate), 7 is a vacuum vessel, 8 is a sample stage on which a wafer as a sample is placed, 1
Reference numeral 0 denotes a high-frequency power supply for accelerating ions, and reference numeral 11 denotes an electrostatic attraction power supply for electrostatically attracting a wafer placed on a sample stage. Inside the vacuum vessel 7, a cylindrical insulating cover 12 made of a plasma-resistant material such as quartz or ceramic is provided on the inner surface. Further, an earth electrode 13 is arranged near the sample table 8 inside the vacuum vessel 7. The ground electrode 13 is electrically connected to the buffer chamber 14 at a ground potential, and has a function of securing a path through which the current of the high-frequency power supply 10 flows through the plasma.

In the apparatus configured as described above, during the etching process, the gas introduction path 16 is inserted into the vacuum vessel 7 evacuated by a vacuum exhaust device such as a vacuum pump and a turbo molecular pump (not shown). The process gas is introduced from the gas outlet of the shower plate 17 through the, and energy is applied to the process gas to form a plasma.

By adjusting the magnetic field by the solenoid coil 5 to make the cyclotron motion of the electrons equal to the frequency of the microwave, the electrons can be moved to the electron cyclotron resonance (Electron cyclotron).
Cyclotron Resonance (hereinafter abbreviated as “ECR”), efficiently transmitting energy and generating high-density plasma 1
5 can be generated. After the plasma is generated, the wafer is suctioned to the sample table 8 by the electrostatic suction power supply 11. After the wafer is attracted to the sample table 8, the high frequency power source 1 is further applied to the sample.
The bias voltage is applied by 1 to start the processing.

FIG. 3 shows details of the wafer. FIG.
In the above, the LOCOS (Local Oxidat
An ion of silicon (22) (film thickness of 4000) and a gate oxide film 23 (film thickness of 45) are formed. LOCOS
22, a polycrystalline silicon 21 (film thickness 1700 °) is formed on the gate oxide film 23, and a photoresist 20 (film thickness 10000 °) is formed on the polycrystalline silicon 21.

Damage can be reduced by etching with the apparatus shown in FIG. 2 according to the step diagram shown in FIG. First, the polycrystalline silicon 21 formed on the gate oxide film 23 is converted to a predetermined saturated ion current density (for example, 2.4
(mA / cm2) plasma is etched (FIG. 3). Etching is performed until a predetermined time comes (FIG. 4). Here, the predetermined time is a time during which the polycrystalline silicon 21 exists over the LOCOS 22 and the gate oxide film 23. After a predetermined time has elapsed, the remaining polycrystalline silicon 21 is etched by plasma having a saturation ion current density lower than the predetermined saturation ion current density (for example, 1.1 mA / cm 2), thereby reducing charge-up damage. (Fig. 5). The reason that the damage can be reduced is that the total charge accumulated in the gate oxide film 23 before and after the etching of the polycrystalline silicon 21 where the charge-up damage is intensively generated is reduced by changing the saturation ion current density to a low value. Because you can. If the switching of the saturated ion current density is performed about 10% before the time when the etching of the polycrystalline silicon 21 on the gate oxide film 23 is completed, it is possible to reduce the damage and to impair the etching speed and shape. Absent.

There are several specific methods for lowering the saturated ion current density. The method includes increasing the pressure of the etching gas, lowering the power of the magnetron 1 for generating plasma, or changing the current flowing through the coil 5 to change the magnetic field. It is practical to increase the distance between the high density plasma portion and the sample 19.

FIG. 7 shows the relationship between the value of the saturated ion current density and the charge-up damage. The vertical axis in FIG. 7 is the frequency of occurrence of damage to the damage evaluation test wafer, and the horizontal axis is the saturated ion current density. Saturated ion current density is 2 mA /
cm2 or less, the rate of occurrence of test wafer damage is 10
% Or less. The test wafer is designed to detect the damage with high sensitivity. If the damage occurrence rate of the test wafer is 10% or less, the damage is at a level that does not cause any problem in the processing of the actual wafer. Therefore, the saturated ion current density after the etching step switching is 2
It is desirable to set it to mA / cm 2 or less.

In this embodiment, polycrystalline silicon is taken as an example of a substance to be etched, but the same result can be obtained by etching a metal such as aluminum. Further, the charge-up damage occurring in the transistor becomes more serious as the thickness of the gate oxide film 23 becomes thinner. Therefore, the effect of the transistor to which the present invention is applied becomes more remarkable as the gate oxide film becomes thinner, and is particularly suitable for processing an element having a gate oxide film thickness of 5 nm or less. This method can be applied not only to a semiconductor etching apparatus using microwaves but also to other apparatus such as a plasma etching apparatus using a radio wave band.

[0017]

According to the present invention, by etching with plasma having a predetermined saturated ion current density, it is possible to perform etching under process conditions that emphasize shape. Thereafter, before the underlying oxide film is exposed near the etching end point of the polycrystalline silicon, the remaining polycrystalline silicon is etched by plasma having a saturated ion current density lower than the predetermined saturated ion current density. This allows
There is an effect that charge-up damage can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of an etching process which is an etching method of the present invention.

FIG. 2 is a configuration diagram showing an example of a plasma processing apparatus for performing the etching method of the present invention.

FIG. 3 is a diagram showing a cross-sectional shape of a sample on which the etching method of the present invention is performed.

FIG. 4 is a diagram showing a cross-sectional shape of a sample during processing by the etching method of the present invention.

FIG. 5 is a diagram showing a cross-sectional shape of a sample near a just etch by the etching method of the present invention.

FIG. 6 is a diagram showing a cross-sectional shape of a sample at the end of etching by the etching method of the present invention.

FIG. 7 is a diagram showing a relationship between a saturated ion current density and damage occurrence frequency.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Magnetron, 2 ... Waveguide, 3 ... Circular rectangular waveguide, 4 ... Cylindrical cavity part, 5 ... Solenoid coil, 6 ...
Microwave transmission window, 7: vacuum container, 8: sample stage, 10
... High frequency power supply, 11 ... Electrostatic power supply, 12 ... Insulator cover, 13 ... Earth electrode, 14 ... Buffer room, 15
... high-density plasma, 16 ... gas introduction path, 17 ... shower plate, 19 ... wafer, 20 ... photoresist, 21 ... polycrystalline silicon, 22 ... LOCOS, 23 ... Gate oxide film, 24 ... Si substrate, 25 ... First step, 2
6 ... time setting, 27 ... second step.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuro Ono Kasamatsu, Kamamatsu, Yamaguchi Prefecture 794, Higashi-Toyoi Inside the Kasado Plant of Hitachi, Ltd.

Claims (18)

[Claims] In the etching of a conductive layer or a semiconductor layer formed on a base oxide film on a wafer using plasma generated in a vacuum vessel, the semiconductor layer is incident on the wafer before the base oxide film is exposed. An etching method characterized by switching to a condition in which the saturated ion current density is lowered. 2. An etching method according to claim 1, wherein said condition for reducing said saturated ion current density is 2 mA / cm 2 or less. 3. The etching method according to claim 1, wherein the conductor layer or the semiconductor layer formed on the base oxide film includes at least a polycrystalline silicon layer. 4. The etching method according to claim 1, wherein the conductor layer or the semiconductor layer formed on the base oxide film includes at least an aluminum layer. 5. The etching method according to claim 1, wherein a pressure of a gas forming said plasma is increased to reduce a density of a saturated ion current incident on said wafer. 6. The etching method according to claim 1, wherein an output of a power supply for generating said plasma is reduced to reduce a saturated ion current density incident on said wafer. 7. An etching method according to claim 1, wherein a distance between said region having a high plasma density and said wafer is increased to reduce a density of a saturated ion current incident on said wafer. 8. The etching method according to claim 1, wherein a pressure of a gas for forming the plasma is increased, an output of a power supply for generating the plasma is reduced, and a region between the region having a high plasma density and the wafer. An etching method for reducing the density of the saturated ion current incident on the wafer by simultaneously using at least two of these conditions. 9. The etching method according to claim 1, wherein the switching to the condition in which the saturated ion current density is lowered is performed about 10% before the time when the etching of the conductor layer or the semiconductor layer is completed. Etching method. 10. The etching method according to claim 1, wherein the thickness of the underlying oxide film on the wafer is 5 nm or less. 11. A method for etching Poly-Si formed on a base oxide film by using plasma, wherein a saturated ion current density (Ion Current Flux: ICF) is 2 mA.
/ Cm2 or less of the remaining Poly-Si
Etching method characterized by etching. 12. A method for etching Poly-Si formed on a base oxide film by using plasma, wherein etching is performed by using plasma having a predetermined saturation ion current density, and the Poly-Si is formed near an end point of the etching. With a small amount of the Poly-Si remaining before the oxide film is exposed, the remaining Poly-S is removed by plasma having a saturation ion current density lower than the predetermined saturation ion current density.
An etching method characterized by etching i. 13. The etching method according to claim 12, wherein plasma having a saturation ion current density lower than the predetermined saturation ion current density is generated by increasing the processing pressure. 14. An etching method according to claim 12, wherein the plasma having a saturated ion current density lower than the predetermined saturated ion current density is generated by lowering the microwave output. 15. An etching method according to claim 12, wherein the plasma having a saturation ion current density lower than the predetermined saturation ion current density is generated by lowering the output of a source RF for generating the plasma. 16. An etching method according to claim 12, wherein the plasma having a saturation ion current density lower than the predetermined saturation ion current density is generated at a distance between an electron cyclotron resonance surface and a wafer surface. 17. The etching method according to claim 12, wherein the plasma having a saturation ion current density lower than the predetermined saturation ion current density generates plasma at a distance between a plasma source and a wafer surface. 18. An etching method according to claim 12, wherein said plasma having a saturated ion current density lower than said predetermined saturated ion current density generates plasma using a plurality of conditions according to claim 13-17.