JPH08264509A - Method and device for surface treatment - Google Patents

Abstract

PURPOSE: To suppress the electronic shading phenomenon and notching in dry etching by changing the applying bias voltage from the usually sinusoidal wave voltage to a high-speed positive pulse voltage. CONSTITUTION: A pulse power source 19 is arranged, replacing the usually sinusoidal wave high-frequency power source, and a positive pulse voltage with a build-up speed of 10<3> V/μs or higher is applied. When the input voltage is lower than the plasma potential, positive charge-up occurs on the fine pattern bottom plane on a substrate 16 by the electronic shading phenomenon, and when an attracting power source 5 is negative, a positive ion 10 is diagonally applied on an SG pattern 18 and notching occurs. When the input voltage becomes higher than the plasma potential, an electron 11 is accelerated to reach the fine pattern bottom plane and positive charge-up is neutralized. The voltage of the attracting power source 5 is also preferably positive so as to prevent notching. Thus, troubles due to the charge-up phenomenon generated by gate etching are suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment apparatus using plasma, and more particularly to an application mechanism of a bias voltage applied to an object to be processed (sample) and an electrostatic adsorption mechanism used to hold the sample on a sample table. .

[0002]

2. Description of the Related Art First of all, the most typical example of a conventional bias applying method called RF bias is shown in FIG.
Shown in The sample 1 to be etched is connected to a high frequency power source 3 via a capacitor 2 caused by an electrostatic attraction mechanism.
A high-frequency power source 3 applies a sinusoidal voltage as shown in FIG. At this time, since the electrons supplied from the plasma 4 are several tens of times larger than the ions, negative charges are accumulated on the sample side of the capacitor 2. Due to this capacitor charge, a negatively shifted voltage appears on the substrate as shown in FIG. This negative voltage accelerates the positive ions, which are etching species, and makes them vertically incident on the substrate, thereby enabling vertical etching. Also, as another idea, patent 10
A method using a pulse waveform voltage as a bias has already been devised in Japanese Patent No. 95402 and Japanese Patent Laid-Open No. 6-61182.

On the other hand, as a sample holding mechanism, in the surface treatment using plasma, a method of holding the sample on the sample table by an electric attraction force (electrostatic attraction) is used. FIG. 5 shows the configuration of a monopole type electrostatic chuck which is one of the most common examples of the electrostatic attraction mechanism. In this apparatus, in addition to the high frequency bias voltage supplied from the high frequency voltage source 3, a DC voltage of about several hundreds of V supplied from the electrostatic attraction constant voltage source 5 is applied to the sample stage 6. Due to this negative voltage, a positive charge 8 is supplied from the plasma 4 to the side surface of the sample 1 of the insulating ceramic plate 7. Negative charge 9 is generated on the side of one of the sample stands due to a mirror image phenomenon.
The sample is attracted to the sample table by the Coulomb force of the positive charge 8 on the sample side of the insulating ceramic 7 and the negative charge 9 on the sample table side. Other known examples include those that supply a positive DC voltage from an electrostatic attraction power supply, and a dipole electrostatic chuck that applies both positive and negative voltages.

However, none of these known examples pay attention to the importance of two relations between the bias voltage waveform and the polarity of the electrostatic attraction DC voltage.

[0005]

When the voltage of the substrate bias waveform shown in FIG. 3 is applied to process the fine pattern, a charge-up phenomenon called electron shading occurs at the bottom surface of the fine pattern. This charge-up phenomenon causes various problems in plasma etching. One of the most important problems is the occurrence of local abnormal side etching (notching) in the processing of gate polysilicon. This charge-up phenomenon and notching mechanism are shown in FIG.

In the substrate bias waveform of FIG. 3, since the positive voltage for accelerating the electrons in the positive cycle in which the electrons enter the sample is almost 0, the electrons are hardly accelerated and enter the substrate. Since the ions 10 are accelerated and enter the sample, they reach the bottom surface of the fine pattern, while the electrons 11 are not accelerated and areotropically incident on the sample, so that the fine pattern is blocked by the mask 12 and reaches the bottom surface. I can't. Therefore, in the fine pattern, the mask is charged up negatively and the bottom surface is charged up positively (electron shading phenomenon). Due to this charge-up, the ions 10 that are the etching species are repelled and come into the side surface of the pattern. The ions 10 incident on this side surface cause local abnormal side etching 15 (notching) at the interface between the polysilicon layer 13 and the underlying silicon oxide film layer 14. The occurrence of the notching 15 is more remarkable in the case of processing the pattern 18 (SG pattern) which is in conduction with the substrate than in the pattern 17 (FG pattern) which is not in conduction with the substrate 16. Development is an urgent task.

Further, it is known that the charge-up due to the electron shading phenomenon is a main factor causing the gate deterioration by causing the breakdown of the gate insulating film and the V _t shift in addition to the shape abnormality such as notching. .

The present invention provides a method of suppressing an electronic shading phenomenon and solving various problems caused by the phenomenon. In particular, the present invention is effective in suppressing notching in the SG pattern.

[0009]

The present invention suppresses the electron shading phenomenon and notching by changing the bias voltage applied in plasma etching from a conventional sinusoidal voltage to a high-speed pulsed voltage. is there. Specifically, as shown in FIG. 1, the bias power source is replaced with a conventional sinusoidal high frequency power source, a pulse power source 19 is installed, and a rising speed of 10 ³ V / μs or more is set as a bias voltage from the pulse power source. Apply pulse voltage.

Further, a positive DC voltage is applied from the electrostatic attraction power source 5.

[0011]

First, consider the case where a high-speed pulse waveform voltage as shown in FIG. 9 is applied from the pulse power supply 19 in the plasma etching apparatus of FIG. In this case, a bias waveform as shown in FIG. 9 appears on the substrate. While the input voltage is 0,
The substrate is in a potential state called floating potential, which is about 20 V lower than the plasma potential. During this time, positive charge-up due to electronic shading occurs on the bottom surface of the fine pattern on the substrate as in the case of FIG. On the other hand, the substrate has a potential higher than the floating potential while the positive pulse voltage is applied. When the potential during the application of the pulse voltage is higher than the plasma potential, the voltage of the difference between the substrate potential and the plasma potential (hereinafter referred to as electron acceleration voltage) accelerates the electrons 11 to the bottom surface of the fine pattern as shown in FIG. Incident. As a result, the positive charge-up on the bottom surface of the fine pattern is neutralized. As a result, it is considered that various problems caused by electronic shading such as notching are reduced.

Next, the conditions of the pulse for generating this electron acceleration voltage on the substrate will be examined.

First, let us consider the rising speed of the pulse. When the rising speed of the pulse is slow, a voltage drop occurs in the capacitor 2 between the sample 1 and the pulse power source 19 in FIG. 7 due to the electron current flowing from the plasma until the substrate potential reaches the plasma potential. No positive potential is generated. Therefore, in order to generate the electron acceleration voltage on the substrate, the rising speed of the pulse must be higher than the speed of the voltage drop due to the electron current shown in Formula 1.

[0014]

[Equation 1]

Assuming that the electron temperature T _e is 2 eV, the plasma density n _e is 10 ¹¹ / cm ^3, and the capacitance value of the electrostatic chuck is 30 pF / cm ² , the voltage drop rate given by the equation 1 is obtained. And about 10 ³ V / μs. Therefore, it is considered that a rising speed of at least 10 ³ V / μs or more is required to generate the electron acceleration voltage on the substrate.

Next, the magnitude of the pulse voltage will be examined. It is assumed that there is no voltage drop of the substrate during the pulse rise and a positive voltage of the same magnitude as the pulse voltage is generated on the substrate by applying the pulse bias. A voltage having a magnitude obtained by subtracting a difference of about 20 V between the plasma potential and the floating potential from this positive voltage is the actual electron acceleration voltage. If the electron acceleration voltage has a value sufficiently larger than the lateral kinetic energy of the electron of about 3 eV, the electron can be vertically incident. Such an electron accelerating voltage needs to be at least 30 V or higher. Therefore, as a voltage actually applied to the substrate, a positive pulse voltage of at least 30V + 20V, that is, 50V or more is required.

Finally, consider the pulse width. When the width of the positive pulse is long, the substrate potential decreases at a rate of 10 ³ V / μs due to the inflow of electrons while the positive voltage is applied, and returns to the floating potential after a certain period of time. Assuming that the magnitude of the pulse voltage is 10 ² V, the time required for the substrate potential to reach the floating potential is 0.1 μs, and the pulse width is preferably shorter than this.

In the apparatus of FIG. 7, a high-speed pulse waveform voltage as shown in FIG. 8 was applied from the bias pulse power source 19 to actually process the polysilicon gate. As a result, notching of the FG pattern was completely eliminated. On the other hand, it was found that the SG pattern did not completely eliminate notching. We have found that the difference between the SG pattern and the FG pattern in the notching occurrence is due to the electrostatic chuck power supply 5
It was found that it was due to the negative DC voltage supplied from the. The mechanism by which this difference occurs is shown in FIG. When a negative voltage of −500 V is applied as the electrostatic attraction voltage,
Compared to the surface of the base oxide film 14, the substrate 16 on the back surface has 20
A potential as low as V appears. Therefore, S that has continuity with the substrate
The G pattern has a negative potential of about 20 V compared to the surface of the oxide film 14 around the G pattern, and the positive ions 10 as etching species are bent toward the SG pattern 18 side, and are easily obliquely incident. It was found that the oblique incidence of these ions promotes notching. Therefore, the device of FIG. 7 and the electrostatic attraction power supply 5
We devised a device as shown in FIG. When a positive voltage of, for example, +500 V is applied from the electrostatic attraction power supply 5 using this device, the SG pattern is the surrounding oxide film 1
The potential is about 20 V higher than that of the surface of No. 4. Therefore,
It becomes difficult for the positive ions 10 to obliquely enter the SG pattern 18. Furthermore, the application of the pulse bias eliminates the charge-up on the bottom surface of the pattern, so that notching does not occur in either the SG pattern 18 or the FG pattern 17. Even when the polarity of the electrostatic attraction voltage is positive, the electrostatic attraction force is the same as that when the polarity is negative.

[0019]

【Example】

(Embodiment 1) FIG. 7 shows an example of an apparatus in which the pulse bias of the present invention is applied to a microwave etching apparatus for processing polysilicon for gates. In this device, a microwave generated by the magnetron 20 is introduced into the discharge tube 22 through the waveguide 21, and a high-density plasma can be generated by electron cyclotron resonance of the introduced microwave and the magnetic field created by the coil 23. Has become. As a sample 1 to be etched, a 6-inch size Si wafer was thermally oxidized to deposit a polysilicon film, and a resist mask was formed on the polysilicon film. The sample 1 is connected to an electrostatic attraction constant voltage source 5 and a bias pulse power source 19 via an electrostatic attraction insulating ceramic 7 having an electrostatic capacity of 30 pF / cm ² . Pulse power supply 1
A terminating resistor 24 having a resistance value (40 ohms or more and 60 ohms or less) equivalent to the internal resistance of the power supply is attached between the output terminal of 9 and the ground. In order to observe the bias waveform, an oscilloscope 25 having a frequency band upper limit value of 100 MHz or more was attached to the output end of the bias pulse power supply 19. In this device, a negative voltage of −500 V is applied from the electrostatic attraction constant voltage source 5, the bias power source 19 has a magnitude of 100 V, a rising speed of 10 ³ V / μs or more, and a pulse as shown in the waveform of FIG. Width 100 n
The sample was etched by applying a pulse voltage of s or less and a duty ratio of 0.5%. The processed shape at this time is shown in FIG. For comparison, FIG. 14 shows a processed shape when a conventional RF bias (800 KHz, 5 W) is applied. When the polysilicon is processed by the conventional method, large notching 15 is observed in both the SG pattern 18 and the FG pattern 17. On the other hand, when the pulse bias application method of the present invention is used, no notching is observed in the FG pattern 17,
It can be seen that the SG pattern 18 also reduces the occurrence of notching.

In this experimental apparatus, a pulse voltage of 100
The pulse width was fixed to 100 ns at V, and the sample was etched by changing the pulse repetition frequency. FIG. 15 shows the relationship between the pulse repetition frequency and notching magnitude at this time.
Shown in The notching size decreases as the pulse repetition frequency increases, and the duty ratio (pulse width × repetition frequency × 100) becomes 0.5%.
With the above, the size of notching is minimized. In particular, in the case of the FG pattern 22, notching completely disappears at a duty ratio of 0.5% or more. The change in notching size at this time is shown in FIG. 16 with the abscissa representing the selection ratio of the underlying silicon oxide film. For comparison, the result in the case of the conventional RF bias etching is also shown in the same figure. Pulse duty ratio is 5%
In the following cases, etching with a higher selection ratio and less notching can be realized than in the case of RF bias.

Next, the pulse width and duty ratio were fixed, the magnitude of the pulse voltage was changed, and the change in the size of the notch was examined. The result is shown in FIG. The magnitude of notching decreases with increasing pulse voltage. Further, the effect of suppressing notching is saturated when the magnitude of the pulse voltage is 50 V or more. Therefore, it is understood that the magnitude of the pulse voltage should be at least 50 V or higher.

Further, as shown in FIG. 1, the polarity of the electrostatic attraction power source was changed, and a voltage of +500 V was applied from the power source to etch polysilicon. The processed shape at this time is shown in FIG. In this case, not only the FG pattern 17
Notching also completely disappeared in the SG pattern 18. In this case, the bias voltage and the electrostatic attraction positive voltage were applied separately, but the same effect can be achieved by directly applying the voltage of the waveform in which the electrostatic attraction positive voltage is superimposed on the bias voltage to the sample stage. can get.

The effect of this embodiment is not limited to the microwave etching apparatus, and the same effect can be obtained in a plasma etching apparatus using another discharge method such as an inductively coupled high frequency plasma etching apparatus and a helicon plasma etching apparatus. is there.

Example 2 FIG. 19 shows WSi / Poly-
It is a figure which shows the flow of the process of processing a Si gate. First, C
N + Poly-S is formed on the silicon oxide film by the VD method.
i, WSi, and SiO ₂ are sequentially deposited. Next, a photoresist is applied and patterned by a lithographic technique to form a resist pattern. Using this resist pattern as a mask, the SiO ₂ layer is CF ₄ / O ₂
Anisotropic dry etching is performed with mixed gas plasma.
Next, WSi layer by Cl ₂ gas plasma and Poly
Anisotropic dry etching both Si layers. Next, the resist pattern is removed by downflow ashing. Next, the remaining SiO ₂ / WSi / Poly-Si
Is used as a mask to perform light doping of phosphorus to form an n-light doped drain layer in the Si substrate. Next, deposit SiO ₂ by the CVD method,
By etching back, a spacer portion is formed on the outer periphery of the gate. Heavy doping of phosphorus is performed using this spacer portion as a mask to form an n + diffusion layer. Of the manufacturing steps in FIG. 19, WSi / Poly-Si
The pulse bias of Example 1 was applied to the film etching process. FIG. 20 shows a timing diagram of bias application in this WSi / Poly-Si etching process.
Since a high bias voltage is required for etching the WSi layer after the start of discharge, an RF bias that can easily create a high bias was applied. Followed by Poly-S
Since the etching of the i layer requires etching with high selectivity and less notching, the bias applied after the etching of the Poly-Si layer was started was switched from the RF bias to the pulse bias. The gate manufactured in this manner has a higher processing dimension accuracy than that of the conventional method, so that the variation in the effective channel length is small. Further, deterioration and V _t shift gate insulating film by jersey up is small, it can be produced gate of stable characteristics.

[0025]

By using the present invention, charge-up and local abnormal etching that occur during gate etching are suppressed.

[Brief description of drawings]

FIG. 1 is a diagram showing an example in which both a pulse bias application and an electrostatic adsorption mechanism of the present invention are applied to a microwave plasma etching apparatus.

FIG. 2 is a diagram showing a configuration of a conventional etching apparatus used for applying an RF bias.

FIG. 3 is a diagram showing a bias input waveform when a conventional RF bias is applied.

FIG. 4 is a diagram showing a substrate bias waveform when a conventional RF bias is applied.

FIG. 5 is a diagram showing an example of a conventional electrostatic attraction mechanism.

FIG. 6 is a diagram showing a mechanism of occurrence of local abnormal side etching (notching) in processing a gate polysilicon.

FIG. 7 is a diagram showing an example in which the pulse bias application of the present invention is applied to a microwave plasma etching apparatus.

FIG. 8 is a diagram showing a bias input waveform in the case of applying a pulse bias according to the present invention.

FIG. 9 is a diagram showing a substrate bias waveform in the case of applying a pulse bias according to the present invention.

FIG. 10 is a diagram showing a mechanism of suppressing an electron shading phenomenon by a pulse bias.

FIG. 11 is a diagram showing a mechanism that causes a difference in notching between an SG pattern and an FG pattern.

12 is a diagram showing an example of a bias waveform applied in the device of FIG.

FIG. 13 is a diagram showing a processed shape of polysilicon etched using the bias application method of the present invention.

FIG. 14 is a view showing a processed shape of polysilicon etched using a conventional RF bias application.

FIG. 15 is a diagram showing a relationship between pulse repetition frequency (duty ratio) and notching magnitude.

FIG. 16 is a diagram showing a relationship between a selection ratio of a base silicon oxide film and a notching size in each of the present invention and the conventional method.

FIG. 17 is a diagram showing the relationship between the magnitude of pulse voltage and the magnitude of notching.

FIG. 18 is a view showing a processed shape of polysilicon etched using the pulse bias application and electrostatic adsorption method of the present invention.

FIG. 19 is a diagram showing a processing step of a WSi / Poly-Si gate.

FIG. 20 is a diagram showing an example of a bias timing diagram when the present invention is applied to a WSi / Poly-Si etching step.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sample, 2 ... Capacitor, 3 ... Bias high frequency voltage source, 4 ... Plasma, 5 ... Electrostatic adsorption constant voltage source, 6 ... Sample stage, 7 ... Insulating ceramic plate, 8 ... Positive charge, 9 ... Negative charge ,
10 ... Positive ions, 11 ... Electrons, 12 ... Resist mask,
13 ... Polysilicon layer, 14 ... Base silicon oxide film layer,
15 ... Notching, 16 ... Substrate, 17 ... FG pattern,
18 ... SG pattern, 19 ... Bias pulse power supply, 2
0 ... Magnetron, 21 ... Waveguide, 22 ... Discharge tube, 23
… Coil, 24… Termination resistor, 25… Oscilloscope

Claims (15)

[Claims] 1. A dry etching for etching a sample by holding an object to be processed placed on a sample table in a reduced pressure processing chamber by an electric attraction force and supplying a plasma to the object to be processed and applying a bias voltage. In the method
A dry etching method characterized by applying a positive pulse waveform voltage as a bias. 2. The dry etching method according to claim 1, wherein the electric attraction force is generated by applying a positive voltage to the sample stage. 3. The magnitude of the positive voltage according to claim 2 is 50.
Dry etching method characterized by being 0 V or more 4. An object to be processed placed on a sample table in a decompression processing chamber is held by an electric attraction force, and plasma is supplied to the object to be processed and a bias voltage is applied to etch the object to be processed. In the dry etching method, a voltage having a waveform in which a positive pulse waveform voltage and a positive or negative DC voltage are superposed is applied as the bias voltage. 5. A dry etching method for etching an object to be processed by supplying plasma to the object to be processed placed on a sample table in a decompression processing chamber and applying a bias voltage to the object to be processed. A dry etching method characterized by switching from a voltage having a waveform to a voltage having a positive pulse waveform. 6. Claim 1, claim 2, claim 3, claim 4
Alternatively, the magnitude of the pulse waveform voltage according to claim 5 is 5
A dry etching method characterized by being 0 V or more. 7. The pulse width according to claim 6 is 100 n.
A dry etching method characterized by being s or less. 8. The duty ratio of the pulse according to claim 7 is 5
% Or less, a dry etching method. 9. The rising speed of the pulse according to claim 8 is 10 ³ V
/ Μs or more, a dry etching method characterized by the above. 10. A step of forming an oxide film on a substrate, CVD
A step of sequentially depositing a first gate layer, a second gate layer, and a SiO ₂ layer on the oxide film by a method, and applying a photoresist on the SiO ₂ layer and patterning by a lithography technique to form a resist pattern. And the above-mentioned SiO 2 using the resist pattern as a mask.
Anisotropic dry etching of the _two layers, anisotropic dry etching of both the second gate layer and the first gate layer, removing the resist pattern by downflow ashing, remaining SiO ₂ , A step of forming an n-light doped drain layer in a substrate by lightly doping phosphorus or boron with the first gate layer and the second gate layer as a mask, SiO by a CVD method
_{A step} of depositing _two films and etching back the SiO ₂ film to form a spacer portion on the outer periphery of the gate; and performing heavy doping of phosphorus or boron using the spacer portion as a mask to diffuse n + into the substrate. In the gate manufacturing process, which consists of the steps of forming layers,
A dry etching method, wherein the etching method of claim 1, claim 2, claim 3 or claim 4 is applied to the step of anisotropically dry etching both the second gate layer and the first gate layer. . 11. A dry unit having a mechanism for holding an object to be processed placed on a sample table in a reduced pressure processing chamber by an electric attraction force, a means for supplying plasma to the object to be processed, and a means for applying a bias voltage. In the etching equipment,
A dry etching apparatus comprising a power supply capable of generating a pulsed positive voltage as part of a means for applying a bias. 12. The dry etching apparatus according to claim 10, comprising a power source capable of applying a positive voltage to a sample stage as a part of a mechanism for generating the electric attraction force. 13. A dry etching apparatus comprising a resistor between an output terminal of a power source for generating the pulse voltage according to claim 10 and the ground. 14. A bias power supply according to any one of claims 10 and 11 is provided with both a power supply capable of generating a pulsed voltage and a power supply capable of generating a sinusoidal voltage. A dry etching apparatus characterized in that 15. A dry etching apparatus comprising an oscilloscope having a frequency band upper limit value of 100 MHz or more.