JPH11258309A - Scan storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scan storage device which prevents malfunction of the shift due to a clock skew while a circuit scale or design man-hours are suppressed. SOLUTION: A scan storage device 100 is provided with a plurality of pairs of a flip-flop 10, which is composed of a master latch circuit 11 and of a slave latch circuit 12, and of a selector 20. In a shift operation, a scan enable signal SE is set to an 'H'-level state, and scan data D1 from a flip-flop at a previous stage is selected by the selector 20 so as to be output. When a clock signal CK rises, the scan data D1 is latched by the master latch circuit 11. In a state that the clock signal CK is at an 'H' level and at a timing which is delayed from the timing of its rise, the scan enable signal SE falls. The slave latch circuit 12 is shifted to a through mode, and the scan data D1 is output toward a flip-flop at a nest state. Thereby, the malfunction of the shift due to a clock skew is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scan storage device having a plurality of flip-flops each including two latch circuits, a master latch circuit and a slave latch circuit, which are connected in series.

[0002]

2. Description of the Related Art Heretofore, a method called a scan path test method has been known as one of the techniques for facilitating the test of a semiconductor integrated circuit. In this scan path test method, a part or the whole of a flip-flop, which is a sequential circuit provided in a semiconductor integrated circuit, has a shift register configuration capable of scanning (this is referred to as a scan path chain), and a test is performed by shifting this shift register. This is a method of sending data inside, or taking internal data into this shift register and sending it out by shifting, thereby facilitating the test.

In the scan path test method, when setting data in flip-flops in a shift register configuration, data is set by a shift operation synchronized with one or a plurality of system clocks. A clock skew occurs between system clocks, and a malfunction may occur in taking in data. Therefore, as a countermeasure against clock skew, a buffer for obtaining a hold time is inserted between adjacent flip-flops, or a scan path chain is configured by reconnecting scan cells in descending order of clock delay. In addition, the circuit is modified so that the asynchronous circuit block in the circuit operates synchronously with the system clock during the test operation.

[0004]

However, in the scan path test method, in the technique of inserting a buffer for countermeasures against clock skew as described above, if the buffer is inserted between all the flip-flops, the area overhead increases, while the selective overhead is increased. The problem is that the static analysis of the circuit is required if it is inserted into the.

In the technique of re-connecting scan cells to reconfigure a scan path chain for countermeasures against clock skew, circuit design reverts due to the need for information on delay data after placement and routing. There is a problem. Furthermore, in the case of a synchronous circuit of an asynchronous circuit block, a clock delay increases due to a circuit modification for converting an asynchronous circuit portion into a synchronous circuit, and special consideration for clock skew is further required, thereby increasing design man-hours. There is.

SUMMARY OF THE INVENTION In view of the above circumstances, it is an object of the present invention to provide a scan storage device in which a shift erroneous operation due to clock skew is prevented while a circuit area and a design man-hour are suppressed.

[0007]

According to the present invention, there is provided a scan storage device comprising: a serially connected master having a latch mode for latching input data and a through mode for outputting input data as it is; A flip-flop comprising two latch circuits, a latch circuit and a slave latch circuit, and data input to the flip-flop is converted into scan data, which is an output of the preceding flip-flop, and an internal circuit in accordance with a predetermined scan enable signal. Scan memory having a plurality of pairs of selectors for selectively switching to normal data, which is a signal obtained from the memory, and having a capture mode for taking normal data into a flip-flop and a shift mode for shifting data taken into the flip-flop In the device, the master Latch circuit is in the shift mode,
The latch mode and the through mode are alternately repeated with a predetermined first clock signal, and the slave latch circuit shifts to the through mode at a later timing than the master latch circuit shifts to the latch mode in the shift mode. As described above, the present invention is characterized in that it operates with the second clock signal having a different phase from the first clock signal.

In the scan storage device according to the present invention, in the shift mode, the scan data from the preceding flip-flop is first latched by the master latch circuit, and after a lapse of a predetermined time, the scan data latched by the master latch circuit is transmitted to the slave latch circuit. And output to the next flip-flop. In this manner, the timing at which the scan data is output from the flip-flop at the preceding stage is delayed from the timing at which the scan data is input to the scan flip-flop. Even if clock skew occurs between adjacent scan cells, Data can be shifted reliably, and malfunction of the shift due to clock skew is prevented. Also, as in the prior art, a buffer is inserted between flip-flops in order to prevent a malfunction in shift due to clock skew,
Alternatively, the circuit scale and the design man-hour can be suppressed without increasing the design man-hour.

In the shift mode, the selector generates a scan enable signal as a scan enable signal at a timing at which the master latch circuit latches the scan data selected by the selector while the selector is selecting scan data. A clock generation circuit for providing a clock signal and generating the second clock signal for switching the mode of the slave latch circuit based on the scan enable signal and the first clock signal for switching the mode of the master latch circuit; It is effective to prepare.

With such a clock generation circuit,
A second clock signal for outputting the scan data latched by the master latch circuit from the slave latch,
It can be generated by a simple circuit based on the scan enable signal and the first clock signal.

[0011]

Embodiments of the present invention will be described below. FIG. 1 is a diagram showing a part of a circuit of an embodiment of the scan storage device of the present invention. The scan storage device 100 shown in FIG. 1 includes a plurality of pairs of flip-flops 10 and selectors 20 (FIG. 1 shows one pair as an example). In addition, the scan storage device 1
00 also includes a clock generation circuit 30.

The flip-flop 10 includes a master latch circuit 11 composed of clocked inverters 11a, 11b and 11c, and a clocked inverter 12a, 1c.
2b, an inverter 12c and a buffer 12d and a slave latch circuit 12 and two latch circuits are connected in series. Each of the master latch circuit 11 and the slave latch circuit 12 has a latch mode for latching input data and a through mode for outputting input data as it is.

The selector 20 responds to a positive-phase scan enable signal SB from a clock generation circuit 30 to be described later, and outputs scan data D1 as an output of a preceding flip-flop (not shown) and normal data as a signal obtained from an internal circuit. D0 is selectively switched and output. The clock generation circuit 30 receives the input clock signal CK
And an inverter 30b that inverts the first negative-phase clock signal CN to generate a first positive-phase clock signal CB. . The master latch circuit 11 is switched between the latch mode and the through mode by the first negative-phase clock signal CN and the first positive-phase clock signal CB. The clock generation circuit 30 also includes an inverter 31a for inverting the input scan enable signal SE to generate an inverted-phase scan enable signal SN and an inverter 31a for inverting the inverted-phase scan enable signal SN to output a positive-phase scan enable signal SB. An inverter 31b for generating is also provided. Further, the clock generation circuit 30 includes:
A NOR gate 32a that receives a first negative-phase clock signal CN and a positive-phase scan enable signal SB to generate a second negative-phase clock signal CNSN, and inverts the second negative-phase clock signal CNSN to produce a second Normal phase clock signal CNS
An inverter 32b for generating B is provided. The slave latch circuit 12 is switched between the latch mode and the through mode by the second negative-phase clock signal CNSN and the second positive-phase clock signal CNSB.

The scan storage device 1 constructed as described above
00 has a capture mode in which the normal data D0 is taken into the flip-flop 10 and a shift mode in which the data taken in the flip-flop 10 is shifted. Hereinafter, the operation of the scan storage device 100 shown in FIG. 1 will be described with reference to FIG. 1 and FIG.

FIG. 2 is a timing chart of the scan storage device shown in FIG. The clock signal CK, the normal data D0, the scan data D1, and the scan enable signal SE are input to the scan storage device 100. First, the shift operation in the shift mode will be described. In the scan storage device 100, as shown in FIG.
It is assumed that an “L” level is input as the level and the clock signal CK. Since the scan enable signal SE is at the "H" level, the inverters 31a and 31b output the "L" level reverse phase scan enable signal SN and the "H" level normal phase scan enable signal SB, respectively. The positive-phase scan enable signal SB at the “H” level is input to the selector 20, and therefore, the selector 20 outputs the scan data D 1
The scan data D1a shown in FIG. 2 is selectively output.

Since the clock signal CK is at the "L" level, the first negative-phase clock signal CN and the first normal-phase clock signal C are supplied from the inverters 30a and 30b, respectively.
“H” level and “L” level are output as B. Therefore, the transfer gates 11a and 11b are on and off, and the master latch circuit 11 is in the through mode. Therefore, the scan data D1a input to the flip-flop 11 is inverted by the inverter 11c via the clocked inverter 11a, and is input to the slave latch 12.

Since the NOR gate 32a receives the "H" level as both the first negative-phase clock signal CN and the positive-phase scan enable signal SB, the NOR gate 32a outputs the second negative-phase clock signal CNSN from the NOR gate 32a. Level is output, and the 'L' level is inverted by the inverter 32b, and the inverter 32b outputs the 'H' level as the second positive-phase clock signal CNSB. Therefore, the transfer gates 12a,
12b is in an off state and an on state. Therefore, regardless of the scan data D1a input to the flip-flop 10, the data held in the slave latch 12 is output as the data Q of the flip-flop 10.

Next, the clock signal CK changes from "L" level to "H" level while the scan enable signal SE remains at "H" level. Then, the changed "H" level is inverted by the inverter 30a, the "L" level is output from the inverter 30a as the first inverted-phase clock signal CN, and the "L" level is further inverted by the inverter 30b to be inverted. An “H” level is output from 30b as the first positive-phase clock signal CB. Therefore, the clocked inverters 11a and 11b
Turns off and on. Therefore, the scan data D1a input to the master latch circuit 11 is latched by the master latch circuit 11.

On the other hand, the "L" level is input to the NOR gate 32a as the first positive-phase clock signal CN.
Since the “H” level is input as the positive-phase scan enable signal SB, the second negative-phase clock signal CNSN
Level “L”, the second positive-phase clock signal CNSB
And the “H” level continues to be output. Therefore, the data latched in the slave latch circuit 12 is continuously output as the data Q of the flip-flop 10.

Next, while the clock signal CK is at the "H" level, the scan enable signal E changes from the "H" level to the "L" level. Then, the inverters 31a,
From 31b, a negative-phase scan enable signal SN of “H” level and a positive-phase scan enable signal S of “L” level
B is output. Since the selector 20 receives the “L” level positive-phase scan enable signal SE, the selector 20 selectively outputs the normal data D0a among the normal data D0 from the internal circuit.

The NOR gate 32a receives the "L" level as the first positive-phase clock signal CN and the "L" level as the positive-phase scan enable signal SB. , The “H” level is output as the second negative-phase clock signal CNSN, and the “L” level is output as the second positive-phase clock signal CNSB from the inverter 32b. Therefore, the transfer gates 12a and 12b are turned on and off, the slave latch circuit 12 is set in the through mode, and the scan data D1a latched by the master latch circuit 11 is supplied to the flip-flop 10
Is output as output data Q.

Further, while the scan enable signal SE is at the "L" level, the clock signal CK changes from the "H" level to the "L" level. Then, the clocked inverter 1 sets the “H” level as the first negative-phase clock signal CN and the “L” level as the first positive-phase clock signal CB.
1a and 11b, and the clocked inverter 11
a and 11b are turned on and off, and the master latch circuit 11 is set in the through mode. The "L" level as the second negative-phase clock signal CNSN and the "H" level as the second positive-phase clock signal CNSB are input to the clocked inverters 12a and 12b, so that the clocked inverters 12a and 12b are turned off. State and the ON state, and the slave latch circuit 12 continues the latch mode. Here, since the scan enable signal SE is at the “L” level, the selector 20 selects the normal data D0a, and the normal data D0a is transmitted through the master latch circuit 11 to the slave latch circuit 12.
However, since the slave latch circuit 12 is in the latch mode, the scan data D1a continues to be output as the output data Q of the flip-flop 10.

Next, when the scan enable signal SE goes to the "H" level again and the clock signal CK rises thereafter, the master latch circuit 11 receives the scan data D1b in the next cycle. For this reason,
Normal data D is stored in the master latch circuit 11 by the shift operation.
0a is not taken in. On the other hand, in the capture operation, the scan enable signal SE goes low. Since the “L” level is input to the NOR gate 32a, the second negative-phase clock signal CNSN, the second positive-phase clock signal CNSB, and the first negative-phase clock signal CN,
The first positive-phase clock signal CB has a relationship of complementary signals having different levels from each other. Since the “L” level scan enable signal SB is input to the selector 20,
The normal data D0c shown in FIG. 2 is selectively output from the selector 20. When the clock signal CK is at the “L” level, the master latch circuit 11 and the slave latch circuit 1
2 is in a through mode and a latch mode. Here, when the clock signal CK changes from “L” level to “H” level, the master latch circuit 11 and the slave latch circuit 1
2 is a latch mode or a through mode, and the normal data D0c latched by the master latch circuit 11 is output.

The scan storage device 100 will now be described with reference to FIG.
3 shows a truth table in the timing chart shown in FIG.

[0025]

[Table 1]

Here, Pn and Qn shown in Table 1 represent latch data latched by the master latch circuit 11 and the slave latch circuit 12, respectively. As shown in Table 1,
In the capture mode, the scan enable signal SE is set to 'L' level. In this state, the clock signal CK
Rises, the master latch circuit 11 and the slave latch circuit 12 enter the latch mode and the through mode. Therefore, the master latch 11 latches the "L" level or "H" level normal data D0 of the current cycle as data Pn. And the latched data Pn
Is output from the slave latch circuit 12 as data of an “L” level or an “H” level. Next, when the clock signal CK falls, the master latch circuit 11 and the slave latch circuit 12 enter the through mode and the latch mode, and the master latch 11 outputs the normal data D of the “L” level or the “H” level in the next cycle.
0 is output, while data D0 of the current cycle is latched in slave latch 12 and output as data Qn.

On the other hand, in the shift mode, when the clock signal CK rises while the scan enable signal SE is at the "H" level, the master latch circuit 11 enters the latch mode, and the slave latch 12 remains in the latch mode. Therefore, the scan data D1 of the current cycle is stored in the master latch circuit 11 as the data Pn.
The data Qn of the previous cycle latched by the slave latch circuit 12 is output from the slave latch circuit 12. Next, when the scan enable signal SE falls while the clock signal CK is at the “H” level, the master latch circuit 11
Is latched as it is and the slave latch circuit 12
In the through mode, the slave latch circuit 12 outputs the data Pn of the current cycle latched in the master latch circuit 11. Next, when the clock signal CK falls while the scan enable signal SE is at the “L” level, the master latch circuit 11 enters the through mode and the slave latch 12 enters the latch mode. Therefore, the data Pn of the current cycle is continuously output from the slave latch circuit 12.

In this embodiment, in the shift mode,
When the scan enable signal SE is at the “H” level, the scan data D1 is taken into the master latch circuit 11 at the rise of the clock signal CK, and after a predetermined time has elapsed while the clock signal CK remains at the “H” level, The scan data D1 captured by the master latch circuit 11 at the fall of the scan enable signal SE is
Since the data is output to the flip-flop of the next stage, each scan cell in the scan path chain can surely capture the data captured one cycle before the scan cell of the previous stage, thereby preventing a shift malfunction. You. Also, there is no need to insert a buffer between flip-flops or to increase the number of design steps in order to prevent a shift malfunction caused by clock skew, which is only necessary to connect flip-flops in sequence, and to reduce the circuit scale and design. Man-hours can be reduced.

In this embodiment, in the shift mode, the master latch circuit 11 outputs the first inverted clock signal C
N, the mode shifts to the latch mode with the first positive-phase clock signal CB, and after the lapse of a predetermined time, the scan enable signal SE falls to shift the slave latch circuit 12 to the through mode. The second positive-phase clock signal CNSB is generated to prevent a shift malfunction due to clock skew. However, the present invention is not limited to this. In the shift mode, the master latch circuit is switched to the latch mode by a predetermined first clock signal. The slave clock circuit is operated by a second clock signal having a phase different from that of the first clock signal so that the slave latch circuit shifts to the through mode at a timing delayed from the shift to the latch mode. Should be fine.

[0030]

As described above, according to the present invention,
Shift malfunction due to clock skew is prevented while the circuit size and design man-hours are suppressed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a circuit of an embodiment of a scan storage device of the present invention.

FIG. 2 is a timing chart of the scan storage device shown in FIG.

[Explanation of symbols]

Reference Signs List 10 flip-flop 11 master latch circuit 11a, 11b, 12a, 12b clocked inverter 11c, 12c, 30a, 30b, 31a, 31b, 3
2b Inverter 12 Slave latch circuit 12d Buffer 30 Clock generation circuit 32a NOR gate 100 Scan storage device

Claims (2)

[Claims] 1. A flip-flop comprising two latch circuits, a master latch circuit and a slave latch circuit connected in series, each having a latch mode for latching input data and a through mode for outputting input data as it is. A selector for selectively switching data input to the flip-flop between scan data as an output of the preceding flip-flop and normal data as a signal obtained from an internal circuit, according to a predetermined scan enable signal; A plurality of pairs, and a scan storage device having a capture mode for taking normal data into a flip-flop and a shift mode for shifting data taken into the flip-flop, wherein the master latch circuit comprises a predetermined first mode in the shift mode. Clock signal With repeated alternately Chimodo and through mode, the slave latch circuit,
In the shift mode, the master latch circuit operates with a second clock signal having a phase different from that of the first clock signal so that the master latch circuit shifts to the through mode at a timing later than the shift timing to the latch mode. A scan storage device, characterized in that: 2. In a shift mode, a clock for generating a timing at which the master latch circuit latches scan data selected by the selector while the selector is selecting scan data as a scan enable signal to the selector. A clock generation circuit that supplies a signal and switches the mode of the slave latch circuit based on the scan enable signal and the first clock signal that switches the mode of the master latch circuit. The scan storage device according to claim 1, wherein: