JPH11252055A - Error correction device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an error correction device in a comparatively simple constitution which can correct errors in received data. SOLUTION: This device includes a level discrimination circuit 12 which compares the instantaneous value of a level signal that bears frame data where a CRC check bit is added with a reference value Eth for level discrimination and outputs a 1st frame data signal; an error estimation circuit 13 which generates an error estimation output when the instantaneous value of the level signal is included in an estimation range of Eth+ to Eth- existing near the reference value Eth; an inverting circuit 14 which outputs a 2nd frame data signal obtained by inverting the value of the relevant bit of the 1st frame data signal in response to the generation of the error estimation output; error detection circuits 17 and 18 which detect the presence or absence of errors by performing the frame CRC checks to the 1st and 2nd frame data signals respectively; and a selection circuit 19 which selects a frame data signals without errors based on the presence or absence of both frame data signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing erroneous conversion when demodulating a digital signal by discriminating a modulated signal carrying digital information.

[0002]

2. Description of the Related Art In a portable communication terminal device, it is required that the circuit configuration be reduced in size and power consumption and be high in transmission quality. For this reason, it is necessary to take measures against reception errors with respect to multipath and noise. For example, a diversity reception method is known as a measure for reducing a multipath reception error. As a countermeasure against noise, there is a method in which transmission data is subjected to an error correction encoding process in advance so that an error can be corrected on a receiving side, and then transmitted, and after reception, an attempt is made to reproduce missing data using an error correction processing circuit. used.

[0003]

However, since the diversity receiving system has a dual receiving system, the circuit is complicated and expensive, and it is not preferable for a portable terminal requiring a small and inexpensive system. Also, when the missing data can be reproduced on the receiving side, the transmitting side requires an error correction coding device, and the receiving side also requires an arithmetic unit with high processing capability for data reproduction. It is not preferable for a device requiring a small size and a low price, such as a telephone device.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an error correction device capable of correcting received data with a relatively simple configuration.

Another object of the present invention is to provide a portable telephone device having a relatively inexpensive error correction device.

[0006]

In order to achieve the above object, an error correction apparatus according to the present invention compares an instantaneous value of a level signal carrying frame data obtained by adding an error check bit to data of a predetermined bit length with a reference value. A level discriminating circuit for discriminating the level and outputting a first frame data signal, and an error estimating circuit for generating an error estimating output when an instantaneous value of the level signal is within an error estimating range near the reference value. A data change circuit for outputting a second frame data signal obtained by changing a value of a corresponding bit of the first frame data signal in response to the generation of the error estimation output; and the first and second frames. An error detection circuit that performs an error check on the frame of each data signal to detect the presence / absence of an error; and the first and the second based on the presence / absence of the error.
And a selection circuit for selecting a frame data signal having no error from among the frame data signals.

With this configuration, when sampling a level signal, two frame data are generated within a range where a sampling error near a threshold can occur, and a frame to be used based on the result of the frame error check is generated. Data can be selected. As a result, error correction becomes possible.

[0008] Preferably, the error check is performed by CRC (Cy
clic Redundancy Check) or FCS (Frame Check)
Sequence) error check. Such a frame (block) inspection method is a so-called PHS (Personal Handy-phon).
e System) is used as a communication method in digital telephones and the like, and thus is suitable for use in demodulation circuits of digital telephones.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a basic circuit of the present invention. FIG. 2 shows an example of data with error check bits carried by the modulated signal. FIG. 3 shows the signal waveform of each part.

In FIG. 1, a modulated signal is supplied to a detector 11. This modulated signal carries digital information that has been subjected to error check processing in advance. One frame of digital information carried by the modulated signal is, for example, as shown in FIG.
This data bit is converted to m data bits by CRC.
(Cyclic Redundancy Check) An n-bit check bit for check is added. The value of the n check bits is
M using a generator polynomial, for example, X ¹⁶ + X ¹² + X ⁵ +1
It is obtained by performing processing on the data bit portion of the bit.

The modulated signal is demodulated by a detector 11 into a level signal. The instantaneous value Vn of the level signal is compared with the reference value Eth at a predetermined sampling cycle by the level discriminator 12 and digitized, and is supplied to the bit inverter 14 and the buffer memory 15 as a first data signal (DATA1). You. The buffer memory 15 can be composed of, for example, a shift register.

The level signal is also supplied to an error estimating circuit 13. The error estimating circuit 13 determines that the instantaneous value Vn of the level signal is a value near the predetermined reference value Eth.
When the value of Eth- is obtained, an error estimation output is generated. This error estimation output is provided to the bit inverter 14. The bit inverter 14 inverts a corresponding bit of the first data signal according to the error estimation output. This data is output to the buffer memory 16 as a second data signal (DATA2). The buffer memory 15 can be composed of, for example, a shift register.

The first memory temporarily stored in the buffer memory 15
The data signal is subjected to a CRC check for each frame by the CRC checker 17 to determine the presence or absence of an error.
In the CRC check, a frame composed of m-bit data and n-bit check bits is divided by using the same generator polynomial as that on the transmission side, for example, X ¹⁶ + X ¹² + X ⁵ +1, and the remainder is obtained. Do. The CRC checking unit 17 gives the result of the error check (the presence or absence of an error) to the data selection circuit 19 by an error detection signal. The second data signal once held in the buffer memory 16 is subjected to a CRC check for each frame by the CRC checker 18, and
It is determined whether there is an error. The CRC checker 18 gives the result of the error check (the presence or absence of an error) to the data selection circuit 19 by an error detection signal. Data selection other circuit 1
Reference numeral 9 selects, from the first and second data signals (frame data), data for which no error is detected, and supplies the selected data to a next-stage circuit (not shown), for example, a data processing circuit.

As shown in FIG. 3, the above-described error correction device compares the amplitude value Vn obtained by extracting the detected signal (level signal) at each sample point with the estimated error values Eth + and Eth-, and | Vn If | <| Eth |, it is determined that there may be an error, and the bit is inverted. As a result, a data output without error estimation (DATA1) and a data output with error estimation (DATA2) are obtained. A CRC error check is performed on these two data outputs, and one without a CRC error is used as reproduction data.

If both data outputs are determined to be errors, the following measures can be taken. For example, when the present invention is applied to a data communication device, it is possible to request the other party to retransmit the error data. In the case of a mobile phone device, both error data are not used. In this case, some data of the voice is lost, but interpolation can be performed even if some of the voice data is missing, and there is little hindrance to conversation.

FIG. 4 shows an example of a frame error rate (FER) characteristic with respect to an error correction threshold. In the figure, the horizontal axis represents the normalized amplitude, the vertical axis FER1 represents the frame error rate without error estimation (DATA1), and the FER2 represents the frame error rate with error estimation (DATA2).
In this example, Eb (energy per bit) / No (1
(Per Hz) = 12 dB. As shown by the error rate ratio curve in the figure, the threshold value Eth is 0.0
When it is near 8, it can be seen that error detection is most efficient in this case.

FIG. 5 shows a frame error rate (FER) characteristic when the error correction according to the present invention is performed and a FER characteristic when no correction is performed in a white Gaussian noise (AWGN) environment. The horizontal axis shows the Eb / No value, and the vertical axis shows the FER value. As shown in the figure, Eb / No
Is 12 dB, the error corrected one can reduce the frame error rate by about 60%.

FIGS. 6 and 7 show a portable telephone, for example, P
9 shows an application example of the present invention to an HS.

FIG. 6 schematically shows a PHS receiving system, wherein 1 is an antenna for converting an incoming radio wave from a base station (not shown) into a high-frequency signal, 2 is a high-frequency section for extracting a phase-modulated signal from a carrier signal, 3 is a demodulation unit for demodulating a digital signal from a phase modulation signal (π / 4 shift QPSK signal),
4 is a digital signal processing TDMA / TDD (TimeDiv
ision Multiple Access / Time Division Duplex) processing unit, 5 is an audio decoder that demodulates the separated digital signal into an audio signal, and 6 is a speaker that converts the audio signal into audio.

FIG. 7 shows a demodulation unit 3 and a TDMA / CD processing unit 4 to which the present invention is applied.

The phase modulated signal demodulated by the high frequency section 2 carries digital information, and is separated by a phase detection circuit 31 into an I (synchronous) signal component and a Q (quadrature) signal component. Both signals are supplied to the decision circuit 32 and the error correction circuit 3
3 is supplied.

The determination circuit 32 determines the phase of the modulation signal at a predetermined sampling period based on the levels of the I signal and the Q signal, and outputs a 2-bit digital value sequence associated with each phase as first data. . This first data output is sent to the bit inversion circuit 34 and the TDMA / TDD processing unit 4.
Is supplied to the buffer memory 41.

The error estimating circuit 33 determines each level of the I signal and the Q signal based on the sampling period. When the sampling level of the I signal is within the error estimation range, I
Generate a signal error estimation output. Further, when the sampling level of the Q signal is within the error estimation range, a Q signal error estimation output is generated. When an error estimation output is generated, the bit inversion circuit 34 inverts the bit value of the first data corresponding to the supplied error estimation output to generate a second data output. The second data output is TDMA / T
The data is output to the buffer memory 42 of the DD processing unit 4. An error check is performed on the frame portion of each data held in the buffer memories 41 and 42 by the CRC check circuits 43 and 44, respectively. Data selection circuit 4
5 selects output data of the buffer memories 41 and 42 based on the respective error determination results of the CRC check circuits 43 and 44. The selected frame data is TDMA / TD
The received data is sent to the D processing unit 4 and separated from the communication channel. Further, the received data is demodulated into an audio signal by the decoder 5, and audio is output from the speaker 6.

As described above, in the PHS communication method, CR
Since the frame data subjected to the C inspection is transmitted and received, it is possible to easily incorporate the error correction device of the present invention.

[0025]

As described above, according to the error correction apparatus of the present invention, it is possible to reduce the level fluctuation error with a relatively simple configuration. In particular, it is preferably used for a portable communication terminal device.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a basic configuration of the present invention.

FIG. 2 is an explanatory diagram illustrating a configuration of frame data.

FIG. 3 is an explanatory diagram illustrating a signal waveform of each unit.

FIG. 4 is a graph illustrating the determination of an error estimation threshold Eth.

FIG. 5 is a graph illustrating an improvement in a frame error rate according to the present invention.

FIG. 6 is a block diagram illustrating a PHS receiving system.

FIG. 7 illustrates an example in which the present invention is applied to a PHS receiving system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Detection circuit 12 Level discrimination circuit 13 Error estimation circuit 14 Bit inversion circuit 15, 16 Buffer memory 17, 18 CRC check circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuhiko Seki 2-12-7 Hatchobori, Chuo-ku, Tokyo Inside Uniden Corporation

Claims (3)

[Claims] A level discrimination for outputting a first frame data signal by discriminating a level by comparing an instantaneous value of a level signal corresponding to frame data obtained by adding an error check bit to data of a predetermined bit length with a reference value. A circuit; an error estimating circuit for generating an error estimation output when an instantaneous value of the level signal is within an error estimation range near the reference value; A data change circuit for outputting a second frame data signal in which the value of the corresponding bit of the frame data signal is changed, and performing a frame error check on each of the first and second frame data signals to detect the presence or absence of an error An error detection circuit for performing the selection, and selecting the error free frame data signal of the first and second frame data signals based on the presence or absence of the error. An error correction device comprising: a circuit; 2. The error check is a CRC error check,
The error correction device according to claim 1. 3. A digital telephone device comprising the error correction device according to claim 2 in a data demodulation system.