JP3121720B2 - Demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator, and more particularly to a demodulator for demodulating a digitally modulated signal used for, for example, FM multiplex broadcasting for mobile reception.

[0002]

2. Description of the Related Art In FM multiplex broadcasting, LMS is used as a modulation signal.
The K signal is used. The LMSK signal changes the amplitude of the MSK signal in accordance with the original broadcast signal, and is used for the purpose of reducing mutual interference. However, in the demodulator, the change in the amplitude is eliminated by a limiter or the like. LMSK
The signal becomes an MSK signal. The demodulation method of the MSK signal is roughly classified into a delay detection method and a synchronous detection method.

[0003] The two systems will be described. In the differential detection system, as shown in FIG. 4, demodulated data is obtained by multiplying an input signal and a signal obtained by delaying the input signal by one data period by a delay circuit 1 in a multiplier 2. Is obtained. On the other hand, in the periodic detection method, an input signal is input to multipliers 3 and 4 as shown in FIG. Further, the carrier reproducing circuit 5
Is input to the multiplier 3 and the
The phase is shifted by 90 degrees by the 0-degree phase shifter 6 and input to the multiplier 4. The data obtained by multiplying the input signal and the reproduced carrier by the multiplier 3 and the data obtained by multiplying the input signal by the 90-degree phase shift component of the reproduced carrier by the multiplier 4 are input to the data decoding circuit 7. Then, demodulated data is obtained from the data decoding circuit 7. At this time, the reproduced carrier from the carrier reproducing circuit 5 is reproduced by giving the data from the multipliers 3 and 4 to a PLL circuit included in the carrier reproducing circuit 5 to perform a PLL operation.

[0004] The feature of each detection method is as follows. Since the delay detection method simply delays and multiplies an input signal, demodulated data can be obtained immediately. On the other hand, in the synchronous detection method, it is necessary to reproduce the reproduction carrier by a PLL circuit included in the carrier reproduction circuit 5, and demodulated data cannot be obtained immediately because a PLL lock time exists. For the above reasons, when the input signal is interrupted due to fading in mobile communication, the delay detection method can obtain demodulated data faster than the synchronous detection method, and the delay detection method is more suitable for mobile communication. It can be said that there is. on the other hand,
In fixed reception, the differential detection method multiplies noise-containing input signals, while the synchronous detection method multiplies the input signal by a reproduced carrier containing almost no noise. It is known that characteristics are better. Therefore, in mobile reception, the delay detection method has better characteristics, and in fixed reception, the synchronous detection method has better characteristics. In other words, the delay detection method is suitable for mobile communication and the synchronous detection method is suitable for fixed reception. .

Therefore, it is only necessary to provide both the delay detection method and the synchronous detection method for switching. However, since manual switching is practically impossible, either of the methods is automatically performed according to the movement and stop of the vehicle. It is possible to choose.
In this case, an additional element such as a movement / stop sensor is required, which increases the cost. SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a demodulator capable of minimizing the occurrence of data errors with a small increase in cost.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a demodulator for demodulating a digitally modulated signal, the synchronous detecting means for synchronously detecting the digitally modulated signal, and the output of the synchronous detecting means.
First error correction means for receiving and correcting errors , delay detection means for delay-detecting a digital modulation signal, and output of the delay detection means
Error correction means for receiving and correcting errors, first error correction
For each packet of the output of the synchronous detection means based on the output of the means
Output from the first determination means and the second error correction means
Correction for each packet of the output of the delay detection means based on the power
Second determining means, first determining means, and second determining means for determining
Output of the first error correction means when both stages are determined to be correct
Is a demodulator that includes an output unit that outputs a signal.

[0007]

The LMSK signal which is a digital modulation signal is detected by the delay detecting means and the synchronous detecting means. No.
The first error correction means and the second error correction means respectively
Error correction based on output from synchronous detection means and delay detection means
Correct. The first determination means is based on the output of the first error correction means.
The correctness of the output of the synchronous detection means for each packet
Similarly, the second determining means also outputs the output of the second error correcting means.
The output of the delay detection means is determined for each packet based on the
Set. For example, output means including AND and OR
When the detection means of the detection means is correct, the delay detection means
Regardless of whether the output is correct or not, for example, the first packet buffer
The output of the first error correction means stored in
To the PU, when the output of the synchronous detection means is wrong
Is the number stored in the second packet buffer, for example.
(2) The output of the error correction means is given to the CPU. Note that the first
The second determining means may perform a CRC check on the packet obtained by the error correction output, check a parity added to the packet,
Whether the detection output is correct or not is determined by determining the state of the BIC of the packet.

[0008]

According to the present invention, it is possible to automatically switch to the correct detection output from the synchronous detection and the delay detection based on the error detection of the detection output. In comparison with the above, no extra element or the like is required and the cost can be reduced. In addition, FM multiplex signals can be received with good characteristics in both fixed reception and mobile reception, and demodulated data with few errors can be obtained. In particular, the effect is great in a situation where movement and stopping occur continuously in a car or the like.

The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0010]

1, a demodulator 10 of this embodiment includes an antenna 12. FIG. The FM radio wave received by the antenna 12 is given to the tuner 14, and a radio wave of a desired frequency is selected from the FM radio waves and detected. Then, the output from the tuner 14 is provided to a filter 16, and the filter 16 extracts only the LMSK signal which is an FM multiplex signal.

Here, the FM multiplex signal has a frame structure as shown in FIG. 2, for example. As shown in FIG. 2, one frame is composed of a matrix of 288 × 272 bits.
Each row is called a block, and one frame is composed of a block for transmitting 190 data and a block of 82 parity for transmitting parity in the column direction. A block for transmitting data includes a 190-bit packet, and a block for transmitting parity in the column direction includes a 190-bit parity packet. The frames are transmitted sequentially and continuously, and within one frame, the first block, that is, the block numbers 1 to 272, are sequentially transmitted.

At the head of each packet and parity packet, a 16-bit BIC (block identification code)
Is added. BIC has four types of BIC1 to BIC4
And each of the BIC1 to BIC4 has, for example, the bit pattern shown in FIG. FIG. 3 shows each of BIC1 to BIC.
4 bit patterns are shown in transmission order. An 82-bit parity is added to the end of each packet and the parity packet.

Returning to FIG. 1, the LMSK signal is applied to a limiter amplifier (or comparator) 18 to remove the amplitude component of the LMSK signal to obtain an MSK signal. The MSK signal is provided to the synchronous detector 20 and the delay detector 22, respectively. The synchronous detector 20 is configured, for example, as shown in FIG. 5 described above. The synchronous detector 20 synchronously detects the MSK signal,
The detection output (demodulated data) is supplied to the first error corrector 24, where error correction of the detection output is performed. In the error correction, an 82-bit parity and a 190-bit parity packet are used. The demodulated data after correction is the first C
It is provided to RC checker 26 and first packet buffer 28. In the first packet buffer 28, one packet (190 bits) of demodulated data is temporarily held.
Then, the first CRC checker 26 performs a CRC check of each packet using a 14-bit CRC code, and determines whether or not demodulated data is correct for each packet. If incorrect, the demodulated data cannot be used. Then, from the first CRC checker 26, a judgment result of correct / incorrect of demodulated data and a check end signal are output for each packet. The result of the determination as to whether the demodulated data is correct or not is given to AND gate 30, and its inverted output is given to AND gates 32 and 34. As a result of determining whether the demodulated data is correct or not, a high-level output indicating "correct data" is output when the demodulated data is correct, and a low-level output indicating "wrong data" is output when the demodulated data is incorrect. Check end signal is CRC end detector 3
6 given.

On the other hand, the delay detector 22 is configured, for example, as shown in FIG. 4 described above. The delay detector 22 performs delay detection of the MSK signal, and the detection output (demodulated data) is supplied to the second error corrector 42. The error correction of the detection output is performed.
Parity and parity packets are also used for this error correction. The demodulated data after error correction is provided to the second CRC checker 44 and the second packet buffer 46. The second packet buffer 46 temporarily holds demodulated data for one packet. The second CRC checker 44 uses a 14-bit CRC code to determine the CR of each packet.
A C check is performed to determine whether demodulated data is correct for each packet. And the second CRC checker 44
From the above, for each packet, the judgment result of the correct / incorrect of the demodulated data is inverted and given to the AND gate 34,
The check end signal is provided to the CRC end detector 36.

The CRC end detector 36 determines whether the first C
When the check is completed by both the RC checker 26 and the second CRC checker 44 and a check end signal is given from each of them, a CRC end signal is output to the first packet buffer 28 and the second packet buffer 46. The first packet buffer 28 and the second
The packet buffer 46 supplies demodulated data for one packet to the AND gates 30 and 32, respectively. If there is a high-level output indicating “positive data” from the first CRC checker 26, the AND gate 30 passes the demodulated data from the first packet buffer 28 and supplies the demodulated data to the CPU 40 via the OR gate 38. Can be AN
If there is a low-level output indicating "erroneous data" from the first CRC checker 26, the D gate 32 passes the demodulated data from the second packet buffer 46, and supplies the demodulated data to the CPU 40 via the OR gate 38. Can be The AND gate 34 outputs a high-level signal indicating that "demodulated data is erroneous" only when the low-level output indicating "erroneous data" is given from the first CRC checker 26 and the second CRC checker 44, respectively. The signal is output to the CPU 40. That is, the AND gate 34
Outputs a signal indicating whether the demodulated data provided to the CPU 40 is correct or not, and outputs a low-level signal if the demodulated data output to the CPU 40 is correct, and outputs a high-level signal if the demodulated data is incorrect. Therefore, the CPU 40 recognizes the correctness of the demodulated data based on the output from the AND gate 34. Then, the CPU 40 serving as a processor processes the demodulated data and supplies the processed data to the output device 48. The output device 48 is constituted by a display, for example, and outputs information according to demodulated data (FM multiplexed data).

In the demodulator 10, if the synchronous detection side is correct, the AND gate 30 outputs the demodulated data on the synchronous detection side, and if not, the AND gate 32 outputs the demodulated data on the delayed detection side. That is, the output of the normal demodulated data improves the characteristics. If both demodulated data are erroneous, the AND gate 34 outputs a high-level signal. If both demodulated data are erroneous, the demodulated data on the delay detection side is output to the CPU 40 in this embodiment. However, since this is meaningless data, the demodulated data on the synchronous detection side is output at this time. Is also good.

In the above-described embodiment, whether the demodulated data is correct or not is determined by the CRC check. However, the present invention is not limited to this. Parity or BIC added to the packet is used, or these are combined to demodulate. The correctness of the data may be determined. If the correctness of the demodulated data is determined by checking the parity, the first CRC
Instead of the checker 26 and the second CRC checker 44, an error detection circuit for checking parity may be used. When determining whether the demodulated data is correct or not based on the state of the BIC, a BIC detection circuit for detecting the state of the BIC may be used instead of the first CRC checker 26 and the second CRC checker 44.

In the above-described embodiment, the case where the LMSK signal used for FM multiplexing is used as the digital modulation signal has been described. However, the present invention is not limited to this case. However, it can be applied to all modulation schemes such as BPSK and QPSK that can be detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an illustrative view showing a frame configuration of an FM multiplex signal;

FIG. 3 is an illustrative view showing a bit pattern of a BIC;

FIG. 4 is a block diagram illustrating an example of a differential detection method.

FIG. 5 is a block diagram illustrating an example of a synchronous detection method.

[Explanation of symbols]

 Reference Signs List 10 demodulator 20 synchronous detector 22 delay detector 24 first error corrector 26 first CRC checker 28 first packet buffer 30, 32, 34 AND gate 36 CRC end detector 38 OR Gate 40 CPU 42 Second error corrector 44 Second CRC checker 46 Second packet buffer 48 Output device

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Takada 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Toru Kuroda 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tadashi Isobe 1-10-11 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (72) Inventor Tsutomu Yamada 1-110 Kinuta, Setagaya-ku, Tokyo Japan Broadcasting Corporation Broadcasting Research Institute (56) References JP-A-6-14066 (JP, A) JP-A-5-14550 (JP, A) JP-A-5-122197 (JP, A) JP-A 62-140 135047 (JP, A) JP-A-6-53940 (JP, A) JP-A-6-152568 (JP, A) JP-A-6-291782 (JP, A) JP-A-5-130061 (JP, A) (58) Field surveyed (In t.Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (4)

(57) [Claims] 1. A demodulator for demodulating a digitally modulated signal, comprising: synchronously detecting means for synchronously detecting the digitally modulated signal; and a first error for receiving and correcting an output of the synchronously detecting means.
Correction means, delay detection means for delay-detecting the digitally modulated signal, and second error for receiving and correcting the output of the delay detection means.
Correction means, the synchronous detection means based on an output of the first error correction means.
First determining means for determining correctness of each output packet of the stage, and the delay detecting means based on an output of the second error correcting means.
The second determination means, the first determination means, and the second determination means for determining correctness for each output packet of the stage are correct.
Output the output of the first error correction means when
A demodulator comprising output means . 2. The digitally modulated signal includes an LMSK signal, wherein the first and second determination means include the first and second error signals.
CR of the packet obtained from each output of the correction means
Determining a positive erroneous by the performing the C check, demodulator of claim 1. 3. The digitally modulated signal includes an LMSK signal, and the first and second determination means include the first and second error signals.
Each output determining a positive erroneous by the checking a parity is added to a packet obtained from the demodulator according to claim 1 of the correcting means. 4. The digitally modulated signal includes an LMSK signal, wherein the first and second determination means are configured to output the first and second error signals.
Depending on the state of the BIC which has been added to the obtained packet from each of the output correction means for determining a positive erroneous claim 1
The demodulator as described.