JPH11251448A - Cmos semiconductor integrated circuit, information processor and design support system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure a timing margin of signal transmission even with a long wiring, improve a circuit speed and reduce noise emission by making a wiring between the functional circuit blocks of a CMOS semiconductor a differential transmission line. SOLUTION: A cell is provided as a circuit element of a logic gate, etc., composed of a plurality of MOS transistors, and a differential signal transmission cell (differential driver) 12a, a differential signal, transmission cell (differential receiver) 12b and single end cells 13a and 13b are provided. The differential driver 12a is provided with positive and negative logical outputs as output terminals, and the differential receiver 12b is provided with a positive logic (+) and a negative logic (-) as input terminals. An inner wiring 14a transmits an output signal from the cell 13a to the differential driver 12a. An inner wiring 14b transmits an input signal to the differential receiver 12b to the cell 13b. Respective inner wirings 14a and 14b becomes a wiring between the cells in the same circuit block. Outer wirings 151 and 152 transmit a differential signal via a wiring between functional blocks A and B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS semiconductor integrated circuit, an information processing device and a design support device, and more particularly to a CMOS-LSI, an information processing device using the same, and wiring in the design support device.

[0002]

2. Description of the Related Art At present, in a CMOS (Complementary Metal Oxide Semiconductor) type semiconductor integrated circuit (CMOS-LSI),
Process miniaturization is progressing, and this CMOS-LSI
With the miniaturization of the process, the circuit density and speed,
In addition, it is becoming possible to lower the voltage.

In data transfer in the current CMOS-LSI, single-end (Single-End) transmission using a common ground is generally performed. this is,
When a signal output from one transmitting circuit is received by another receiving circuit, the signal voltage on the transmitting side and the voltage for discriminating the signal voltage on the receiving side are referenced to a common ground voltage on the transmitting and receiving sides. It is assumed that. The connection between the transmission side circuit and the reception side circuit is performed using a single signal line and a common ground.

In a bipolar LSI, EC
L (Emitter-coupled logic element)
erential) transmission. In this method, signals having opposite phases are simultaneously transmitted from a transmitting side to two signal lines, and a receiving side circuit determines a signal by reading a potential difference between the two signal lines.

Further, in general, in LSI, a circuit group for realizing a certain function is often divided into functional circuit blocks and arranged in a chip. For example, in a one-chip microcomputer, a central processing circuit (CPU), an external input / output circuit,
Each function such as a memory is collectively arranged as a functional circuit block.

It is known that the miniaturization of the CMOS-LSI process makes it possible to increase the circuit density and lower the voltage.
In the m process, the power supply voltage was 5 V, whereas the power supply voltage was 0.5 V.
The power supply voltage is 3.3 in the 5 μm to 0.35 μm process.
V, and the power supply voltage is 2.5 V to 1.8 V in the 0.25 μm to 0.18 μm process.

[0007] However, even if the process becomes finer, the chip size is rarely smaller than in the past. This is because, at the same time as the process is miniaturized, the functional performance required for the LSI is also improving, and the circuit scale is increasing. Since the chip size does not decrease even if the process is miniaturized, the wiring length between the functional circuit blocks may be longer than the circuit size in the LSI.
The wiring in the LSI is represented by a distributed constant circuit composed of RC, and the resistance component R and the capacitance component C of the wiring increase in proportion to the wiring length. Therefore, as the wiring length increases, the capacitance component C of the wiring also increases, and the rise time of the signal waveform increases before the signal output from the driver reaches the receiver.

In a CMOS-LSI, LS
When the circuit in I operates, the ground voltage of the operating circuit fluctuates due to the through current in the circuit. The power consumption of an LSI is proportional to the square of the power supply voltage and the chip area. Even if the power supply voltage decreases, the chip size does not decrease, and the power consumption increases due to the higher speed of the circuit. This is also an increase in the current flowing to the ground in the chip, and the increase in the current increases the fluctuation in the ground voltage. These things, L
This is an obstacle to speeding up the SI.

The single-ended transmission will be described with reference to FIG. The CMOS-LSI 10 'has functional circuit blocks A, B11a', 11b ', and the like. Then, the two functional circuit blocks A, B11a ', 11b'
Among the circuits 12a ', 13a', 12b ', 13b'
Is illustrated. For example, the functional circuit block A11a '
In this case, signal transmission is performed between the circuits 12a 'and 13a', and the circuit 13a 'is referred to as a "driver" and the circuit 12a' is referred to as a receiver (hereinafter referred to as a "receiver").
Call. ). When the driver 13a 'and the receiver 12a' are arranged close to each other, the ground point of the driver 13a 'and the receiver 12a' is close, so that
The ground voltage is almost the same between the driver 13a 'and the receiver 12a'. In this case, the signal voltage is set so that the ground voltage of the driver 13a 'and the receiver 12a' can be ignored even if the ground voltage fluctuates due to the operation of the circuit in the functional circuit block.

On the other hand, functional circuit blocks A and B11a ',
11b ', a signal is transmitted between the driver 12a' and the receiver 12b '. The driver and the receiver are separated from each other, and the wiring length between the driver 12a' and the receiver 12b 'is It is assumed to be longer than the circuit size. In this case, if the propagation time is long, the ground voltage at the ground point of the receiver fluctuates while the signal output from the driver 12a propagates through the wiring 15 ', and the signal between the driver 12a' and the receiver 12b ' May be different from each other.

The signal timing during single-ended transmission will be described with reference to FIG. FIG. 13 is a timing chart showing the timing of signal transmission from the driver 12a 'to the receiver 12b'. In FIG.
(A) shows the timing of signal output from the driver 12a ', and (B) shows the input timing of the same signal at the receiver 12b'. Here, the voltage at which the receiver 12b 'determines a signal is defined as Vref. Further, GND in the figure is a ground voltage waveform in the driver 12a ',
D2 is a ground voltage waveform at the receiver 12b '. Vgb is the potential difference between the ground voltage when the driver 12a 'outputs the signal and the ground voltage when the receiver 12b' receives the signal. Therefore, if the driver 12a 'and the receiver 12b' are located close to each other, Vgb is almost zero, and the reference voltage Vref and the actual reference voltage V
ref2 will be equal. In this case, the signal is always transmitted correctly. However, the ground voltage Vgb may occur when the signal output from the driver 12a 'reaches the receiver 12b', and in this case, the actual reference voltage Vref2 also changes according to Vgb. The fluctuation of the reference voltage causes a delay time difference tgb. If the signal handled here is a clock signal, the duty ratio may change, and a circuit that operates based on the clock signal may not operate normally. This is a factor that reduces the timing margin in actual circuit design,
Speeding up becomes difficult.

Further, in single-ended transmission, when a signal is sent from a driver to a receiver, a return current flows from the ground point of the receiver to the ground point of the driver. This return current, when the transmission frequency is low,
It flows straight from the ground point of the receiver to the ground point of the driver, but when the transmission frequency increases, it flows near the wiring between the driver and the receiver. At this time, if the ground wiring is not secured near the signal wiring, the return current strays through the other ground wiring, thereby increasing the distortion of the signal waveform and the radiation noise to the outside of the LSI.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art, and to secure a timing margin for signal transmission even if the wiring between functional circuit blocks becomes long. It is an object of the present invention to provide a CMOS-LSI that can achieve high speed and reduce radiation noise, an information processing device using the same, and a design support device.

[0014]

According to the present invention, there is provided a CMOS semiconductor integrated circuit having two or more functional circuit blocks and wiring between the functional circuit blocks. This is a CMOS type semiconductor integrated circuit which is a dynamic transmission line.

Further, the present invention is a CMOS semiconductor integrated circuit in which the functional circuit block has two or more small circuits, and wiring between the small circuits is a differential transmission line.

According to the present invention, the functional circuit block includes an output circuit that outputs two signals having phases opposite to each other;
C comprising: a voltage comparison circuit for comparing a voltage between two terminals; and a wiring connecting the output circuit and the voltage comparison circuit.
This is a MOS type semiconductor integrated circuit.

Further, according to the present invention, the functional circuit block includes an output circuit having a power supply point and a ground point, and an input circuit for inputting a signal from the output circuit. A CMOS type semiconductor integrated circuit is connected between the ground and the ground point using a separately provided wiring.

According to the present invention, at least one of the functional circuit blocks is a CMOS semiconductor integrated circuit having an operating voltage different from that of the other functional circuit blocks.

The present invention is a CMOS semiconductor integrated circuit in which at least one of the functional circuit blocks has a ground voltage different from that of the other functional circuit blocks.

Further, the present invention is a CMOS type semiconductor integrated circuit in which at least one of the functional circuit blocks has a ground wiring different from other functional circuit blocks.

Further, according to the present invention, the functional circuit block is a CMOS semiconductor integrated circuit including a functional circuit block of an analog circuit and a functional circuit block of a digital circuit.

According to the present invention, there is provided an information processing apparatus having at least one semiconductor integrated circuit as a central processing circuit, an input / output circuit, and the like.
This is an information processing device that is a MOS type semiconductor integrated circuit.

Furthermore, the present invention provides a CMOS having two or more functional circuit blocks and wiring between the functional circuit blocks.
A design support device for a semiconductor integrated circuit, comprising: a differential transmission line setting means for setting the wiring to a differential transmission line at a stage of designing the semiconductor integrated circuit.

Further, the present invention provides a CMOS having two or more functional circuit blocks and wiring between the functional circuit blocks.
A design support device for a semiconductor integrated circuit, comprising: an automatic selection unit for automatically selecting a differential transmission line or a single-ended transmission line according to a wiring length of the wiring.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described. A CMOS semiconductor integrated circuit, an information processing device, and a design support device according to the present invention will be described using embodiments. FIG. 1 is a schematic explanatory diagram of the first embodiment. FIG. 2 is a timing chart explanatory diagram of signal transmission in the first embodiment. FIG. 3 is a schematic explanatory diagram of the second embodiment. FIG.
FIG. 13 is a schematic explanatory diagram of a third embodiment. FIG. 5 is a schematic explanatory diagram of the fourth embodiment. FIG. 6 is a schematic explanatory diagram of the fifth embodiment.
FIG. 7 is a schematic explanatory diagram of the sixth embodiment. FIG. 8 is a schematic explanatory diagram of the seventh embodiment. FIG. 9 is an explanatory diagram of a screen display of the design tool according to the eighth embodiment. FIG. 10 is another screen display explanatory diagram in the eighth embodiment. FIG. 11 is a schematic explanatory diagram of the ninth embodiment.

Embodiment 1 will be described with reference to FIG. FIG. 1 is a configuration diagram of an internal circuit of the CMOS-LSI chip 10. The LSI chip 10 has functional circuit blocks A, B 11a, 11b, etc., and external wirings 151, 152. The functional circuit blocks A, B 11a, 11b are circuit blocks composed of a plurality of cells 12a, 13a, 12b, 13b, internal wirings 14a, 14b, and the like. The cell is a circuit element such as a logic gate composed of a plurality of MOS transistors, and is a cell for transmitting a differential signal (hereinafter, referred to as a cell).
It is called "differential driver". 12a), a differential signal receiving cell (hereinafter, referred to as “differential receiver”) 12b, and single-ended cells 13a, 13b. Differential driver 1
2a has two output terminals, a positive logic output and a negative logic output. The differential receiver 12b has two input terminals, a positive logic input (+) and a negative logic input (-). The internal wiring 14a transmits a signal output from the cell 13a to the differential driver 12a. Internal wiring 14b
Converts the signal input to the differential receiver 12b into the cell 13b
To be transmitted. The external wires 151 and 152 are
The differential signal output from the differential driver 12a in 11a is transmitted to the differential receiver 12b in the functional block B11b. By the differential driver 12a, a signal of positive logic is transmitted to the external wiring 151, and a signal of negative logic is transmitted to the external wiring 152. These two signals have an opposite phase relationship to each other. Note that the outer wirings 151 and 152 are differential transmission lines that are wired in parallel and of equal length. Cells 13a, 1
3b is also wired to other cells (not shown), in addition to the internal wiring 14a and 14b to the differential driver 12a and the differential receiver 12b. The differential driver 12a and the cell 13a are provided in the functional block A11a. Further, the differential receiver 12b and the cell 13b are provided in the functional block B11b. Internal wiring 14
Reference numerals a and 14b denote wirings between cells in the same functional circuit block. The outer wirings 151 and 152 are wirings between the functional blocks A and B, and transmit differential signals.

The transmission timing and voltage level of the differential signal will be described with reference to FIG. FIG. 2 is a timing chart showing signal transmission timing and voltage levels of the differential signal from the differential driver 12a to the differential receiver 12b. In FIG. 2, (A) shows the differential driver 1
2A shows a signal waveform and a ground waveform at the time of output from 2a. In (A), the voltage on the positive logic side of the differential driver 12a is Vp, and the voltage on the negative logic side is Vn.
(B) shows a signal waveform and a ground waveform when the signal from the differential driver 12a is received by the differential receiver 12b. In (B), the voltage on the positive logic side of the differential receiver 12b is Vp2, and the voltage on the negative logic side is Vn2. In the case of differential transmission, the signal is determined based on the potential difference between the positive logic voltage Vp2 of the differential receiver 12a and the negative logic input Vn2. Therefore, even if the ground voltage fluctuation Vgb occurs or the common mode noise is applied to the signal, the same offset voltage is applied to both the negative logic input and the positive logic input, so that the positive logic side Vp2 and the negative logic side Vn2 Does not change, and there is no delay time difference due to the fluctuation Vgb of the ground voltage.

As described above, according to this embodiment,
Since differential transmission is performed between each functional circuit block, signal transmission between each functional circuit block can be speeded up. In addition, stray return current due to signal transmission between functional circuit blocks can be suppressed, and radiation noise from the chip can be reduced.

In the present embodiment, the differential driver 12a and the differential receiver 12b are buffers functioning as an interface between a normal signal and a differential signal. A circuit that can input and output signals may be added. Further, in this embodiment, differential transmission is used for signal transmission between functional circuit blocks. However, even in a functional circuit block, for an inner line having a long wiring length, a signal by a differential signal is also used between cells. Transmission may be performed. Further, a configuration may be adopted in which differential transmission is performed between all of the external wirings and the internal wirings between and within the functional circuit blocks.

Embodiment 2 will be described. This embodiment is different from the first embodiment in the wiring method between the functional circuit blocks. FIG. 3 shows the function blocks A and B2 in this embodiment.
It is explanatory drawing in the case of performing signal transmission between 1a and 21b.
The difference between FIG. 3A and FIG. 1 is that a driver 22a and a receiver 22b for single-end transmission are used instead of the differential driver 12a and the differential receiver 12b.
In FIG. 3B, particularly, the drive circuit portion 2 of the driver 22a
21, 222 and the receiving circuit part 223 of the receiver 22b
Is illustrated. Further, in addition to the signal line 251 used for signal transmission between these cells, external wirings 252 and 253 run in parallel. These wirings are wired in parallel and of equal length. The external wiring 252 is a wiring connecting the power supply (VDD) of the driving circuit portion 221 of the driver 22a and the power supply of the receiving circuit portion 223 of the receiver 22b. Also,
The external wiring 253 is connected to the drive circuit portion 222 of the driver 22a.
And the ground (GND) of the receiver 22b of the receiver 22b. As shown in FIG. 3, the signal transmission between the driver and the receiver, the power supply, and the ground can also be run in parallel, as in the case of the differential transmission line described with reference to FIG.

Embodiment 3 will be described. CMOS of this embodiment
As shown in FIG. 4, the LSI chip 30 includes functional circuit blocks A, B 31a and 31b, and external wirings 351 and 3
52. In the first embodiment, the signal transmission direction is one direction from the functional block A11a to the functional block B11b. In the present embodiment, the signal transmission direction is the functional blocks A, B31a,
1b can be bidirectionally transmitted. 4 and FIG. 1 is that the differential driver 32a and the differential receiver 3
The difference is that the second differential receiver 32a2 and the second differential driver 32b2 are added to the external wirings 351 and 352 connecting the second differential receiver 2b and the second differential driver 32b2. The second differential driver 32b2 is disposed in the functional block B31b, and the second differential driver 32b2
a2 is arranged in the functional block A31a. As a result, the function block A31a changes to the function block B31.
b, the differential driver 32a and the differential receiver 32b are used. Conversely, when transmitting from the functional block B31b to the functional block A31a, the second differential driver 32b2 and the second differential receiver 32a2 are used. . By doing so, there is an effect that the speeding up of the LSI and the bidirectional transmission can be simultaneously performed.

Embodiment 4 will be described. C of the present embodiment
As shown in FIG. 5, the MOS-LSI chip 40 includes an input / output circuit 41, functional circuit blocks A, B, C, D41a,
41b, 41c and 41d, and external wirings 451 and 452 are provided. The input / output circuit 41 has an external buffer 42 for receiving a clock signal supplied from outside the chip and distributing it to each functional circuit block in the chip. Functional circuit blocks A, B, C, D41a, 41b, 41
c and 41d are inner buffers 42a, 42b, 42c and 42 for distributing the clock signal received from the outer buffer 42 to cells in the functional circuit block or other buffers.
d. Outer buffer 42 and inner buffer 42
a, 42b, 42c, 42d, external wiring 45
1, 452 are connected so that the wiring length, the position of the branch point, and the number of branches are substantially equal. In the present embodiment, the outer buffer 42 arranged in the input / output circuit 41 and the inner buffers 42a, 42 arranged in each functional circuit block.
b, 42c and 42d are connected by a differential transmission line. In this embodiment, an external clock signal is
Although it is supplied to each functional circuit block using the external buffer 42 of the input / output block 41, the PLL (P
Hase Locked Loop) circuit and DLL
(Delay Locked Loop) circuit is provided,
The clock signal may be supplied to each functional circuit block after frequency division, multiplication or phase adjustment of an external clock signal. Further, the external buffer 42 differentially transmits a signal transmitted from the outside of the chip in a single-ended manner in the chip, but a clock signal from the outside of the chip may be a differential transmission signal. Thus, according to the present embodiment, the clock signal supplied to each functional circuit block is also
Can be applied. Thus, even if the current and voltage in the chip fluctuate, a clock signal with a uniform duty ratio can be supplied to each functional circuit block in the chip, which can contribute to an increase in the speed of the LSI.

Embodiment 5 will be described with reference to FIG. FIG. 6 shows L in which the operating voltage differs between the functional circuit blocks.
FIG. 2 is a configuration diagram of an SI chip, in which a chip 50 includes an input / output circuit 51, functional circuit blocks A, B51a, 51b, and external wiring. The input / output circuit 51 performs input / output between the outside of the chip and the functional circuit blocks A, B 51a, 51b inside the chip. In addition, the functional circuit blocks A, B51a, 5
The operating voltage of 1b is 1.8V, and the operating voltage and the input / output voltage of the input / output circuit 51 are 3.3V. Therefore, the input / output circuit 51 and the functional circuit blocks A and B51
Between a and 51b, a differential driver and a differential receiver are provided in locations requiring transmission, that is, in functional circuit blocks having different operating voltages. Further, the differential driver and the differential receiver are connected by a differential transmission line. In the present embodiment, the voltages of the functional circuit blocks A, B51a, 51b are equal, but as described in the first embodiment, the functional circuit blocks A, B51
A differential transmission line may be provided between a and 51b. The operating voltage of the input / output circuit 51 is 3.3 V in all cases, but the input / output circuit 51 may be divided into blocks having different operating voltages according to the functional circuit block to be connected. According to the present embodiment,
It can be applied even if the operating voltage is different between functional circuit blocks, and it is possible to simultaneously achieve faster signal transmission between functional circuit blocks and signal transmission between functional circuit blocks with different operating voltages. Become.

Embodiment 6 will be described with reference to FIG. FIG. 7 is a configuration diagram of an LSI chip 60 in which digital circuits and analog circuits are mixed. The chip 60 has input / output circuits A and B 61a and 61b, a logic circuit 61c, a conversion circuit 61d, and external wiring. The logic circuit block 61c is configured by a digital circuit in a chip,
It is a digital circuit block. Conversion circuit block 61d
Is a functional circuit block including an analog / digital conversion circuit (A / D conversion circuit) and a digital / analog conversion circuit (D / A conversion circuit) which is configured by an analog circuit in a chip. It is a block. The input / output circuit A61a inputs / outputs digital signals between the logic circuit 61c and the outside of the chip, while the input / output circuit B61b inputs / outputs analog signals between the conversion circuit 61d and the outside of the chip. Perform output. Although not particularly shown in the present embodiment, the digital circuit block 61c and the analog circuit block 61d have independent ground lines. In this embodiment, between the digital circuit block 61c and the analog circuit block 61d, between the input / output circuit B61b and the analog circuit block 61d, and between the input / output circuit A61a and the digital circuit block 61c.
Are connected by a differential transmission line. According to this embodiment, even if an analog circuit and a digital circuit are mixed in a chip, signal transmission between functional circuit blocks can be speeded up by applying the present invention.

Embodiment 7 will be described with reference to FIG. FIG. 8 is a configuration diagram of the inside of a chip 70 of a one-chip microcomputer (hereinafter, microcomputer). Microcomputer chip 70
Are a central processing circuit (CPU) 71a, a storage circuit (memory) 71b, a peripheral control circuit 71c, a memory control circuit 71
d, an input / output circuit 71, and functional circuit blocks and external wiring. The central processing circuit 71a performs arithmetic processing based on programs and data recorded in the memory 71b. The peripheral control circuit 71c controls peripheral circuits provided outside the microcomputer, such as communication and screen display. The memory control circuit 71d includes a memory provided outside the microcomputer.
(External memory). The input / output circuit 71 includes a central processing circuit (CPU) 71a, a storage circuit (memory) 71
b, input / output signals between the peripheral control circuit 71c, the memory control circuit 71d, and the outside of the chip. Although not shown in FIG. 8, the microcomputer according to the present embodiment includes a storage circuit (external memory) for recording a program and data for performing arithmetic processing, and a circuit for performing communication, screen display, and the like ( Peripheral circuit). In this embodiment, by applying the present invention to the signal transmission between the functional circuit blocks 71a to 71d and 71, the signal transmission between the functional circuit blocks can be sped up, and as a result, the speed of the whole one-chip microcomputer can be increased. It becomes possible.

Embodiment 8 will be described with reference to FIGS. 9 and 10. FIG. FIG. 9 is a part of a display screen during design by an LSI logic design tool (CAD). In the display window 871, L
A part of the circuit diagram in the SI is displayed. In FIG. 9, L
One of several functional circuit blocks constituting the SI and a part of the block are displayed. Cells 831 to 834 arranged in functional blocks are shown.
The cell 832 and the cell 833 are connected by a wiring 842. The cell 834 is an input / output terminal for another functional circuit block. Here, when the designer provides the wiring 841 to connect the cell 831 and the input / output terminal 834, another display window 872 is displayed on the screen, and the wiring 841 and the cell 8
A state in which the designer can answer whether or not to change 31 for differential transmission is set. The designer clicks the answer button "Yes" here 8
When 81 is selected, the cell 831, the wiring 841, and the input / output terminal 834 are changed to cells, wiring, and input / output terminals for differential transmission, respectively. The cell changed here has the same function as the cell placed before the change by the designer,
The input / output circuit is for differential transmission. On the other hand, when the designer selects the answer button “No” 882, the cell 831, the wiring 841, and the input / output terminal 834 are not changed for differential transmission.

FIG. 10 is a part of another display screen of the logic design tool of the LSI during design. In the display window 873,
A part of the circuit diagram in the LSI is displayed. FIG. 10 shows one of several functional circuit blocks constituting the LSI and a part of the block, and shows cells 835 to 838 arranged in the functional block. The cell 837 and the cell 838 are connected by a wiring 844. If the cell 835 and the cell 836 are arranged during the design and then these cells are connected by the wiring 843, another display window 874 is displayed on the screen, and the wiring 843 and the cells 835 and 836 are connected. Is ready to answer whether or not to change for differential transmission. This display window is displayed by automatically selecting a differential transmission line or a single-ended transmission line when the wiring length of the wiring 843 exceeds a value preset in a design tool. If the designer selects the answer button 883 “Yes” here, the design tool changes the cells 835 and 836 to cells for differential transmission, and further changes the wiring 843 to a differential line. The cell to be changed here has a function equivalent to that of the cell arranged by the designer before the change, and the input / output circuit is for differential transmission. On the other hand, if the designer selects the answer button 884 “No”, cells 835 and 83
6 and the wiring 843 are not changed for differential transmission. In the present embodiment, the change is made during the cell arrangement, but the change may be made collectively after the arrangement is completed. In addition, the designer may be able to arbitrarily change the cells and wirings for differential transmission. As described above, according to the present embodiment, an LSI designer can design a high-speed LSI without being conscious of differential transmission between functional circuit blocks.

Embodiment 9 will be described with reference to FIG. FIG. 11 is a configuration diagram when this embodiment is applied to a computer system. Computer system
Central processing units (CPU) 91a, 91b, memory control unit 92, storage units (memory) 93a to 93d, hard disk control unit 94, communication unit 95, display control unit 9
6, keyboard control device 97, bus wires 98a to 98c
Etc. The central processing unit 91 includes bus wirings 98a to 98a-9.
8c, a memory control device 92, a storage device (memory) 93, a hard disk control device 94, a communication device 9
5, connected to the display control device 96, the keyboard control device 97, and the like. The hard disk control device 94 is connected to the hard disk 941. The communication device 95 is connected to a local area network (LAN). The display control device 96 is connected to the display device 961 and displays images and data on the display device 961. The keyboard control device 97 is connected to the keyboard 971. The bus wires 98a to 98c are connected via a bus bridge 99. In FIG. 11, the bus lines 98a to 98c are shown as single lines, but in an actual system, the bus lines are composed of a plurality of signal lines and are transmitted differentially. The central processing units 91a and 91b input and output data to and from the storage devices 93a to 93d via the memory control device 92, and the hard disk 941, LAN, display device 961, and keyboard via the bus bridge 99 and each control device, respectively. 971 and input / output data. In this embodiment, the central processing unit 91 and the memory control device 9
2 and the bus bridge 99 are configured using the LSI according to the present invention. Thereby, the speed of the central processing unit 91, the memory control device 92, and the bus bridge 99, which are required to be particularly high-speed operations in the computer system, can be increased, and the performance of the computer system can be improved. In addition, the present invention can be applied to the hard disk control device 94, the communication device 95, and the display control device 96,
Further, it is possible to improve the performance of the computer system.

[0039]

According to the present invention, signal transmission between functional circuit blocks can be speeded up by performing signal transmission using wiring between functional circuit blocks in a CMOS-LSI chip as a differential line. Single-ended transmission CMO
Compared with the S-LSI, the speed of the entire circuit can be increased. Furthermore, since stray return current due to signal transmission between functional circuit blocks can be suppressed, it is possible to reduce radiation noise to the outside of the LSI. Thus, a CMOS-LSI with high speed and low radiation noise can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic explanatory diagram of a first embodiment.

FIG. 2 is a timing chart explanatory diagram of signal transmission in the first embodiment.

FIG. 3 is a schematic explanatory view of a second embodiment.

FIG. 4 is a schematic explanatory view of a third embodiment.

FIG. 5 is a schematic explanatory view of a fourth embodiment.

FIG. 6 is a schematic explanatory view of a fifth embodiment.

FIG. 7 is a schematic explanatory view of a sixth embodiment.

FIG. 8 is a schematic explanatory view of a seventh embodiment.

FIG. 9 is an explanatory diagram of a screen display of a design tool according to an eighth embodiment.

FIG. 10 is another screen display explanatory diagram in the eighth embodiment.

FIG. 11 is a schematic explanatory view of a ninth embodiment.

FIG. 12 is a schematic explanatory diagram of a conventional transmission method.

FIG. 13 is an explanatory diagram of a timing chart of signal transmission in the related art.

[Explanation of symbols]

10, 30, 40, 50, 60, 70 LSI chip 11, 21, 31, 41, 51, 61, 71 Functional circuit block 12, 22, 32, 42 Differential driver, buffer 13, 83 cell 14, internal wiring 15 , 25, 35, 45 external wiring 87 window 88 answer button, 91 central processing unit 92 memory control device 93 memory 94 hard disk control device 941 hard disk 95 communication device 96 display control device 961 display device 97 keyboard control device 971 keyboard 98 bus wiring 99 Bus bridge

Claims (11)

[Claims] 1. A CMOS semiconductor integrated circuit having two or more functional circuit blocks and wiring between the functional circuit blocks, wherein the wiring between the functional circuit blocks is a differential transmission line. CMOS type semiconductor integrated circuit. 2. The CMOS semiconductor integrated circuit according to claim 1, wherein said functional circuit block has two or more small circuits, and a wiring between said small circuits is a differential transmission line. CMOS type semiconductor integrated circuit. 3. The CMOS type semiconductor integrated circuit according to claim 1, wherein the functional circuit block compares an output circuit that outputs two signals having phases opposite to each other with a voltage between two terminals. A CMOS semiconductor integrated circuit, comprising: a circuit; and a wiring connecting the output circuit and the voltage comparison circuit. 4. The C according to claim 1, wherein
In the MOS-type semiconductor integrated circuit, the functional circuit block includes an output circuit having a power supply point and a ground point, and an input circuit for inputting a signal from the output circuit. A CMOS semiconductor integrated circuit, wherein the ground points are connected by using a separately provided wiring. 5. The C according to claim 1, wherein
In a MOS semiconductor integrated circuit, at least one of the functional circuit blocks has an operating voltage different from that of another functional circuit block. 6. C according to any one of claims 1 to 5,
In the MOS type semiconductor integrated circuit, at least one of the functional circuit blocks has a ground voltage different from that of the other functional circuit blocks. 7. The C according to claim 1, wherein
In the MOS type semiconductor integrated circuit, at least one of the functional circuit blocks has a ground wiring different from other functional circuit blocks. 8. C according to any one of claims 1 to 7,
In the MOS semiconductor integrated circuit, the functional circuit block includes a functional circuit block of an analog circuit and a functional circuit block of a digital circuit. 9. An information processing apparatus having at least one semiconductor integrated circuit as a central processing circuit, an input / output circuit, and the like, wherein the semiconductor integrated circuit is a CMOS type semiconductor device according to claim 1. An information processing device, being an integrated circuit. 10. A CMOS-type semiconductor integrated circuit design support apparatus comprising two or more functional circuit blocks and a wiring between the functional circuit blocks, wherein the wiring is connected to a differential transmission line in a designing stage of the semiconductor integrated circuit. A design support apparatus comprising a differential transmission line setting means for setting. 11. A design support apparatus for a CMOS semiconductor integrated circuit comprising two or more functional circuit blocks and a wiring between the functional circuit blocks, wherein a differential transmission line or a single-ended transmission is provided according to a wiring length of the wiring. A design support device comprising automatic selection means for automatically selecting a track.