JP3003577B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit, and more particularly to an output impedance control circuit used for a data output section of an LSI requiring high-speed operation.

[0002]

2. Description of the Related Art In recent years, high-performance microprocessors (M
(PU) has dramatically improved the performance of workstations and personal computers, but in the multimedia age, enormous data processing of images and sounds is required, so higher speed processing is possible Computer is required. Therefore, in order to satisfy this demand, it is essential to improve not only the performance of the MPU but also the processing speed of peripheral LSIs such as a memory and a controller. Speaking of the interface between LSIs, the TTL interface that has supported a 5V power supply
Operation at 0 MHz or higher has become difficult. The main reasons are (a) generation of signal line / power supply noise, (b) generation of reflection noise / crosstalk noise, and (c) increase in power consumption due to the large signal amplitude.

On the other hand, the above problems have been considerably improved by reducing the amplitude of a signal transmitted between LSIs. LVTTL, GT as small amplitude interface
L and CTT have been developed one after another, and recently HSTL and ST
New interfaces such as BUS are also being developed.
With the advent of these small-amplitude interfaces, 100
The operation around MHz has become a reality, but when operating at higher frequencies, reflection of the transmitted signal is the biggest problem. Here, the adverse effect of reflection of a transmission signal between LSIs will be considered. Generally, between the transmission lines, that is, as shown in FIG.
2. Terminating resistor 33 connected to load-side inverter 34
If the impedances are matched, there is no disturbance in the waveform at the receiving end (load section) as shown in FIG. However, when impedance matching is not achieved, the transmission signal is reflected at the receiving end, resulting in a distorted waveform shown in FIG. When such a disturbed waveform is received by the next-stage LSI, it becomes "L" or "H" depending on the timing of capturing the waveform. If “L” is taken in when “H” should be taken in, the device will malfunction. From a different perspective,
It can be said that the access itself is delayed due to the reflection of the transmission signal.

When a device is constructed using a plurality of LSIs,
Ideally, impedance matching is achieved between all the LSIs. However, it is difficult to make the output impedance of the LSI uniform due to diffusion process variations. Also, even if the output unit can be adjusted to a specific impedance on the LSI chip,
The matching may be shifted due to the influence of the inductance and capacitance of the package and the printed circuit board when the LSI is mounted. From the above points, stable high-frequency operation becomes difficult unless the output impedance has a degree of freedom after the LSI is manufactured.

To solve such a problem, an output impedance control circuit shown in FIG. 6A has been proposed to suppress reflection of an output waveform. This circuit allows the output impedance to be varied by the value of an external resistor. As shown in FIG.
L), an external resistor 21 connected between the power supplies to make
A plurality of, here three, NMOS transistors 22a to 22a connected in parallel to the external resistor 21 respectively.
2c, two internal resistors 23a and 23b connected between the power supplies to generate one fixed potential (VREF), a comparator 24 for comparing these potentials VAL and VREF, and a comparison potential of the comparator 24. 25 that fetches data in synchronization with an externally supplied clock
And a clock synchronous type up / down counter 26 for adding / subtracting according to the “H” and “L” signals from the register 25.
It has.

In order to determine the final impedance based on the up / down counter 26, three latch groups 27a to 27c for temporarily storing the digital signal of the up / down counter 26 and the latch 2
7a to 27c and receives internal signals IN, I
NB and Hi-impedance control signal Hi-Z are input, and three-input logic gates 28b-28d, 28f-28h for driving the next-stage output transistor group, and the next-stage output transistor group are driven by the internal signal and the Hi-impedance control signal. Two-input logic gates 28a and 28e
Output transistors 29a to 29h connected in parallel driven by the logic gates 28a to 28h are provided. Here, the NMOS transistor groups 22a, 22b,
22c and the size of each of the output transistors 29b, 29c, 29d and 29f, 29g, 29h have an integer ratio of 3: 2: 1 in this order. The output transistors 29a and 29e are sized to be the upper limit of the output impedance.

In this output impedance control circuit, VA is connected by connecting an optional external resistor 21.
The potential of L is determined. If the output of the up / down counter 26 is "000" and the NMOS transistors 22a to 22
If all the c are in the OFF state, the VAL level is 0 V
, And the potential of VREF becomes higher. At this time, assuming that the outputs of the latches 27a to 27c are also "000", among the output transistors divided in parallel, 29b to 29d,
Since 29f to 29h are turned off and only a pair of 29a and 29e are turned on / off, the current output impedance has the largest value. At this time, the comparator 24 outputs “H”, and the data is taken into the register 25 in synchronization with the rising (or falling) edge of the externally supplied clock. And up-down counter 2
6 also counts up in synchronization with the clock (000 → 00
1) Yes. As a result, one of the NMOS transistors 22c
Turns ON, and the potential of VAL rises.

After that, VAL and VR are again output from the comparator.
EF is compared, and when the potential of VREF is higher, the count-up is performed by the same operation as before (001 → 010).
And NMOS transistor is ON / O in another combination
FF (22b / 22c), and raises the potential of VAL. The above operation is repeated to count up as shown in FIG. 6B, and approach a digital signal proportional to the external resistor 21. When the potential of VAL rises to a certain point, it becomes higher than VREF, and the up / down counter counts down. Thereafter, the up / down counter reaches an equilibrium value while repeating count up / down. Then, the latches 27a to 27
c to open the output transistors 29b to 29d and 29f to 2
The ON / OFF relation of 9h is determined, and the state is maintained by closing the latch. Until the output impedance is determined, a clock signal of several cycles externally supplied is required as shown in FIG.

[0009]

The above-mentioned conventional semiconductor integrated circuit requires an external clock to adjust the output impedance to a desired value, and is not suitable for an asynchronous LSI. Further, since the output impedance is determined on an AC basis, when used in a high-speed operation LSI, the bits of a register or a counter are inverted due to the influence of noise or the like, and the output impedance may be different from a desired value.

An object of the present invention is to determine the output impedance at high speed and stably in such a high-speed LSI, etc.
An object of the present invention is to provide a semiconductor integrated circuit applicable to not only a synchronous LSI but also an asynchronous LSI.

[0011]

A semiconductor integrated circuit according to the present invention, particularly an output impedance control circuit, generates reference potential generating means for generating a plurality of reference potentials, and generates one potential corresponding to the resistance value of an external resistor. A plurality of reference potentials and one potential to determine one potential, and output a signal corresponding to the determined potential; and a potential determining means. a code gate means for outputting a corresponding code signal based on the discrimination output, is driven by the code output of the code gate means and a plurality of output transistors circuit for changing the output impedance, the reference potential generating
Generating said single potential between the means and a power supply connected thereto;
Between the means and the power supply connected to the means,
Each of the force ends has a switch means;
Latch means at an output end of the latch means;
At the same time as latching the output of the code gate means.
And the switch means is turned off .

Also, in the present invention, a plurality of reference potentials
Potential generating means for generating the resistance, and the resistance value of the external resistor
A single potential generating means for generating one potential corresponding to
Comparing the plurality of reference potentials and one potential to one potential
Potential is determined, and a signal corresponding to the determined potential is output.
Potential discriminating means, and discrimination output of the potential discriminating means.
A code gate that outputs a corresponding code signal based on the
Driven by the stage and the code output of this code gate means.
Output impedance to change the output impedance
A plurality of MOS transistors each having a drain or a source connected to the highest potential or the lowest potential, each of which constitutes a plurality of sets, and the code gate means includes a plurality of MOS transistors each having a drain or a source connected to the lowest potential. The connection forms of the potential and the lowest potential are different from each other, and one of the sets is selected, and when selected, the potential is output from each source or drain of the MOS transistors constituting the set.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an output impedance control circuit according to a first embodiment of the present invention. In this circuit, an external resistor 1 connected between a power supply VDD and GND to generate one fixed potential (VDC), internal resistors 2a and 2b connected in series to this, and a plurality of fixed potentials (VR)
EF1 to VREF9), a plurality of internal resistors 3a to 3i connected between power supplies, and their potentials VDC and VR
A plurality of comparators 4a to 4i for comparing EF1 to VREF9 and EX-OR gates 5a to 5h for detecting a mismatch between outputs adjacent to these comparators
And the outputs of these EX-OR gates 5a to 5h,
NMOS gate 6 composed of a plurality of NMOS transistors for generating digital signals (000 to 111)
It has. Further, in order to determine the final output impedance, logic gates 7a to 7h having two or more inputs are provided.
Output transistors 8a to 8h divided in parallel driven by these logic gates 7a to 7h are provided.

Here, the comparators 4a to 4i are shown in FIG.
As shown in the figure, PMOS transistors 9a to 9c and N
It is configured as a differential amplifier circuit composed of MOS transistors 9d and 9e and an inverter (buffer) 9g.
The NMOS gate 6 has a set of three MOS transistors. The drain or source of each MOS transistor is connected to VDD or GND, and the gate is selectively set to “H”. 000
To 111). Further, the output transistor 8
The sizes of a to 8h are such that the output transistors 8a and 8e have the upper limit value of the output impedance, and the output transistors 8b to 8d and 8f to 8h have the integer ratio of 3: 2: 1 in this order. ing.

According to this output impedance control circuit, by connecting an optional external resistor 1,
VDC is determined by the potential division between the resistors 2a and 2b. Here, the internal resistor 2a may be originally absent, but is provided so that when the external resistor 1 is set to 0Ω, the potential difference between the two inputs of the comparator described below does not become zero. This VDC corresponds to a plurality of comparators 4a to 4
i is commonly input. One of the inputs of each of the comparators 4a to 4i has a plurality of fixed potentials VRE obtained by a plurality of resistors 3a to 3i inserted between the power supplies and dividing the power supply.
F1 to VREF9 are input. Comparators 4a to 4
Regarding i, the transistor sizes 9a to 9c are changed according to the levels of VREF1 to VREF9, so that the potential difference having a small amplitude can be reliably amplified.

If the potential of VDC is higher than VREF4 and lower than VREF5, the comparator group 4
The outputs 4a to 4d output "H", and the outputs 4e to 4e
4h output "L". With respect to these outputs, the next stage EX-OR outputs "L" since the outputs between the comparators 5a to 5c and 5e to 5h are the same, and outputs only the EX-OR 5d. "H" is output because the comparators do not match.
Since the "H" output signal selectively inputs "H" to the gate of the corresponding MOS transistor of the NMOS gate 6, "100" of the digital pattern is output.

Thus, the next stage gates 7b to 7d, 7f
7h are determined, and the output transistors 8a-8h at the next stage are further determined based on the output of the selected gate.
ON / OFF is determined. Actually, the internal signals IN, IN
B, the output transistors 8b to 8d or 8f to 8
ON / OFF (“H”, “L”) of h is determined. Thus, the output impedance is determined. That is, by using a predetermined resistor as the external resistor 1, the output impedance corresponding to this is determined. In this case, regarding the relationship between the external resistance and the internal resistance group, when an external resistance of how many Ω is connected in advance, one output of any EX-OR becomes “H” and a digital pattern is selected. It is only necessary to determine how much output impedance will be obtained depending on the pattern.

As described above, in the output impedance control circuit of this embodiment, the power supply is turned on or the connection of the external resistor is performed by connecting the external resistor 1 without the need for an external clock or a control pin for updating. Immediately determines the output impedance. Therefore, the present invention can be applied to an asynchronous LSI. If the power supply VDDQ for the output transistor is set to 1.2 V, GT
L, CTT for 3.0V, HST for 1.5V
It can be applied to various interfaces such as L. Since the output impedance is determined by DC, it is more stable than the conventional circuit determined by AC. In this embodiment, 3bi
t, that is, an example of a circuit in which eight combinations are possible is shown, but it goes without saying that a configuration of 4 bits or more is possible if there is no restriction on the chip size.

FIG. 3 shows a second embodiment of the present invention. Note that parts equivalent to those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. In the first embodiment, a plurality of comparators are used, and the circuit has a function of converting a small-amplitude difference potential from the resistor group to a MOS level. However, when the present invention is applied to an LSI that requires a low current consumption because a through current flows, the current needs to be reduced. Therefore, in the second embodiment,
The latches 10a to 10c are provided at the output end of the digital pattern of the NMOS gate 6, and are driven by the control signal G together with the comparators 4a to 4i. Also,
The comparators 4a to 4i, as shown in FIG.
S transistors 9a to 9c and NMOS transistor 9
d to 9f and an inverter 9g are configured as a differential amplifier circuit.
The transistor 9f is connected so as to operate by the control signal G. Further, a PMOS transistor 11a is interposed between the resistor 2b and the power source, and a PMOS transistor 11b is interposed between the resistor 3i and the power source.

In this circuit, the control signal G is set to "L" before determining the output impedance. At this time, the latch circuits 10a to 10c are set to a through state. The operation for determining the impedance is the same as in FIG. Next, the control signal G is set to "H" to latch the digital code and, at the same time, cut off the current flowing through the comparators 4a to 4h by turning off the PMOS transistor 9a. Further, by turning on the NMOS transistor 9f, the input level of the inverter is fixed at "L" to prevent a through current of the next-stage inverter 9g. Further resistance 2
a, 2b and the current flowing through the resistors 3a to 3i
It is cut by turning off the OS transistors 11a and 11b. By adding this function, the standby current can be significantly reduced. It should be noted that the second embodiment can also correspond to a small-amplitude interface such as GTL, CTT, HSTL, etc.
The same as in the first embodiment is applicable to I.

[0021]

As described above, according to the present invention, a plurality of reference potentials to be generated and one corresponding to the resistance value of an external resistor are provided.
The two potentials are compared to determine the potential of one potential, a signal corresponding to the determined potential is output, a corresponding code signal is output based on the determined output, and an output is provided by the code output of the code gate means. Since the output impedance is changed by driving the transistor circuit, the output impedance can be more quickly and stably determined in a high-speed LSI requiring a small-amplitude interface. Further, since an external clock is not required, the present invention can be applied to an asynchronous LSI. In addition, by adding one control terminal, L which requires low power consumption is required.
Compatibility with SI is also possible. From these facts, the present invention exerts a sufficient effect on the demand for further high-speed LSI (200 MHz or more) in the future. Further, claim 1
By providing switch means and latch means of
Dramatically reduce standby current while preventing current
Is possible. Further, according to the MOS gate of claim 2,
Code gate means can be a simple circuit
You.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of an output impedance control circuit according to the present invention.

FIG. 2 is a circuit diagram of the comparator shown in FIG. 1;

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

FIG. 4 is a circuit diagram of the comparator shown in FIG. 3;

FIG. 5 is a diagram for explaining an effect of an output impedance on a transmission line.

FIG. 6 is a circuit diagram of an example of a conventional output impedance control circuit and a timing chart for explaining its operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 External resistance 2a, 2b Resistance 3a-3i Resistance 4a-4i Comparator 5a-5h EX-OR gate 6 NMOS gate 7A-7h Logic gate 8a-8h Output transistor 9a-9f MOS transistor 10a-10c Latch 11a, 11b PMOS transistor

Claims (5)

(57) [Claims] 1. A reference potential generating means for generating a plurality of reference potentials; a single potential generating means for generating one potential corresponding to a resistance value of an external resistor;
Potential determining means for comparing the two potentials to determine one potential and outputting a signal corresponding to the determined potential ;
Code gate means for outputting a corresponding code signal based on the judgment output of the potential judgment means, and a plurality of output transistor circuits driven by the code output of the code gate means to change the output impedance thereof , Between the potential generating means and the power supply connected thereto
Between the single potential generating means and a power supply connected thereto.
Switch means at the output end of the discriminating means.
And a latch means is provided at an output end of the code gate means.
The code gate means is output by the latch means.
Latch the force and turn off the switch at the same time
A semiconductor integrated circuit characterized by having such a configuration . 2. A reference potential generator for generating a plurality of reference potentials.
Generation means and one potential corresponding to the resistance value of the external resistor.
Means for generating a single potential;
The two potentials are compared to determine the potential of one potential.
Potential determining means for outputting a signal corresponding to the different potential;
A corresponding code based on the discrimination output of the potential discrimination means
Code gate means for outputting a signal, and the code gate
Driven by the code output of the means, its output impedance
A plurality of output transistor circuits for changing the
The code gate means includes a plurality of MOs each having a drain or a source connected to the highest potential or the lowest potential.
A plurality of S-transistors constitute a set in units of plural units, and the connection form of the highest potential and the lowest potential of the MOS transistor differs between each set, and one of the sets is selected. MOS to do
A semiconductor integrated circuit which outputs a potential from each source or drain of a transistor. Wherein said reference potential generating means is constituted by a plurality of connected resistors between the power supply for generating a plurality of reference potential, wherein said single potential generating means external resistor and multiple connected between the power supply is composed of a resistor, the potential determining means includes a plurality of comparators for comparing the plurality of reference potential and one potential, the output of the two comparators for comparing the reference potential adjacent one of said plurality of comparators Are respectively input to a plurality of exclusive ORs (EX-O
R) a gate, wherein the code gate means comprises a MOS gate composed of a plurality of MOS transistors for generating and outputting a corresponding binary signal by using an output of the EX-OR gate as an input. Item 1 or 2
A semiconductor integrated circuit as described in the above . 4. The output transistor circuit according to claim 1, wherein
A plurality of logic gates having a binary output of the S gate as one input and one or more other input signals, and a plurality of parallel-connected output transistors driven by the logic gate to change output impedance. Term
4. The semiconductor integrated circuit according to any one of 1 to 3 . 5. The semiconductor integrated circuit according to claim 5, wherein the other input signal of said plurality of logic gates is an internal signal and high impedance control signal.