JPH11145817A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed and high stability circuit with which an input threshold voltage is does not fluctuate through process dispersion, the duty ratio of an external signal can be transmitted to the inside with high stability and the design margin of an internal circuit can be expanded. SOLUTION: This device is provided with an input voltage 1 for a reference voltage to be supplied to a resistor ladder composed of resistors 8, 9, 10 and 11, input terminal 2 of a comparator 5 to function as a CMOS input buffer, input terminal 3 of a comparator 6 as a TTL input buffer, and input terminal 4 of a comparator 7 as a GTL input buffer. The respective voltages of inverted inputs at the comparators 5, 6 and 7 are almost correspond to the CMOS input level, TTL input level and GTL input level of a general LSI and external signals from the input terminals 2, 3 and 4 to be inputted to the forward inputs of the comparators 5, 6 and 7 are respectively transmitted into the LSI, while being converted into high level signals when they are higher than the above inverted input voltage or while being converted into low level signals, when they are lower than the above inverted input voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to an input buffer of an integrated circuit having different input levels of CMOS, TTL, and GTL.

[0002]

2. Description of the Related Art Generally, the input level of an integrated circuit is CMOS.
Level and TTL level. The CMOS level and the TTL level have input thresholds of 2.5 V and 1.5 V, respectively, and transmit a high level when an external signal is higher than the input threshold level, and transmit a low level when the signal is lower than the input threshold level. In recent years, a GTL with an input threshold of 0.8 V suitable for signal transmission exceeding 100 MHz is used.
There are also levels.

FIG. 4 shows a conventional input circuit for transmitting these input levels to the inside of an LSI. In the figure, 2 is C
The input terminal 3 of the MOS input buffer 12 is the input terminal of the TTL input buffer 13, and the input terminals 4 and 15 are the input terminals of the GTL input buffer 14. The CMOS input buffer 12 and the TTL input buffer 13 have input stages designed to obtain the desired input levels of the transistor dimensions. The GTL input buffer 14 has a differential input stage.
, And an external input signal is applied to the non-inverting input from the input terminal 4. If the external input signal is higher than the reference voltage, a high level is transmitted, and if the external input signal is low, a low level is transmitted.

However, in the conventional circuit shown in FIG. 4, when the input level fluctuates due to process variations between the CMOS level and the TTL level, the duty ratio of the external signal cannot be transmitted accurately. For example, a rise time of 1 V / ns and a fall time of 0.5 V / n
An input buffer having an input threshold voltage of 2.5 V with respect to an external signal of 60 MHz with a duty of 50% having a s of 2.5 s becomes 2.5 V threshold voltage when the input threshold voltage becomes 2 V due to process variation. The rise is transmitted earlier by the time represented by 0.5V ÷ 1V / ns = 0.5ns, and the fall is caused by the time represented by 0.5V ÷ 0.5V / ns = 1ns , Transmitted late. Therefore, the duty ratio of the transmitted signal is (8.3 ns + 1.5 ns) ÷ 16.7 ns = 58.7.
% Become.

In recent years, the speed of integrated circuits has been remarkably increased, and the internal Tpd has become less than 0.2 ns. Naturally, the setup time and the hold time of the clock signal and the data signal in the synchronous circuit are also at the same level as the internal Tpd. In such a situation,
If the duty ratio fluctuates as much as 10% due to the fluctuation of the input threshold as described above, a malfunction obviously occurs without a circuit margin.

On the other hand, if a differential input is used, a highly stable input threshold can be obtained. As a logic circuit using a differential input, there is a logic circuit for the same multi-level signal as shown in FIG. 2 of JP-A-59-176781.

[0007]

However, the input circuit described in this publication cannot cope with different binary signals of CMOS level, TTL level and GTL level.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem. In an input circuit to which binary signals of different levels are input, there is no change in input threshold voltage due to process variations, and the duty ratio of an external signal is reduced. It is an object of the present invention to provide a semiconductor integrated circuit device capable of transmitting data stably to the inside, expanding a design margin of an internal circuit, and obtaining a high-speed and highly stable circuit.

[0009]

A semiconductor integrated circuit device according to the present invention has an input terminal to which a binary signal of a different level is input, and the input terminal connected to one input of a comparator corresponding to the different level. First connecting means for connecting a plurality of series-connected resistive elements to divide a reference voltage at a reference voltage input terminal and obtain a plurality of reference voltages corresponding to the different levels; Second connection means for inputting a reference voltage corresponding to the level to the other input of the comparator.

Another semiconductor integrated circuit device according to the present invention comprises:
A reference voltage input terminal to which a reference voltage is input; an external signal input terminal to which binary signals of different levels are input; a plurality of comparators corresponding to the different levels; and the external signal input terminal is one of the comparators. First connection means for connecting to an input, and a plurality of series-connected resistive elements incorporated in the integrated circuit device for dividing a reference voltage at the reference voltage input terminal to obtain a plurality of reference voltages corresponding to the different levels And second connection means for inputting a reference voltage corresponding to the different level to the other input of the comparator.

In this semiconductor integrated circuit device, the different levels are a CMOS input level, a TTL input level, and a GTL input level of an LSI, and the comparator operates equivalently to a CMOS input buffer, a TTL input buffer, and a GTL input buffer. Or the different levels are an LVCMOS input level, a PCI input level, and a GTL input level of an LSI, and the comparator
It can be configured to operate equivalently to a CMOS input buffer, a PCI input buffer, and a GTL input buffer.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 shows an input circuit of a semiconductor integrated circuit device according to an embodiment of the present invention. 1 is a resistor 8, 9, 10, 11
Input terminal of a reference voltage to be supplied to a resistor ladder composed of 2 input terminals of a comparator 5 functioning as a CMOS input buffer, 3 input terminals of a comparator 6 functioning as a TTL input buffer, and 4 a comparator functioning as a GTL input buffer 7 is an input terminal.

Each of the resistors 8, 9, 10, and 11 has a resistance of 2 kΩ.
Assuming that the reference voltage of the input terminal 1 is 3.2 V, voltages of 2.4 V, 1.6 V, and 0.8 V are transmitted to inverting inputs of the comparators 5, 6, and 7, respectively.
These voltages substantially correspond to the CMOS input level, TTL input level, and GTL input level of a general LSI.

In the input circuit of the present embodiment thus configured, external signals from the input terminals 2, 3, and 4 input to the non-inverting inputs of the comparators 5, 6, and 7 are 2.4 respectively.
V, 1.6 V, and 0.8 V, the signal is converted into a high-level signal, and if it is lower, the signal is converted into a low-level signal and transmitted to the inside of the LSI. That is, the comparators 5, 6, and 7 are CMOS
The operation is completely equivalent to the input buffer, TTL input buffer, and GTL input buffer. The variation of the input threshold due to the process variation is caused by the variation of the input offset voltage of the differential stage and the variation of the voltage dividing ratio of the resistor ladder. Therefore, the fluctuation of the duty ratio does not matter at all.

FIG. 3 is an internal circuit diagram of the comparators 5 to 7 used in this embodiment. Q _p1 and Q _n1 are bias circuits, Q _p2 is a constant current source circuit, Q _n2 ,
Q _n3 , Q _n4 and Q _n5 are differential stages. And Q _p3 and Q
_{This is an n5} amplifier circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. 23 is a resistor 19, 20, 21, 22
An input terminal of a reference voltage to be supplied to a resistor ladder, 24 is an input terminal of a comparator 16 functioning as an LVCMOS input buffer, 25 is an input terminal of a comparator 17 functioning as a PCI input buffer, and 26 is a GTL input buffer. This is an input terminal of the comparator 18 to be operated.

Each of the resistors 19, 20, 21, and 22 is 2K
Ω, 1 KΩ, 2 KΩ, 4 KΩ and the reference voltage of the input terminal 23 is 1.8 V, the inverting inputs of the comparators 16, 17, 18 are 1.4 V, 1.
Voltages of 2V and 0.8V are transmitted. These voltages substantially correspond to the LVCMOS input level, the PCI input level, and the GTL input level in the 3.3 V power supply LSI.

In the input circuit of the present embodiment having the above-described configuration, the comparators 16, 17, and 18 are connected to the LVCM.
The operation is completely equivalent to the OS input buffer, the PCI input buffer, and the GTL input buffer. Similarly to the first embodiment, the variation of the input threshold due to the process variation is caused by the variation of the input offset voltage of the differential stage and the variation of the voltage dividing ratio of the resistor ladder. Degree and extremely small. Therefore,
Fluctuation of the duty ratio does not matter at all.

[0019]

As described in detail above, according to the present invention,
Since the fluctuation of the input threshold voltage due to the process variation is extremely small, the duty ratio of the external signal can be transmitted to the inside with high stability. Thereby, the design margin of the internal circuit can be increased, and a high-speed and highly stable circuit operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an internal circuit of a comparator used in the present embodiment.

FIG. 4 is a circuit diagram showing a conventional input circuit.

[Explanation of symbols]

Reference voltage input terminals 2, 3, 4, 24, 25, 26; external signal input terminals 5, 6, 7, 16, 17, 18, 18; comparators 8, 9, 10, 11, 19, 20, 21 , 22; resistance element

Claims (4)

[Claims] 1. An input terminal to which a binary signal of a different level is input, first connection means for connecting the input terminal to one input of a comparator corresponding to the different level, and a built-in integrated circuit device. A plurality of series-connected resistor elements for dividing the reference voltage of the reference voltage input terminal to obtain a plurality of reference voltages corresponding to the different levels; and a reference voltage corresponding to the different levels to the other input of the comparator. And a second connection means for inputting. 2. A reference voltage input terminal to which a reference voltage is input, an external signal input terminal to which binary signals of different levels are input, a plurality of comparators corresponding to the different levels, and the external signal input terminal. First connecting means for connecting to one input of the comparator, and a plurality of series circuits which are incorporated in the integrated circuit device and divide a reference voltage of the reference voltage input terminal to obtain a plurality of reference voltages corresponding to the different levels. A semiconductor integrated circuit device comprising: a connected resistive element; and second connecting means for inputting a reference voltage corresponding to the different level to the other input of the comparator. 3. The different level is a CMOS input level, a TTL input level, and a GTL input level of an LSI, and the comparator is a CMOS input buffer, TTL
3. The semiconductor integrated circuit device according to claim 1, wherein an operation equivalent to an input buffer and a GTL input buffer is performed. 4. The method according to claim 1, wherein the different level is an LVCMO of an LSI.
S input level, PCI input level, GTL input level, and the comparator is an LVCMOS input buffer,
3. The semiconductor integrated circuit device according to claim 1, wherein an operation equivalent to a PCI input buffer and a GTL input buffer is performed.