JPH11251206A - Semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate distinguishing between front and back surfaces and rough alignment, even when a semiconductor wafer has breaks and cracks while alignment precision of the semiconductor wafer with large diameter is improved by providing a plurality of notches with different sizes and shapes in the periphery of the semiconductor wafer. SOLUTION: Notches 2a-2d, each having a different area, are provided on the circumference 1c of a semiconductor wafer 1. The notches 2a-2d are provided on contacts of diagonals 1d with the circumference 1c, with only the length in the circumference direction (circumference length) being different and the distance in the radial direction being identical, to the center 1a, at least a portion of which is straight. In this way, alignment precision of large semiconductor wafer 1 is improved. Even though the breaks and cracks occur on the semiconductor wafer 1 and parts of the notches 2a-2d do not function, the distinction between front and back surfaces and rough alignment of the semiconductor wafer 1 can be readily performed with other notches.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor wafer, and more particularly, to a semiconductor wafer having a notch.

[0002]

2. Description of the Related Art Orientation flats have been provided on conventional semiconductor wafers in order to distinguish between front and back surfaces and to perform rough alignment. However, by providing this orientation flat, the symmetry of the wafer is impaired. For example, when a resist is applied, there is a case where the resist agent cannot be applied uniformly due to eccentricity.

As a countermeasure, one notch is provided at the peripheral portion of the semiconductor wafer to almost eliminate the deviation between the center of the wafer and the actual center of gravity. However, since this small notch is formed so that its shape changes continuously, there is a drawback that an alignment error increases when performing rough alignment.

In order to eliminate this drawback, Japanese Patent Application Laid-Open No. 2-240
As described in Japanese Patent Application Laid-Open No. 912, a device that changes the shape of a notch discontinuously has been proposed. This will be described below with reference to FIG.

As shown in FIG. 5, the semiconductor wafer 1 is a wafer in which a notch 2 is formed in a peripheral portion of a circular semiconductor wafer 1, and the notch 2 is moved in accordance with a change in position toward the center. A stair shape that changes discontinuously,
In addition, the shape of the notch 2 is left-right asymmetric with respect to a diagonal line (center line) 1b from the center point 1a.

Since the notch 2 has a discontinuous shape and is asymmetrical in the left and right directions, a change in the presence or absence of detected light when a photosensor is used can be confirmed at a plurality of locations. It is said that alignment accuracy is improved.

[0007]

A first problem is that, in the prior art, rough alignment of the entire large-diameter semiconductor wafer cannot be performed with the desired accuracy.
The reason is that the notch is locally provided on the semiconductor wafer, and therefore, it is not possible to assist the semiconductor wafer against distortion or the like.

A second problem is that rough alignment cannot be performed due to a crack or the like at a notch portion of a semiconductor wafer. The reason is that alignment is performed using notches formed only in local portions of the entire semiconductor wafer as described above.

SUMMARY OF THE INVENTION It is an object of the present invention to improve the alignment accuracy of a semiconductor wafer having a large diameter, to facilitate the distinction between the front and back of a semiconductor wafer having a chip or a crack, and to perform a rough alignment, thereby improving the productivity. It is to provide a semiconductor wafer that can be used.

[0010]

A semiconductor wafer according to the present invention has a plurality of notches having different sizes and shapes.

[0011]

The formation of a semiconductor device on a semiconductor wafer is performed by using a photolithography technique or the like. In photolithography technology, alignment accuracy of a semiconductor wafer is important.

As a method of performing rough alignment of a semiconductor wafer, a method of utilizing transmission from a notch portion using a transmission sensor is generally used. However, a plurality of notches and an area of each notch are made different. The transmission time of each notch can be varied. By utilizing the different transmission times, rough alignment of the entire semiconductor wafer can be easily performed with higher accuracy.

[0013]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a top view of a semiconductor wafer according to an embodiment of the present invention, and FIG. 2 is an enlarged view of a notch portion of the semiconductor wafer.

Referring to FIGS. 1 and 2, four notches 2 (2a to 2d) having different areas are provided on a circumference 1c of a circular semiconductor wafer 1. These notches 2 differ from the center point 1a only in the circumferential length (circumferential length) 1d at the contact point between the diagonal line 1b and the circumference 1c, and the center point direction distance 1e is at least partially They are straight and of the same length. The distance 1e in the direction of the center point is
Is preferably about 1% to 2% of the diameter in the case where is circular.

According to the embodiment configured as described above, even if a chip or a crack occurs in a large-diameter semiconductor wafer and some of the notches do not function, the semiconductor wafer is not removed by a plurality of other notches. And rough alignment can be easily performed.

When performing rough alignment of a semiconductor wafer, the presence or absence of light reflection at a notch 2 provided on the wafer is generally used. This will be described below with reference to FIG.

In FIG. 3, the light emitting section 3 and the light receiving section 4 are located at the notch 2 of the semiconductor wafer 1 at positions where light passing through the lens 5 can be transmitted and received. The semiconductor wafer 1 conveyed to the stage 6 is rotated by the stage controller 7 in the circumferential direction around the center point and aligned.

Here, when the notch 2 does not exist in the circumferential portion of the semiconductor wafer 1, the light from the light emitting section 3 is blocked by the semiconductor wafer 1 and does not reach the light receiving section 4.

Conversely, in a portion where the notch 2 is present in the circumferential portion of the semiconductor wafer 1, the light receiving portion 4 is turned on by the light emitting portion 3 for a time dependent on the rotation speed of the stage 6 and the circumferential length 1d of the notch 2. Receive light from FIG. 4 shows the state of the light receiving time when the wafer having the four notches 2a to 2d shown in FIG. 1 is used.

The time when the semiconductor wafer 1 makes one rotation is one round time 9 and the light receiving time (sec) of each notch is 1
0a to 10d, and the light receiving time is determined by the circumferential length 1d of the formed notch. When the semiconductor wafer 1 has a distortion or the like and the light receiving times 10a, 10b, 10c, and 10d vary, for example, 10a ¹ = 10a + α (sec
9, 10b ¹ = 10b + β (sec), 10c ¹ = 10
When c + γ (sec) and 10d ¹ = 10d + δ (sec), the data aligned with 10a / 2 as the center is changed to [(α + β + γ + δ) / 4 + 10
The microcomputer 8 controls the stage controller 7 so that the alignment is performed as [a] / 2.

Further, when chips or cracks occur in the notch 2 and 10a, 10b, 10c and 10d exceed the allowable range, for example, when 10b exceeds the allowable range,
The data of 10b is deleted and the other data is controlled so that the data aligned with a / 2 as the center is aligned as [(α + γ + δ) / 3 + 10a] / 2.

In this way, the semiconductor wafer 1 is rotated to a predetermined position, and the XY stage controls the position in the X and Y directions.

In the above embodiment, a semiconductor wafer having four notches has been described, but the number of notches may be two or more.

[0025]

The first effect is that the alignment accuracy of the entire semiconductor wafer is improved. Thereby, even if the semiconductor wafer has a distortion or the like, it becomes possible to cope with the distortion. The reason for this is that a plurality of notches of different sizes are provided at independent locations on the semiconductor wafer.

The second effect is that the number of cases where the semiconductor wafer cannot be aligned is reduced. This makes it possible to cope with the occurrence of chips and cracks. This is because a plurality of notches having different sizes are provided as described above.

[Brief description of the drawings]

FIG. 1 is a top view of a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a notch portion of the semiconductor wafer.

FIG. 3 is a diagram showing how a semiconductor wafer of the present invention is aligned.

FIG. 4 is a time chart of the illuminance of the light receiving unit when the semiconductor wafer is rotating.

FIG. 5 is a top view of a prior art semiconductor wafer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Center point 1b Diagonal line 1c Circumference 1d Circumference length 1e Distance to center point direction 2 (2a to 2d) Notch 3 Light emitting unit 4 Light receiving unit 5 Lens 6 Stage 7 Stage control device 8 Microcomputer 9 1 round time

Claims (3)

[Claims] 1. A semiconductor wafer having a plurality of notches in a peripheral portion. 2. The semiconductor wafer according to claim 1, wherein the plurality of notches have different areas. 3. The semiconductor wafer according to claim 1, wherein the shape of the notch includes a portion in which lines at both ends of the notch facing the center of the wafer change discontinuously.