JPH11250700A - Memory mixed semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory mixed semiconductor integrated circuit in which a test circuit for operating the efficient test of a large-scaled memory macro by a few terminals for test is incorporated. SOLUTION: A memory macro 11 is mixed with a logic part 12, and provided with a test circuit 20 for decoding a coded input signal for test supplied to an input terminal 17 for test for testing the memory macro 11, and test-operating the memory macro 11 without the logic part 12. The test circuit 20 is provided with a signal generating circuit 16 for decoding a coded memory control signal among input signals, and selectively performing direct access to the memory macro 11 according to the memory control signal and non-coded address signal and data signal for executing the test operation, and a control circuit 15 for decoding coded memory macro activation signal and memory macro selection signal among input signals for test, and selectively activating the signal generating circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a memory macro is mounted together with a logic section on a single chip, and more particularly to a memory integrated semiconductor integrated circuit having a built-in test circuit for testing a memory macro.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit (LS) in which a large-scale memory macro is mixed in an ASIC, a microprocessor, or the like.
Various I) have been proposed. This type of memory embedded LSI
In, the normal operation of the memory macro is controlled by a signal from the logic unit. For example, when a read command is issued from the logic unit, the memory macro outputs data at the selected address to the logic unit. Similarly, when a write command is input from the logic unit, data input simultaneously with the command is written to the address of the selected memory macro.

There are two methods for testing a memory macro in this type of memory-embedded LSI. One is a method of performing a test by controlling the operation of a memory macro through a logic unit without providing a dedicated test circuit, and the other is a built-in dedicated test circuit and a test input / output terminal. And a test is performed independently of the logic unit. The former method is not practical because the vector length is long in a large-scale memory macro, and the latter test method is generally used.

[0004] The test circuit of the embedded memory is mainly composed of a multiplexer that switches a normal operation signal to and from the logic section and a test signal from a test input / output terminal by a test mode signal. As a test input / output terminal, a terminal for inputting / outputting an address signal, a data signal, and other control signals is provided as in a normal memory operation, and a test is performed by a method called direct access. In this direct access method, all signals for which a memory macro is defined in specifications are required as test signals.

[0005]

The above-described conventional test circuit for an embedded memory has the advantage that a test similar to that of a general-purpose memory can be performed. On the other hand, when the number of memory macro signals increases, the number of test signals also increases. Thus, there is a problem that the increase in the test bus width affects the chip size, or that the test bus width does not match the ASIC with a small number of pins. In addition, since the memory capacity of the embedded memory has been increasing due to the recent technological development, it is necessary to test a large number of memory cards at the same time to reduce the cost in the shipping test. There is a problem that it cannot be manufactured or that the number of memories for simultaneous measurement must be reduced.

The present invention has been made in consideration of the above circumstances, and enables a large-scale memory macro to be tested with a small number of test terminals, so that an efficient test can be performed even when the memory capacity or data bit configuration changes. It is an object of the present invention to provide a memory-integrated semiconductor integrated circuit having a built-in test circuit for facilitating multi-product development and mass production of ASICs.

[0007]

In a memory integrated semiconductor integrated circuit according to the present invention, a memory macro embedded together with a logic part and a test input signal for testing the memory macro are coded and input. A test input terminal, a test output terminal from which an output signal obtained by a test operation of the memory macro is extracted, and a coded test input signal supplied to the test input terminal for decoding the memory macro. And a test circuit for performing a test operation without using the logic unit.

In the memory-integrated semiconductor integrated circuit according to the present invention, a plurality of memory macros embedded together with a logic unit and a test input signal for testing these memory macros are partially coded and input. A test input terminal shared by each memory macro, an output signal obtained by a test operation of each memory macro is taken out, and supplied to the test output terminal shared by each memory macro and the test input terminal. And a test circuit provided for each memory macro for decoding the coded input signal for test and performing a test operation on each of the memory macros without passing through the logic unit.

The test circuit according to the present invention includes, for example,
The coded memory control signal is decoded among the test input signals supplied to the test input terminal, and the memory macro is selected based on the decoded memory control signal and the uncoded address signal and data signal. A signal generation circuit for performing direct access by performing a test operation, and decoding and decoding a coded memory macro activation signal and a memory macro selection signal among test input signals supplied to the test input terminal. And a control circuit for selectively activating the generation circuit.

The control circuit in the test circuit is, for example,
A control main decoder for decoding a memory macro activation signal, a selection decoder for decoding a memory macro selection signal, and a memory macro test operation controlled by outputs of the control main decoder and the selection decoder. And a latch circuit for outputting a test enable signal.

Further, the control circuit of the test circuit further preferably includes a test operation determining circuit for performing a test mode control of the memory macro by a password signal and a clear signal output from the control main decoder.

Further, the signal generating circuit of the test circuit preferably receives the test input signal supplied to the test input terminal and converts the uncoded address signal and data signal of the test input signal. A receiver circuit for transferring the memory macro as it is to the memory macro; a command decoder for decoding a coded memory control signal among the test input signals received by the receiver circuit and transferring the coded memory control signal to the memory macro; A byte control circuit controlled by the output of the circuit to control the test operation of the memory macro in byte units.

In the present invention, in order to test the embedded memory macro, a dedicated test circuit for directly accessing the memory macro without using a logic unit is provided. In this case, the test input signal to the external test input terminal is coded according to the test specification and given. Specifically, at least various other control signals except the address signal and the data signal of the memory macro are provided. The test circuit has a built-in decoder for decoding various control signals. Thus, the number of test input terminals can be reduced.

In the present invention, when a plurality of memory macros are mounted, a test circuit is provided corresponding to each memory macro. In this way, by performing the circuit and layout design with the test circuit portion as a unit, there is an advantage that the design change when the number of memory macros to be mounted is changed becomes extremely simple. Since the size of the test circuit is small, the effect on the chip size of the LSI is small even if it is provided for each memory macro.

A signal generating circuit for decoding a coded memory control signal and selectively directly accessing a memory macro in accordance with the decoded memory control signal and an uncoded address and data signal. And a control circuit for decoding a coded memory macro activation signal and a memory macro selection signal to selectively activate a signal generation circuit, thereby realizing a direct access method with a reduced number of test terminals. It is possible to test memory macros with a high degree of freedom.

Further, according to the present invention, a test operation determining circuit for controlling a test mode of a memory macro by a password signal and a clear signal output from a control main decoder is provided in a control circuit of the test circuit.
It is possible to perform control such that the apparatus does not operate unless a predetermined password code is input after the power is turned on, thereby preventing malfunction in a normal operation state. Further, when the test operation determination circuit is not selected, it is possible to set a no operation (NOP) mode in which the memory macro is not operated.

Further, in the present invention, by providing a byte control circuit for controlling the test operation of the memory macro on a byte basis in the signal generation circuit of the test circuit, the test operation on a byte basis becomes possible. Normally, the embedded memory has a mask function of prohibiting writing in units of bytes with a multi-bit width, and it is common to multiplex up to a testable bit width at the time of testing in order to support this multi-bit. On the other hand, according to the present invention, by providing the byte control circuit, it is possible to control the data input / output of the memory macro in byte units. This allows
For read data, an efficient read operation test with a reduced data bus width is possible. Also, at the time of writing, a write operation test with an arbitrary bit width of 1 byte or several bytes is performed by controlling a common write data line and a mask signal for enabling or disabling a mask function with a byte selection signal. Can be.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a conceptual layout of a memory-embedded LSI chip 1 according to one embodiment. In this embodiment, two memory macros 11 (11a and 11b) are mounted on the LSI chip 1 together with the logic unit 12. The memory macro 11 is, for example, a DRAM.

For each memory macro 11,
A test circuit 20 (20a, 20b) having the same configuration is provided. The LSI chip 1 has two test circuits 20
, A plurality of test input terminals 17 for inputting test input signals TESTIN, and a test output signal T
A plurality of test output terminals 18 for extracting ESTOUT
Is provided. In order to test one of the memory macros 11 by sharing the input / output terminals, the two test circuits 20 incorporate a selection decoder as described later,
Only one of them is activated.

Test input signal TES from outside the chip
The TIN includes a test mode signal TM for controlling the test mode of the memory macro 11 and test control signals S1 to Sn for controlling the control circuit 15 and the signal generation circuit 16, as shown in FIG. Here, the test control signals S1 to S1
Sn is a signal (memory macro selection signal, memory macro activation signal, etc.) for selectively activating any one of the memory macros 11, an address signal used for normal operation of the memory macro 11, It includes data signals and other various memory control signals (read enable signal, write enable signal, precharge signal, address strobe signal, reference signal, etc.). What is important in this embodiment is that, of these test control signals S1 to Sn, the address signal and the data signal of the memory macro 11 are directly supplied to the memory macro 11 as they are, and the other control signals are coded. Is to be given.

As a result, the number of test input terminals 17 can be significantly reduced as compared with the case of performing a test by the conventional direct access method, while allowing the memory macro 11 to be directly accessed. Specifically, by coding the test input signals excluding the address signal and the data signal, the number of test input terminals conventionally required about 10 can be reduced to about 5 and about half.

The test circuit 20 supplies a test input signal TESTI from outside the chip when testing the memory macro 11.
N operates with a receiver circuit 14 (14a, 14b) receiving N and an output signal SCMD from the receiver circuit 14,
A control circuit 15 (15a, 15b) for controlling the test circuit 20 in units of the memory macro 11 operates with output signals from the control circuit 15 and the receiver circuit 14, and the memory macro 11 performs input and output with the logic unit 12. A signal generation circuit 16 (16) that generates signals (ie, address signals, data signals, and memory control signals) having the same meaning as the signal for performing
a, 16b) and a driver circuit 13 (13a, 13b) for transferring the test output data signal QMC from the memory macro 11 to the outside of the chip.

In this embodiment, the test circuits 20 having the same configuration are provided for the respective memory macros 11 mainly for the convenience of design. As a design concept, it is conceivable to provide one test circuit 20 for a plurality of memory macros 11. However, in this case, when the number of mounted memory macros is changed, it is necessary to change the design of the test circuit. On the other hand, if the test circuit 20 is designed as a group of circuits and layouts, and the same test circuit is directly transferred when the number of memory macros is increased, the LSI can be easily implemented.
Can be changed.

FIG. 2 shows a conceptual configuration of the memory macro 11 to be mounted. Memory macro 11 as shown
A core circuit 21 including a memory cell array 201, a column decoder / sense amplifier 202, a row decoder 203, a predecoder / control circuit 204, and a data buffer 205; Having. Further, the memory macro 11 has a test signal input / output circuit 23 for transmitting and receiving a test signal between the test circuit 20 shown in FIG. The embedded memory macro 11 has a wider data bit width than an ordinary general-purpose memory.
It is set to about 8 bits or 256 bits.

FIG. 3 shows a specific circuit example of the receiver circuit 14 in the test circuit 20. As illustrated, the receiver circuit 14 includes a buffer circuit 3 to which the test mode signal TM and other test control signals S1 to Sn are input.
1, 32 (321 to 32n) and the test mode signal TM obtained in the buffer circuit 31 as one input, and an AND gate 33 using the output of the buffer circuit 32 as the other input.
(331 to 33n). As a logical result of the AND gate 33, output signals SCMD (SCMD1 to SCMDn) are obtained only in the test mode. The output signal SCMD is “0” when the test mode signal TM is logically “0”, and when the test mode signal TM is logically “1”, the input control signal S has the same logic as the signal SCMD. Is output.

In this embodiment, the test of the memory macro 11 is enabled when the test mode signal TM is "1". However, when the test of the memory macro 11 is valid when the logic is "0", the buffer circuit 31 is activated. What is necessary is just to change into an inversion buffer (inverter circuit).

FIG. 4 shows a specific circuit example of the driver circuit 13 in the test circuit 20. Control circuit 15
Provides a test enable signal MCE for enabling the memory macro 11 to be selectively tested, as will be described later. The test output signal Q
MC (QMC1 to QMCm) is obtained. The driver circuit 13 includes an output buffer circuit 41 to which a test output signal QMC from the memory macro 11 is input, and a tri-state buffer circuit 42 (42) that controls and extracts an output of the output buffer circuit 41 by a test enable signal MCE.
1 to 42 m).

When the test enable signal MCE from the control circuit 15 is active, the output signal OU of the driver circuit 13
TMC (OUTMC1 to OUTMCm) is output in the same logic as the test output signal QMC from the memory macro 11,
This is a test output signal TESTOU which is taken out to the outside.
It becomes T. When the test enable signal MCE is inactive, the output of the buffer circuit 42 is in a high impedance state.

In FIG. 4, the test output signal OUTMC is generally indicated by m bits, but is actually output in byte units (8 bits or 16 bits) as described later. As shown in FIG. 1, the output of the driver circuit 13 of each memory macro 11 is commonly connected to the test output terminal 18 by the logic unit 12, and the output signal OUTMC is externally supplied to one memory. It is output as an output signal for the macro.

FIG. 5 shows a specific circuit example of the control circuit 15 in the test circuit 20. The control circuit 15 activates the memory macro 11 from among the signals other than the memory macro control signal directly sent to the signal generation circuit 16 in the output signal SCMD from the receiver circuit 14. Coded signals such as a clear signal, a clear signal, and a password signal (in the figure, SCMD
1, a control main decoder circuit 51 for decoding two bits of SCMD2, and a memory macro selection signal (SCMD3, SMD in the figure) which is also coded.
The macro selection decoder 52 decodes the two bits of the CMD4.

When a memory macro activation command is input, a memory macro activation signal MC decoded by the control main decoder 51 is multiplied by an AND gate 53 with a gate signal GATE (for example, a clock signal). , The gates of the latch circuits 541 and 542 for selectively activating the memory macro 11 are enabled. These latch circuits 541 and 542 are transparent latch circuits having a reset or preset function.

When a memory macro selection signal is input,
Signals E1, E decoded by macro selection decoder 52
Reference numeral 2 denotes a complementary signal that is valid for one of them, and this is input to the latch circuits 541 and 542, respectively. As a result, the latch circuits 541 and 542 provide the test enable signals MCE1 and MCE2 for which one of them is valid.
Is output.

In FIG. 5, the inputs of the macro selection decoder 52 are illustrated as SCMD1 and SCMD2.
When there are two memory macros 11, two test enable signals MCE1 and MCE2 are decoded. According to this example, the input of the macro selection decoder 52 is actually one bit.

The control circuit 15 includes a latch circuit 55,
A test operation determination circuit 58 including an inverter 56 and an OR gate 57 is provided. The latch circuit 55 is of a set-reset type, and controls a no operation (NOP) mode in which basically no operation of the memory macro 11 is performed. That is, a ready signal MCRDY indicating that the memory macro 11 is operable (for example, power is turned on) is output from the memory macro 11 by the latch circuit 5.
5, the reset signal RESET is valid (RESET = "1") until the password signal PWD is input even if the operation is enabled by turning on the power. During this time, the latch circuits 541 and 542 are also reset. Then, the memory macro 11 is set to the NOP mode.

The control main decoder 51 decodes the password signal code instructing the start of the test operation, and when the password signal PWD becomes valid (PWD = "1"), the latch circuit 55 is set and the reset signal RESET is set.
Is reset (RESET = "0"). Further, a reset signal command instructing stop of the test operation is decoded by the control main decoder 51, and the clear signal CLR becomes valid (CL
When R = “1”), the reset signal RESETT becomes valid via the off gate 57 (RESET = “1”).
"1"), and the latch circuit 54 for test enable
1, 542 are reset, and the memory macro 11 is set to the NOP mode. That is, the reset signal RESET is valid even when the ready signal MCRDY from the memory macro 11 is not selected, and the latch circuit 55 holds the reset signal RESET in a valid state until the set terminal S becomes valid.

The test circuit 20 of this embodiment has many latch circuits in order to enable an advanced and flexible memory macro test. However, there is a possibility that an erroneous signal may be latched due to power-on and noise. have. The above-mentioned bus word signal PWD has a function of preventing such an erroneous signal latch, and a command for validating the password signal PWD is always supplied as an input signal from outside the chip before the memory macro 11 is tested. There must be.

The control circuit 15 shown in FIG. 5 includes two latch circuits 541 and 54 corresponding to the two memory macros 11.
2 and one of the test enable signals MCE1 and MCE1 is valid. Therefore, the test control of the two memory macros 11 can be performed by the one control circuit 15. However, in this embodiment, as described with reference to FIG.
Is provided. Therefore, in actual use, FIG.
Of the two latch circuits 541 and 542, only one valid one is used in accordance with each memory macro 11, and the other is left unused.

FIG. 6 shows a specific circuit example of the signal generation circuit 16 in the test circuit 20. Signal generation circuit 1
6 is an output signal SCMD from the receiver circuit 14 and a reset signal RESE which is an output signal from the control circuit 15.
T, test enable signal MCE and clock signal CL
A macro receiver circuit 61 having K as an input, a command decoder 62 for decoding a coded memory control signal of the signal BSCDM waveform-shaped by the macro receiver circuit 61, and a command decoder 6
A command generation circuit 63 and a byte control circuit 64 controlled by the two output signals. The output signal of the macro receiver circuit 61 includes, in addition to the coded memory control signal, an uncoded address signal ADRS and a write data signal DATA as a macro test signal to the memory macro 11. The signal and the data signal are transferred to the memory macro 11 as they are.

Of the signals supplied to the macro receiver circuit 61, the macro test signal S directly input from the receiver 14
The CMD is a key signal for testing the memory macro 11. Reset signal RE sent from control circuit 15
SET and the test enable signal MCE are signals that indicate that the memory macro 11 is in a testable state. The clock signal CLK is a basic signal necessary for a synchronous operation, and all operations operate in synchronization with the clock signal.

FIG. 7 is a specific circuit example of the macro receiver circuit 61. The clock signal CLK and the macro test signal SC are shown in FIG.
AND gates 71 and 72 to which MDs are respectively input;
An inverter 74 and an AND gate 73 for controlling the AND gates 71 and 72 with a combination of the reset signal RESET signal and the test enable signal MCE are provided. The reset signal RESET is treated as positive logic here, and is used as a signal for initializing each macro test signal held in an arbitrary state. The output of the AND gate 73 is valid when the corresponding memory macro 11 can be tested and is not in the initialization state. And
When the output of the AND gate 73 becomes valid, the clock signal CLK and the macro test signal BSCMD are output from the AND gates 71 and 72, respectively. When the output of the AND gate 73 is invalid, it is fixed to logic "0".

In this embodiment, the NOP command is defined as when all external test inputs are set to logic "0". If the test enable signal MCE is invalid or the reset signal RESET is valid, the NOP command Is equivalent to

The command decoder circuit 62 is a simple decoder circuit which receives a test control signal BSCMD obtained by logically synthesizing an external test input signal in the macro receiver circuit 61, and outputs the decoded output signal to the command generation circuit 63. And the byte control circuit 64. As for the signal input to the byte control circuit 64, the test reading / reading of the memory macro 11 is performed in byte units.
This is a basic control signal for controlling writing. The signal input to the command generation circuit 63 is output as a memory control signal MCONT via a buffer for a macro test signal requiring a change in real time, and via a latch circuit for a signal requiring a state to be maintained. It is supplied to the memory macro 11. The latch circuit here needs a latch circuit with a reset function in order to satisfy the function of the reset signal RESET for initialization, and may be the set-reset type latch circuit used in the control circuit 15 described above. The memory control signal MCONT obtained from the command generation circuit 63 is, for example, a read enable signal or a write enable signal of the memory macro 11.

When the memory macro is of a synchronous type, each operation is made into a state machine, and various operation modes are expressed by commands. The code used in this embodiment conforms to this operation system, and has many latch circuits in the command generation circuit to hold the operation by the code. In this embodiment, in order to prevent a malfunction in a normal operation state, the test circuit has a feature that the test circuit does not operate unless a code determined at the time of design is inputted after the power is turned on, and a decoder circuit for recognizing the code is provided. And a test operation determination circuit composed of a set reset circuit. Thus, when the test operation determination circuit is not selected, it is possible to generate a NOP command that does not operate anything, which is one of the commands of the memory macro 11.

As described above, the memory macro to be mounted has a wide bit width of about 128 bits or 256 bits. However, at the time of testing, it is required to operate in 8-bit or 16-bit units, which is almost the same as that of general-purpose memory, due to the limitation of the number of test terminals. Therefore, in this embodiment, a byte control circuit 64 is provided as shown in FIG. 6 in order to perform a test in units of bytes, instead of multiplexing to a required bit width as in the related art.

FIG. 8 shows a block configuration of the byte control circuit 64, which comprises an address decoder circuit 81 and an address register circuit 82. The output signal BSCMD from the macro receiver circuit 61 and the decoder output control signal MLSW from the command decoder circuit 62 are input to the address decoder circuit 81.
The decoded output signals BSEL1 to BSEL8 are obtained. The address register circuit 82 includes an address decoder circuit 81
, A register control signal LDSW, an increment control signal INC, a reset signal RESET, and a clock signal BCLK from the command generation circuit 63, thereby outputting, for example, eight byte selection signals BTDQ1-8. Is done.

As shown in FIG. 9, the address decode circuit 81 includes eight decode outputs SD1 by a wired logic circuit 91 and an AND gate 92 for detecting coincidence of all combinations of the 3-bit signals BSCMD1 to BSCMD3. ~
8 and a decode part for read control for validating any one of the signals 8 and a 2-bit signal B by the wired logic circuit 93.
It has a decode part for write control to obtain decode outputs MD1 to MD8 which are alternately enabled four by four by repeating SCMD1 and BSCMD2. At the time of reading, the output data lines are shared, so that reading is performed only in units of 1 byte. Therefore, only one decoding output SD1 to SD8 is used for selecting 1 byte. Since several bytes can be selected at the same time for writing, the decode outputs MD1 to MD8 which are enabled four by four are used. A multiplexer 94 is provided to switch between them by the control signal MLSW.
These are decoded and output as SEL1 to SEL8.

FIG. 10 shows a configuration example of the address register 82 in FIG. 8, which is a shift register circuit in which eight flip-flops 2DFF1 to 8 having a reset function and a multiplexer function are connected. In each of the flip-flops 2DFF1 to 8, the decode outputs BSEL1 to BSEL8 from the address decoder 81 are input to the AI terminal, and the output from the preceding stage is input to the D terminal, respectively, to select which of the terminals AI and D is to be transferred internally. The byte selection signals BTDQ1 to BTDQ8 are output to the Q terminal under the control of the signal LDSW. Further, at the time of read control, an increment control signal INC and a clock BCLK are used.
Data shift control is performed.

That is, in the address decoder 81 shown in FIG. 9, during the read control in which the decode outputs SD1 to SD8 are selected, one of the 8-bit signals BSEL1 to BSEL8 is in the selected state. At this time, the increment control signal I
The NC is enabled, and the 8-bit byte selection signals BTDQ1 to BTDQ8 are sequentially selected in synchronization with the clock signal BCLK. On the other hand, the address decoder 81 shown in FIG.
In write control in which the decode outputs MD1 to MD8 are selected, an arbitrary number (four in the example of FIG. 9) of the 8-bit signals BSEL1 to BSEL8 are simultaneously enabled. At this time, by setting the increment control signal to the non-selection state, an arbitrary number of the 8-bit byte selection signals BTDQ1 to 8 holds the selection state.

As described above, at the time of test reading, sequential reading operation control is performed in byte units. Further, at the time of test writing, the writing operation can be controlled by freely selecting one byte to several bytes or all bytes. By enabling such a byte-by-byte test operation, coupled with the test input signal coding,
Not only is it possible to fit a small number of pins in an ASIC,
Even when the capacity of the memory macro or the bit configuration of the data is changed, an efficient test can be performed, and the development and mass production of a wide variety of ASICs can be facilitated. Also, as for the test at the time of shipment, a large number of tests can be performed at the same time, and the test cost can be reduced.

The data output circuit of the memory macro 11 for outputting test data in byte units by the above-described byte control circuit 64 includes, for example, eight byte selection signals BTDQ1 from the byte control circuit 64 as shown in FIG. ~
8 respectively controlled by the tri-state buffers T
BUF1 to BUF8. These buffers TB
One data in the selected state among UF1 to UF8 is output to common test data output buses TQ0 to TQ7. This corresponds to the test output signal QMC in FIG. On the other hand, the output data RD0 to 7, RD8 to 15,..., RDi to k of the memory macro 11 are taken out as they are as outputs Q0 to 7, Q8 to 15,.

FIG. 12 shows a configuration example of a data input circuit controlled by the byte control circuit 64 to input test data to the memory macro 11. Mixed memory macro 1
The first use is mostly related to image data processing, but in such a use, the above-described write-inhibit function (mask function) in byte units is used. In FIG. 12, an input circuit having such a mask function has a function of switching and inputting a test data signal. That is, the logic unit 1
2 are transferred to the inside of the memory macro via multiplexers MUXD1-8 and MUXM1-8, respectively. On the other hand, the byte selection signals BDTQ1 to BDTQ8 from the byte control circuit 64 are input to the mask signal multiplexers MUXM1 to MUXM8, respectively, and the test data signals TD0 to TD7 are input to the data input multiplexers MUXD1 to MUXD8. In this way, the test mode signal TM switches between the test mode and the normal mode.

As a result, in the test mode, the test write data signals TD0 to TD7 are simultaneously input to all the bytes, but only the selected byte among the byte selection signals BTDQ1 to BTDQ8 has the multiplexer MUX.
An operation is performed in which write data is transferred into the memory macro by one of D1 to D8.

[0053]

As described above, according to the present invention,
By providing a test input signal in a coded manner and by providing a dedicated test circuit for directly accessing a memory macro by decoding the coded test input signal, several memories embedded in one chip An efficient test can be performed with a small number of test input terminals for macros. Thereby, the memory embedded LS
It is possible to facilitate standardization for mass production of I and multi-product development.

[Brief description of the drawings]

FIG. 1 shows a schematic chip layout of a memory-embedded LSI chip according to an embodiment of the present invention.

FIG. 2 shows a schematic configuration of a memory macro in the embodiment.

FIG. 3 shows a configuration example of a receiver circuit in the test circuit of the embodiment.

FIG. 4 shows a configuration of a driver circuit in the test circuit of the embodiment.

FIG. 5 shows a configuration example of a control circuit in the test circuit of the embodiment.

FIG. 6 shows a configuration example of a signal generation circuit in the test circuit of the embodiment.

FIG. 7 shows a configuration example of a macro receiver circuit in the signal generation circuit.

FIG. 8 shows a configuration example of a byte control circuit in the signal generation circuit.

FIG. 9 shows a configuration example of an address decoder circuit in the byte control circuit.

FIG. 10 shows a configuration example of an address register circuit in the byte control circuit.

FIG. 11 shows a configuration example of a data output circuit of the memory macro of the embodiment.

FIG. 12 shows a configuration example of a data input circuit of the memory macro of the embodiment.

[Explanation of symbols]

1: LSI chip, 11a, 11b: memory macro, 1
2 Logic part, 20a, 20b Test circuit, 13
a, 13b: driver circuit, 14a, 14b: receiver circuit, 15a, 15b: control circuit, 16a, 16b: signal generation circuit, 51: control main decoder, 52: macro selection decoder, 541, 542: latch circuit, 58 ... test operation determination circuit, 61 ... macro receiver circuit, 62 ... command decoder circuit, 63 ... command generation circuit, 64 ...
Byte control circuit.

Claims (6)

[Claims] 1. A memory macro embedded together with a logic unit, a test input terminal into which a test input signal for testing the memory macro is coded and input, and a test operation of the memory macro A test output terminal from which an output signal is taken out, and a test circuit that decodes a coded test input signal supplied to the test input terminal and performs a test operation of the memory macro without passing through the logic unit. A memory-integrated semiconductor integrated circuit, comprising: 2. A plurality of memory macros embedded together with a logic unit, and a test input signal for testing these memory macros are partially coded and input, and are shared by each memory macro. An input terminal, an output signal obtained by a test operation of each of the memory macros is taken out, a test output terminal shared by each memory macro, and a coded test input signal supplied to the test input terminal A test circuit provided for each memory macro for decoding and performing a test operation by directly accessing each of the memory macros without passing through the logic unit;
A semiconductor integrated circuit with embedded memory, comprising: 3. The test circuit decodes a coded memory control signal among test input signals supplied to the test input terminal,
A signal generating circuit for selectively performing the test operation of the memory macro by the decoded memory control signal and the uncoded address signal and data signal; and a code included in the test input signal supplied to the test input terminal. 3. The memory according to claim 1, further comprising: a control circuit configured to decode the activated memory macro activation signal and the memory macro selection signal to selectively activate the signal generation circuit. 4. Mixed semiconductor integrated circuit. 4. The control circuit includes: a control main decoder for decoding the memory macro activation signal; a selection decoder for decoding the memory macro selection signal; and a control main decoder and an output of the selection main decoder. 4. The memory-embedded semiconductor integrated circuit according to claim 3, further comprising: a latch circuit that outputs a test enable signal to enable a test operation of the memory macro. 5. A control main decoder for decoding the memory macro activation signal, a password signal and a clear signal for instructing start and stop of a test operation, respectively, and decodes the memory macro selection signal. And a latch circuit that is controlled by the outputs of the control main decoder and the selection decoder to output a test enable signal that enables the memory macro to perform a test operation; and a password output from the control main decoder. 4. The memory-integrated semiconductor integrated circuit according to claim 3, further comprising: a test operation determination circuit that controls a test mode of the memory macro by a signal and a clear signal. 6. The signal generation circuit receives a test input signal supplied to the test input terminal, and converts an uncoded address signal and data signal of the test input signal into the memory as it is. A receiver circuit for transferring the macro to a macro; a command decoder circuit for decoding a coded memory control signal among the test input signals received by the receiver circuit and transferring the decoded signal to the memory macro; and an output of the command decoder circuit. 4. The memory-integrated semiconductor integrated circuit according to claim 3, further comprising: a byte control circuit that is controlled to control the test operation of the memory macro on a byte-by-byte basis.