JPH11250650A - Semiconductor device and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lessen the influence of a high parasitic capacitance component an outer terminal has at the time of signal input. SOLUTION: A high resistance element is inserted between an outer terminal 2 and output node of a monitor output circuit 5. The time const. of the resistance value R of the high resistance element 6 and output capacitance component C2 of the monitor output circuit 5 is set to about 10 times or more the period of a signal fed to an input buffer circuit 4. In the input operation of the input circuit, the charge-discharge operation about the parasitic capacitance component thereof becomes substantially negligible. In the high speed input operation of the input circuit, the situation that the input signal waveform would unnegligibly round or be disturbed can be avoided and the malfunction in the high speed input operation of the input circuit can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a configuration in which a monitor output circuit having a non-negligible capacitance component at an output node is connected to an external terminal common to an input circuit, thereby reducing the influence of the capacitance component. Technology
For example, the present invention relates to a technology effective when applied to an SDRAM (Synchronous Dynamic Random Access Memory).

[0002]

2. Description of the Related Art A semiconductor device can have an output function in consideration of a device test. For example, SDRAM
In order to make it possible to observe at the time of a device test whether or not the bootstrapped word line drive voltage (word line bootstrap voltage) has been boosted to a regular voltage, for example, a predetermined external terminal to which an address input circuit is connected A word line drive voltage monitor output circuit can be connected. This monitor output circuit has, for example, an output MOS transistor or the like as an output circuit for the word line drive voltage, and the output operation of the output MOS transistor is enabled in synchronization with the setting of the test mode.

[0003]

The inventor of the present invention has found that when the monitor output circuit and the input circuit share an external terminal, the influence of the parasitic capacitance at the output node of the monitor output circuit (such as the source of the output MOS transistor) is reduced. investigated. That is, a so-called diffusion capacitance is parasitic on an output node such as the source of the output MOS transistor. This capacitance component becomes an undesired capacitance component for the input circuit even when the monitor output circuit is deactivated. When a signal is input to the input circuit, the parasitic capacitance component is charged and discharged. When the signal frequency input to the input circuit is high, the change speed or the change waveform of the input signal waveform becomes slow due to the influence of the charge / discharge operation, and there is a possibility of malfunction. Particularly, a semiconductor device such as an SDRAM operated in synchronization with a clock signal tends to operate at a higher speed, and even a memory is likely to cause such a malfunction.

An object of the present invention is to provide a semiconductor device capable of reducing the influence of a capacitance component on an external terminal having a large parasitic capacitance component when a signal is input.

Another object of the present invention is to reduce the influence of a capacitance component in a semiconductor device having a configuration in which a monitor output circuit having a non-negligible capacitance component at an output node is connected to an external terminal common to an input circuit. Is to do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a high resistance element (6) is inserted between the external terminal (2) and the output node of the monitor output circuit (5). Specifically, the semiconductor device includes an external terminal, an input buffer circuit connected to the external terminal, a high-resistance element having one end coupled to a connection point between the external terminal and the input buffer circuit, A monitor output circuit having a monitor output terminal coupled to an end thereof; a resistance value (R) of the high resistance element (6) and an output capacitance component (C) of the monitor output circuit (5);
2) is set to be about 10 times or more the signal period supplied to the input buffer circuit.

As described above, during the input operation of the input circuit, the charge / discharge operation relating to the parasitic capacitance component of the monitor output circuit becomes substantially invisible due to the action of the high resistance element. In other words, by setting the time constant of about 10 times or more, the charge / discharge operation relating to the parasitic capacitance component becomes an operation that can be substantially ignored. Therefore, it is possible to prevent a malfunction in the high-speed input operation of the input circuit.

An electrostatic discharge circuit (3) can be provided between the external terminal and the high resistance element. The monitor output circuit is a circuit that makes it possible to observe the operating voltage generated by the power supply circuit (7) from the external terminal, and is an output MOS transistor (52) that is made capable of outputting the operating voltage by a test control signal (52). 50). The monitor output circuit may be a circuit that enables the word line bootstrap voltage in the SDRAM to be monitored from outside.

The semiconductor device (22) and a second semiconductor device (24) for controlling access to the semiconductor device (22) are mounted on a mounting board (2).
The data processing system mounted on 6) can increase the operating frequency.

[0012]

FIG. 1 shows a part of a semiconductor device according to an example of the present invention. Although not particularly limited, the semiconductor device shown in FIG. 1 is formed on a single semiconductor substrate 1 such as single crystal silicon by a known MOS integrated circuit manufacturing technique. In the figure, 2 is a bonding pad, 3 is an ESD circuit, 4 is an input buffer circuit, 5 is a monitor output circuit, and 6 is a high resistance element.

The ESD (Electrostatic Discharge)
The circuit is a circuit that discharges static electricity such as surges,
Although not particularly limited, it can be configured as shown in FIG. 30 is a diode, 31 and 32 are bipolar transistors, and 33 is a MOS transistor.

Although the details of the input buffer circuit 4 are not particularly shown, the input buffer circuit 4 includes a circuit such as an inverter at the first stage of the input.
The input node of the input buffer circuit 4 has an input capacitance represented by C1.

As shown in FIG. 2, for example, the monitor output circuit 5 uses a series connection point of an output MOS transistor 50 and a diode-connected NOS transistor 51 as an output node. The gate of output MOS transistor 50 is coupled to the output terminal of CMOS inverter 53 receiving test mode signal 52. The drain of output MOS transistor 50 is connected to power supply circuit 7. Although not particularly limited, the power supply circuit 7 is a circuit that generates a word line drive voltage (word line bootstrap voltage) and the like in the SDRAM. When the test mode signal 52 is set to the low level to instruct the test mode, the MOS transistor 50 is turned on, and the monitor output circuit 5 outputs the word line drive voltage generated by the power supply circuit 7 to the bonding pad 2. I do. Outside the semiconductor device, the level of the word line drive voltage can be monitored via the bonding pad 2. The output node of the monitor output circuit 5
Diffusion capacitance components caused by the sources and drains of the S transistors 50, 51, and 54 are parasitic. This parasitic capacitance component is represented by C2. The parasitic capacitance component C2
Is, for example, about 0.1 pF to 1 pF. In this specification, an arrow is attached to the back gate of a p-channel MOS transistor to distinguish it from an n-channel MOS transistor.

The high resistance element 6 is inserted between the output node of the monitor output circuit 5 and the bonding pad 2.
The resistance value of the high resistance element 6 is R. The time constant (R × C2) between the high resistance element 6 and the parasitic capacitance component C2 is set to be about ten times or more the period of the signal input to the input buffer circuit 4. The resistance value R of the high resistance element 6 is determined so as to satisfy this.

During the input operation of the input buffer circuit 4, the charge / discharge operation relating to the parasitic capacitance component C2 of the monitor output circuit 5 becomes substantially invisible due to the action of the high resistance element 6.
In other words, the time constant of about 10 times or more is set on the output node side of the monitor output circuit 5 via the high resistance element 6, so that the charge / discharge operation relating to the parasitic capacitance component C2 is substantially ignored. It is an operation to get. Therefore, in the high-speed input operation of the input buffer circuit 4, it is possible to prevent the input signal waveform from becoming dull or disturbed so as not to be ignored.

FIG. 4 is a block diagram showing an example of the SDRAM to which the configuration shown in FIG. 1 is applied. For example, in FIG. 4, the address input terminal A0 is an external pin connected to the bonding pad 2 in FIG. In FIG. 4, the illustration of the ESD circuit 3 is omitted. The column address buffer 205 and the row address buffer 206 in FIG. 4 correspond to the input buffer circuit 4 in FIG. The address pin A0 is connected to the input nodes of the column address buffer 205 and the row address buffer 206, and is coupled to the output node of the monitor output circuit 5 via the high resistance element 6.

Although not particularly limited, the SDRAM 22 shown in FIG. 4 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. The SDRAM 22 has a memory bank A (BANK).
A) Memory Array 200A and Memory Bank B Constituting A)
(BANKB). Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the same column are connected to a word line (not shown) for each column. The data input / output terminals of the memory cells arranged on the same row are connected to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding a row address signal by the row decoder 201A. Complementary data lines (not shown) of memory array 200A are coupled to sense amplifier and column selection circuit 202A. The sense amplifier in the sense amplifier and column selection circuit 202A is an amplifier circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary common data line 204. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A. Similarly, the row decoder 201 is provided on the memory array 200B side.
B, a sense amplifier and column selection circuit 202B, and a column decoder 203B are provided. The complementary common data line 204 is connected to the output terminal of the data input buffer 210 and the input terminal of the data output buffer 211. The input terminal of the data input buffer 210 and the output terminal of the data output buffer 211 are 16-bit data input / output terminals I /
Connected to O0 to I / O15.

The row address signal and the column address signal supplied from the address input terminals A0 to A9 are taken into the column address buffer 205 and the row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207. The column address counter 207 outputs a column address signal as the preset data or the column address thereof according to an operation mode specified by a command described later. The value obtained by sequentially incrementing the signal is output to the column decoders 203A and 203B.

The controller 212 includes, but is not limited to, a clock signal CLK and a clock enable signal CK.
E, external control such as a chip select signal CSb (a suffix b means that a signal attached thereto is a row enable signal), a column address strobe signal CASb, a row address strobe signal RASb, and a write enable signal WEb. Signals and control data from the address input terminals A0 to A9 are supplied.
It forms an internal timing signal for controlling the operation mode of M and the operation of the circuit block, and includes a control logic (not shown) and a mode register 220 therefor.

The clock signal CLK is a master clock of the SDRAM, and other external input signals are made significant in synchronization with the rising edge of the clock signal CLK.

The chip select signal CSb indicates the start of a command input cycle by its low level. When the chip select signal is at a high level (chip unselected state), other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state.

Each of the signals RASb, CASb, and WEb has a function different from that of a corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for instructing the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid.

Although not shown, the controller 30 also supplies an external control signal for controlling output enable to the data output buffer 211 in the read mode.
When the signal is at a high level, for example, the data output buffer 211 is set to a high output impedance state.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK.

The input from A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at a low level, the memory bank BANKA is selected, and when the input of A9 is at a high level, the memory bank BANKB is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the data input buffer 210 and the data of only the selected memory bank are selected. This can be performed by processing such as connection to the output buffer 211.

The input of A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that the target of the precharge is both memory banks, and its low level. The level indicates that one of the memory banks indicated by A9 is to be precharged.

The column address signal is A0 in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK.
ＡA7. The column address defined in this way is used as a start address for burst access.

Next, the SDRA specified by the command
The main operation modes of M will be described.

[1] Mode register set command (M
o) A command for setting the mode register 220. The command is specified by CSb, RASb, CASb, and WEb = low level, and data to be set (register set data) is provided via A0 to A9. Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, burst lengths that can be set are 1, 2, 4, 8, and full page (25
6), and the configurable CAS latency is 1, 2, 2,
3, and the settable write modes are burst write and single write.

The CAS latency specifies how many cycles of the clock signal CLK are required from the fall of CASb to the output operation of the data output buffer 211 in a read operation specified by a column address read command described later. It is. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the clock signal CLK. In other words, when using a clock signal CLK with a high frequency, the CAS latency is set to a relatively large value, and when using a clock signal CLK with a low frequency, the CAS latency is set to a relatively small value.

[2] Row address strobe / bank active command (Ac) This is a command for validating a row address strobe instruction and selecting a memory bank by A9.
b, RASb = low level and CASb, WEb = high level. At this time, the address supplied to A0 to A8 is taken as a row address signal, and the signal supplied to A9 is taken as a memory bank selection signal.
The fetch operation is performed in synchronization with the rising edge of the clock signal CLK as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines.

[3] Column Address Read Command (Re) This command is a command necessary for starting the burst read operation and a command for giving an instruction of a column address strobe. CSb, CASb,
= Low level, RASb, WEb = high level. At this time, addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address. In the burst read operation designated thereby, the memory bank and the word line in the memory bank are selected in the row address strobe / bank active command cycle, and the memory cell of the selected word line is supplied with the clock signal CLK. Are sequentially selected in accordance with the address signal output from the column address counter 207 and are successively read out. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the clock signal CLK defined by the CAS latency.

[4] Column Address Write Command (Wr) When a burst write is set in the mode register 220 as a mode of the write operation, it is a command necessary to start the burst write operation, As a mode, when single write is set in the mode register 220, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is
CSb, CASb, WEb, = low level, RASb =
Instructed by the high level, the address supplied to A0 to A7 at this time is taken in as a column address signal. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

[5] Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A8 and A9,
b, RASb, WEb, = low level, CASb = high level.

[6] Auto-refresh command This command is a command required to start auto-refresh, and includes CSb, RASb, and CAS.
Instructed by b = low level, WEb, CKE = high level.

[7] Burst stop in full page command This command is necessary to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is performed when CASb, WEb = low level, RASb, CA
Instructed by Sb = high level.

[8] No operation command (No
p) This is a command instructing that no substantial operation is performed. CSb = low level, RASb, CASb, W
Indicated by Eb = high level.

In the SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Alternatively, data of one word line in a memory block selected by a row address strobe / bank active command cycle may be latched by a latch circuit (not shown) for readout before a column-related operation. I have. Therefore,
Unless data collision occurs at the data input / output terminals I / O0 to I / O15, during execution of a command whose processing has not been completed, precharge to a memory bank different from the memory bank to be processed by the command being executed The internal operation can be started in advance by issuing a command, a row address strobe / bank active command.

Further, the SDRAM 22 outputs the clock signal C
Since data, addresses, and control signals can be input and output in synchronization with LK, a large-capacity memory similar to a DRAM can operate at a high speed comparable to that of an SRAM. By specifying the number of data to be accessed by the burst length, it is understood that a plurality of data can be read or written continuously by sequentially switching the selection state of the column system by the built-in column address counter 207. .

The SDRAM operates in synchronization with the clock signal. This is to make it available for a high-speed data processing system. At this time, as described above, the input buffer 4
During the input operation, the charge / discharge operation relating to the parasitic capacitance component C2 of the monitor output circuit 5 becomes substantially invisible due to the action of the high resistance element 6. In other words, the time constant of about 10 times or more is set on the output node side of the monitor output circuit 5 via the high resistance element 6, so that the charge / discharge operation relating to the parasitic capacitance component C2 is substantially ignored. It is an operation to get. Therefore, in the high-speed input operation of the input buffer circuit 4, it is possible to prevent the input signal waveform from becoming dull or disturbed so as not to be ignored. In other words,
High-speed operation of the SDRAM can be guaranteed.

FIG. 5 shows an example of a data processing system using the SDRAM 22. A required wiring pattern is formed on the mounting board 26. A microprocessor 24, an SDRAM 22, and other input / output circuits 23 connected via a bus 27 constituted by this wiring pattern are mounted. Reference numeral 25 denotes an external interface terminal for interfacing the bus 27 with the outside. The microprocessor 24 is a semiconductor integrated circuit. By employing the SDRAM 22, the data processing system can realize a high data processing capability or a high data processing speed without requiring a special reduction in the access speed of the SDRAM 22.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the input buffer circuit is not limited to the address buffer, but may be a data input buffer, a control signal input buffer, or the like. Further, the specific circuit configuration of the monitor output circuit is not limited to FIG. 2 and can be appropriately changed. Further, the function of the monitor output circuit is not limited to the dual output of the word line drive voltage, and any monitor function may be used.

In the above description, the invention made mainly by the present inventor has been described by using the SDR which
Although the description has been given of the case where the present invention is applied to AM, the present invention is not limited thereto, and can be widely applied to various semiconductor devices such as other memories, semiconductor devices for data processing such as a microprocessor or a microcomputer. it can.

The present invention can be applied to a semiconductor device under the condition that a monitor output circuit having at least a non-negligible capacitance component at an output node is connected to an external terminal common to an input circuit.

[0050]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the time constant related to the parasitic capacitance component of the monitor output circuit is set to be about 10 times or more the input signal period of the input circuit by the action of the high resistance element, and the In the input operation, the charge / discharge operation relating to the parasitic capacitance component is an operation that can be substantially ignored. As a result, in the high-speed input operation of the input circuit, it is possible to prevent the input signal waveform from becoming dull or disturbed so as not to be ignored. Therefore, malfunction in the high-speed input operation of the input circuit can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a main part of a semiconductor device according to an example of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a monitor output circuit.

FIG. 3 is a circuit diagram illustrating an example of an ESD circuit.

FIG. 4 is a block diagram showing an example of an SDRAM to which the configuration of FIG. 1 is applied;

FIG. 5 is a block diagram showing an example of a data processing system using the SDRAM of FIG.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 bonding pad 3 ESD circuit 4 input buffer C1 input capacitance of input buffer 5 monitor output circuit C2 parasitic capacitance component of output node in monitor output circuit 6 high resistance element 7 power supply circuit 22 SDRAM 24 microprocessor 26 mounting substrate 50 output MOS transistor

Claims (5)

[Claims] An external terminal, an input buffer circuit connected to the external terminal, a high resistance element having one end coupled to a connection point between the external terminal and the input buffer circuit, and a high resistance element connected to the other end of the high resistance element. A monitor output circuit having a monitor output terminal coupled thereto, wherein a time constant between a resistance value of the high resistance element and an output capacitance component of the monitor output circuit is about 10 times or more of a signal period supplied to the input buffer circuit. A semiconductor device, characterized in that: 2. The semiconductor device according to claim 1, wherein an electrostatic discharge circuit is provided between said external terminal and said high resistance element. 3. The monitor output circuit is a circuit that enables an operation voltage generated by a power supply circuit to be observed from the external terminal, and has an output MOS transistor that can output the operation voltage by a test control signal. 3. The semiconductor device according to claim 2, wherein: 4. The monitor output circuit is a synchronous DR.
4. A circuit for externally monitoring a word line bootstrap voltage in AM.
13. The semiconductor device according to claim 1. 5. A semiconductor device comprising: a first semiconductor device according to claim 1; and a second semiconductor device for controlling access to the first semiconductor device mounted on a mounting substrate. A data processing system, comprising: