JPH11249972A - Abnormality detection circuit for flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an abnormality detection circuit which can detect the abnormality of data stored in a flash memory even in the case a power source is interrupted during the write. SOLUTION: A sequencer 13 detects commands successively given to a flash memory 3 during write and stores corresponding codes in a storage element 12. When a BUSY signal of the flash memory 3 reports the end of internal processing, the sequencer 13 stores a code indicating the normal end in the storage element 12. The storage element 12 is connected to a backup power source 14 and holds this code group in the period when a system power source 4 is interrupted. If a system 1 is stopped during write, only the code group given till then is stored in the storage element 12. Consequently, the system 1 can surely detect the data abnormality of the flash memory 3 in a short time based on the code group in the storage element 12 in the activation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory abnormality detection circuit suitably used in a system using a flash memory such as a personal computer.

[0002]

2. Description of the Related Art In recent years, software has become large-scale, and it is increasingly difficult to complete software without errors (bugs). On the other hand, for example, the speed at which the use environment of the system changes, such as a place where the system is used or a system operating in cooperation with the system, is increasing year by year.

[0003] Therefore, in order to store data to be retained even when the power is turned off, a flash memory is being used instead of a non-rewritable ROM. In the flash memory, for example, when a defect is found in a program or when it is desired to change initial data or setting data, data can be easily rewritten. Therefore, a system having a higher degree of freedom can be constructed as compared with the case where a normal ROM is used.

The flash memory is slower than a normal RAM, and is not suitable for storing frequently rewritten data such as data in a work area. Therefore,
For example, it is often used to store data such as programs, initial data, or setting data, whose rewriting frequency is extremely low and which needs to be retained even when the power is turned off.

When data is written in the flash memory, it is necessary to erase the stored data once and then write new data due to the structure of the memory cell. Further, in order to manufacture a flash memory at lower cost, it is necessary to erase data for each area (sector) including a plurality of memory cells. Therefore, in order to prevent careless writing and erasing, writing and erasing procedures are defined. JEDEC (Joint Electron Device) is a general flash (erase) procedure for flash memory.
In the case of the standard command of the e Engineering Council, writing and erasing are performed by repeating a procedure of writing predetermined data to a predetermined address four to six times. For example, the procedure for writing to a specific address in word units is performed by writing to a flash memory four times, as shown in S1 to S4 in FIG.

Here, in the conventional system, when it is determined whether or not there is an abnormality in the data stored in the flash memory, data to be written to the flash memory is made redundant by using, for example, a checksum. Along with
When the system is started, a checksum is calculated from the data stored in the flash memory, and it is determined whether or not the data is abnormal.

[0007]

However, when a data abnormality is detected using redundant data, when there are many data abnormalities, the calculation results may coincide with each other and the data abnormality cannot be detected. is there. If the range of data abnormality is wide, the stored checksum value itself may be destroyed. Also in this case, data abnormality cannot be detected.

Here, in the flash memory, since the reliability of the device is improved, if the writing is completed normally, in most cases, no abnormality occurs in the stored data.
However, if the power is turned off during data writing (erasing) due to, for example, a power failure or a user operation error, the data is surely destroyed. As described above, since data is erased in sector units, the range of data to be destroyed often extends in sector units.
Data in the entire flash memory may be destroyed. Therefore, there is a possibility that data abnormality cannot be detected by the above-described conventional method.

Further, checksum and CRC (Cyclic
When a data abnormality is detected using a code (Redundancy Check) or the like, it is not possible to determine whether or not a data abnormality has occurred unless all of the redundant data is calculated.
In recent years, since the storage capacity of the flash memory has been improved with the improvement in the degree of integration, the time required for determination has also increased. As a result, there is a problem that the system startup time is prolonged.

Here, as described above, the flash memory often stores data, such as programs, initial data, and setting data, which are essential for the normal operation of the system. Therefore, if data abnormality is not detected, the damage is large, and it is strongly required to detect data abnormality in a short time and reliably.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a flash memory abnormality detection circuit capable of reliably detecting an abnormality in data stored in the flash memory. It is in.

[0012]

According to a first aspect of the present invention, there is provided a flash memory abnormality detection circuit for monitoring a writing procedure when writing data to a flash memory. It is characterized by comprising a procedure storage means for storing the write procedure and for storing the stored write procedure even when power is not supplied to the flash memory.

In the above configuration, when data is written to the flash memory, the procedure storage means stores a write procedure. Here, if the power of the flash memory is turned off while data is being written to the flash memory, the data stored in the flash memory is destroyed. On the other hand, the procedure storage means keeps storing the write procedure stored up to that time by, for example, a backup power supply. Therefore, by referring to the writing procedure, it is possible to determine whether or not the previous power shutdown occurred during the data writing. As a result, it is possible to reliably detect data destruction of the flash memory due to power interruption during writing, and to improve the reliability of a system using the flash memory.

Further, the storage capacity required for storing the above-mentioned writing procedure is extremely smaller than the storage capacity of the flash memory. Therefore, the data abnormality can be detected in a shorter time as compared with the case where the data sum is calculated from the data stored in the flash memory to detect the data abnormality.

The writing procedure may be a procedure for changing the data stored in the flash memory, for example, a procedure for specifying and writing data, or a predetermined procedure such as resetting to zero. May be the procedure for writing the data.

According to a second aspect of the present invention, in the flash memory abnormality detecting circuit according to the first aspect of the present invention, the abnormality detecting circuit further supports each write command sequentially input to the flash memory when data is written. , Code generation means for generating a code having a smaller bit width, wherein the procedure storage means sequentially stores the codes.

According to the above configuration, the code group corresponding to each command is stored instead of the write command group, so that the required storage capacity is reduced as compared with the case where the write command is stored in the procedure storage means as it is. it can. Therefore, the time required to detect a data abnormality can be further reduced, and the energy required for maintaining the writing procedure can be reduced.

In addition, even when only a storage element having a narrow data bus width, such as an 8-bit data width, can be used, a code can be stored by one writing. The number of elements can be reduced. As a result, the energy required for maintaining the writing procedure can be further reduced, and the manufacturing cost can be reduced.

According to a third aspect of the present invention, in the flash memory abnormality detecting circuit according to the first aspect of the present invention, the procedure storing means may store the flash memory in a state that the flash memory can take at the time of data writing as a writing procedure. Of these, while storing the current state of the flash memory,
The flash memory abnormality detection circuit further includes a state stored in the procedure storage unit and a write command newly input to the flash memory.
It is characterized by comprising state transition means for updating the state stored in the procedure storage means.

In the above configuration, since the procedure storage means stores the current state of the flash memory, the required storage capacity can be reduced as compared with the case where each write command is stored sequentially. Therefore, the time required to detect a data abnormality can be further reduced, and the energy required for maintaining the writing procedure can be reduced.

The arithmetic processing unit may run out of control due to various factors, such as when there is a mistake (bug) in the program or when the input / output processing is combined at a specific timing. . In particular, in a system such as a personal computer that performs non-standardized processing, it is difficult to verify whether or not all processing operates normally, and it is more likely that a runaway will occur than in a system that performs only standardized processing.

Normally, during runaway, a return process such as turning off the power and turning on the power again is performed. However, at the time of runaway, the arithmetic processing unit performs an unexpected operation, so that there is a possibility that data in the flash memory is accidentally destroyed by repeatedly accessing the flash memory.
Therefore, during runaway, if the recovery process is not performed as early as possible, the data in the flash memory will be destroyed,
It may not be possible to return to normal operation.

According to a fourth aspect of the present invention, in the flash memory abnormality detecting circuit according to the third aspect of the present invention, the write command newly input to the flash memory includes the procedure storing means. If the flash memory cannot be accepted in the state stored in the flash memory, it is determined that the flash memory has been accessed by an illegal procedure, and an unauthorized procedure notifying means for notifying an arithmetic processing unit that accesses data of the flash memory is provided. Features.

In the above configuration, when the flash memory is accessed by an unauthorized procedure, the unauthorized procedure notifying unit notifies the arithmetic processing unit. Therefore, the arithmetic processing device can recognize that it is out of control, and can take appropriate measures such as, for example, restarting. As a result, even if the arithmetic processing unit runs away, the data in the flash memory can be reliably protected, and the reliability of the system using the flash memory can be further improved.

Further, in the above configuration, runaway of the arithmetic processing unit is detected by illegal access to the flash memory. Therefore, an abnormality detection circuit for the flash memory and a circuit for monitoring runaway of the arithmetic processing unit are provided separately. As compared with the case, the configuration of the circuit can be simplified.

The member for detecting an abnormality may be, for example, an arithmetic processing unit. In this case, the arithmetic processing device is used both for processing data in the flash memory and for detecting data abnormality, so that the configuration of the entire system including the arithmetic processing device can be simplified. However, when the arithmetic processing unit detects an abnormality by a program stored in the flash memory, a range in which data is destroyed is wide, and if the program is also destroyed, there is a possibility that an abnormality in the data cannot be detected. .

According to a fifth aspect of the present invention, there is provided a flash memory abnormality detecting circuit according to the first, second, third, or fourth aspect of the present invention, wherein the arithmetic processing unit accesses data of the flash memory. When the device is activated, the device includes an abnormality notifying unit that determines whether or not an abnormality has occurred during writing to the flash memory with reference to the writing procedure stored in the procedure storing unit and notifies the arithmetic processing unit. It is characterized by having.

In the above configuration, since the abnormality is detected by the abnormality notification means provided separately from the arithmetic processing unit, regardless of the range in which the data in the flash memory is destroyed,
The data abnormality can be reliably detected, and the reliability of the system using the flash memory can be further improved.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] An embodiment of the present invention will be described below with reference to FIGS. That is, the abnormality detection circuit of the flash memory according to the present invention is a circuit for detecting an abnormality of data stored in the flash memory, and can be widely applied to a system using the flash memory such as a personal computer.

For example, as shown in FIG. 1, a system 1 according to this embodiment includes a computer system having a CPU (arithmetic processing unit) 2, a flash memory 3, and a system power supply 4 for supplying power to the entire system 1. It is. The CPU 2 and the flash memory 3 are connected to an address bus A
The CPU 2 is connected to each other via cpu, a data bus Dcpu, and a control bus Ccpu. When reading data stored in the flash memory 3, the CPU 2 specifies an address at which the data is stored via an address bus Acpu. At the same time, the control bus Ccpu instructs the flash memory 3 to read. On the other hand, the flash memory 3 outputs the data stored at the given address to the data bus Dcpu. Thereby, the CPU 2
Can read data from a desired address of the flash memory 3.

In the flash memory 3, when writing data, it is necessary to erase the data stored in the memory cell once and then write the desired data due to the structural limitation of the memory cell. It is used to store data such as data and setting data, which is rewritten less frequently than work data. Therefore, a write / erase command of a predetermined procedure is prepared so that data written in the memory cell is not inadvertently changed. In order to simplify the memory cell, erasing of the memory cell is performed by a plurality of memory cells (sectors).
This is done every time. In the flash memory 3 according to the present embodiment, for example, as shown in Tables 1 and 2 below, data can be written or erased using JEDEC standard commands.

[0032]

[Table 1]

[0033]

[Table 2]

In Tables 1 and 2, RA
And RD indicate a read address and read data, and PA and PD indicate a write address and write data. SA is an erase address composed of a combination of address bits A17 to A12, and can specify individual sectors. Further, in addition to the above Tables 1 and 2, by applying "B0H" to the data bus of the flash memory 3, a sector erase suspend command is designated, and after the sector erase suspend command is issued, "30H" is issued. ”Can restart the sector erase.

Therefore, for example, a certain address a1
When writing the data d1 in word units, as shown in FIG. 2, in the first to third write cycles,
The CPU 2 stores a command (address / data) indicating a program in units of words in the flash memory 3 as “command (address / data)”.
5555H / AAH "," 2AAAH / 55H ", and" 5555H / A0H "are sequentially given (at times t1 to t3), and the desired address a1 and data d1 are written to the flash memory 3 in the fourth write cycle. Then, the data d1 is written to the address a1 (at time t4), and the flash memory 3 performs the writing and erasing processes inside the flash memory 3 even after the fourth write cycle is completed. The flash memory 3 according to the present embodiment is configured to output a BUSY signal of a predetermined level, for example, a low level during the execution of the internal processing. Can be notified to the outside.

Further, the system 1 according to the present embodiment
As shown in FIG. 1, there is provided an abnormality detection circuit 11 for monitoring a writing procedure to the flash memory 3 and detecting occurrence of an abnormality. The abnormality detection circuit 11 includes a storage element (procedure storage means) 12 for sequentially storing codes indicating commands to the flash memory 3 and the address bus Acp.
u, the data bus Dcpu, and the control bus Ccpu, to detect a command to the flash memory 3 and to encode the detected command,
Sequencer (monitoring means) 13 for writing data to a backup power supply 14 provided independently of the system power supply 4
Are provided. Further, the sequencer 13
When the BUSY signal from the flash memory 3 indicates that the internal processing is being performed after the BUSY signal indicates that the internal processing is being performed, a code (end code) indicating a normal end can be written to the storage element 12. The backup power supply 14 supplies power to both the sequencer 13 and the storage element 12 so that the sequencer 13 and the storage element 12 can operate normally while the code is being written, even when the system power supply 4 is shut off. While the power supply 4 is shut off, power can be continuously supplied to the storage element 12 so that the storage element 12 can hold the written code.

In the above configuration, the storage element 12 stores commands sequentially applied to the flash memory 3 as codes. Therefore, in the normal case, that is, when the system 1 is stopped after the data writing to the flash memory 3 ends normally, a code group indicating the immediately preceding writing procedure and an end code are stored in the storage element 12. Is stored.

However, when the system 1 is stopped while data is being written to the flash memory 3, for example, when a power failure occurs during operation and the system power supply 4 is cut off, the storage element 12 Stores only the code group indicating the writing procedure instructed until the system 1 stops, and does not store the code group indicating the remaining writing procedure or the end code. In this case, the flash memory 3
Has received some or all of the command,
Data in sector units is destroyed by erasing or partial writing. Therefore, for example, when the system 1 is started, the CPU 2 reads the code group stored in the storage element 12 and determines whether or not the end code is stored. Data corruption can be reliably detected.

When an abnormality is detected, the CPU 2 rewrites the data in the flash memory 3 to correct data by, for example, the following recovery processing. That is, C
The PU 2 displays that the data in the flash memory 3 is abnormal, or notifies the external device connected via the network. Further, the CPU 2 accesses a network server in which correct data is stored via a network, and downloads the data. Furthermore, the downloaded data is stored in the flash memory 3
After that, the CPU 2 restarts the system 1. The address of the network server storing the correct data and the program for connecting to the network server are stored in, for example, a ROM or another flash memory (neither is shown).
The PU 2 can access the network even if an abnormality occurs in the flash memory 3 shown in FIG.

As described above, the write procedure is a command of at most six times. Therefore, even when the command itself is stored in the storage element 12, the storage capacity required for storing the write procedure is small, and data destruction is not performed. The time required for detection is extremely short. In particular, in the present embodiment, the commands are coded and stored, so that the storage capacity can be further reduced. On the other hand, when the writing is normally completed, the flash memory 3 can reliably hold the stored data. As a result, for example, a data abnormality such as a checksum can be detected in a shorter time and more reliably than the conventional technique of detecting a data abnormality by using data written in the flash memory 3.

The storage element 12 can store a code output from the sequencer 13 for each write cycle of the flash memory 3 and can hold data while the system power supply 4 is shut off. Even if an element is used, the same effect as in the present embodiment can be obtained. If the writing speed to the storage element is low, a wait is inserted into the flash memory 3 to lengthen each write cycle.
The above conditions can be satisfied. However, in this case, the writing time to the flash memory 3 becomes longer, and therefore, it is preferable that the storage element be an element having a writing speed that satisfies the above-mentioned condition even when no weight is inserted.

Further, among the storage elements satisfying the above conditions, it is desirable that the cost for holding data is as low as possible and the energy for holding data is small. In the following, as a suitable storage element satisfying these conditions, the backed-up S
The case where a RAM is used will be described in detail with reference to FIG.

That is, in the abnormality detection circuit 21 according to the configuration example, the SRAM 22 serving as the procedure storage means is backed up by the battery 24 serving as a backup power supply. On the other hand, the sequencer 23 includes a code generation unit (code generation unit) 25 that generates a code corresponding to the command.
And an SRAM control unit 26 for controlling an address and the like when the code is written to the SRAM 22.

The SRAM control unit 26 increases the value of the address signal Aseq to be supplied to the SRAM 22 by one each time a code is supplied from the code generation unit 25. Also,
When the end code is written at the end of a series of writing procedures, for example, the first address of the SRAM 22
The value of the address signal Aseq is initialized to a predetermined value. Further, as shown in FIG. 2, when the value of the address signal Aseq and the value of the data signal Dseq generated by the code generation unit 25 are stabilized, the SRAM control unit 26 sends the code recording signal (FIG. (Write control signal shown in FIG. 3), and instructs the timing of writing the code.

The command of the flash memory 3 according to the present embodiment is represented by a combination of data of nine values and addresses of two values, as shown in Tables 1 and 2 described above. Therefore, as an example of decoding, the code generation unit 25 according to the present embodiment converts the data of the command into D0 to D3 as shown in Tables 3 and 4 below.
And the address is coded into two bits D4 and D5. Tables 3 and 4 below
In Table 1 and Table 2, "Other" indicates a case where the address or data has a value other than the command, such as a case where a write address is given. Table 4 shows only write (erase) commands in word units.

[0046]

[Table 3]

[0047]

[Table 4]

Further, in the present embodiment, D0 to D5
In addition to these 6 bits, a flag D6 indicating whether or not the code is an end code and a flag D7 indicating whether or not each code is a code written in the previous writing procedure are provided. The flag D7 has the same value during a series of writing procedures, and inverts the value each time an end code is recorded. Therefore, even if the code indicating the procedure is overwritten, it is possible to distinguish between the previously written code and the currently written code, as described later. A code indicating a write procedure is created by these eight bits D0 to D7.

The code generator 25 monitors the data bus Dcpu, for example, as shown in FIG.
Based on the value of pu, bits D0-D of the values shown in Table 3 above
3 and an address encoder 25b that monitors the address bus Acpu and generates the bits D4 and D5 having the values shown in Table 4 above based on the value of the address bus Acpu in the write cycle to the flash memory 3. And a flag generation circuit 25 for generating flags D6 and D7 of the above values based on the BUSY signal
c, and a code composed of D0 to D7 can be given as a data signal Dseq to the SRAM 22 shown in FIG. The write cycle of the flash memory 3 can be identified by, for example, taking the logical product of the chip select signal CS # of the flash memory 3 and the write enable signal WE #. When a command indicating reset is issued, the encoders 25a and 25
b instructs the flag generation circuit 25c to generate an end code. In addition, in FIG. 4 and the like, ♯ attached to a reference sign indicates that the signal is negative logic.

By the way, in this embodiment, the CPU 2
The code group stored in the SRAM 22 is read when the system 1 is activated. However, when writing to the flash memory 3, the sequencer 23 supplies the address signal Aseq and the data signal Dseq to the SRAM 22, so that the address bus Acpu of the CPU 2 and the SRAM
22 address bus Asram or C
When the data bus Dcpu of the PU 2 is directly connected to the data bus Dsram of the SRAM 22, the address bus A
The signal of cpu collides with the address signal Aseq, and the signal of the data bus Dcpu collides with the data signal Dseq.

Therefore, in the abnormality detecting circuit 21 according to the present embodiment, in order to avoid a collision, the SRAM 22
Via an address selector 27, an address bus Acpu
And a data bus Dcpu via a data buffer 28 which is a tri-state buffer. The address selector 27 is, for example, when the SRAM read signal RRD calculated from the logical product of the signal obtained by decoding the address when the CPU 2 reads the code from the SRAM 22 and the read signal RD # indicates the reading from the SRAM 22. And the address bus Acpu to S
The voltage is applied to the RAM 22, otherwise, the address signal Aseq is selected as the address of the SRAM 22. Similarly, when the data buffer 28 indicates reading from the SRAM 22, the data buffer 28 outputs the data of the SRAM 22 to the data bus Dcpu, and otherwise keeps the data bus Dcpu in a high impedance state. Thus, the sequencer 23 can write a code at the time of writing to the flash memory 3 without being affected by a signal from the CPU 2. On the other hand, the CPU 2
In a normal read cycle, the code in the SRAM 22 can be read without being affected by the sequencer 23.

In the above configuration, as shown in FIG. 2, when a series of commands is given to the flash memory 3, the sequencer 23 writes a code as shown in FIG.
Are sequentially written (periods t1 to t5). After the writing to the flash memory 3 is normally output,
When a series of commands is given to the flash memory 3, the sequencer 23 writes a code corresponding to the new command group into the SRAM 22 (period t6 to t10).

However, the period from t1 to t5 and the period from t6 to t1
During the period of 0, the value of the flag D7 is different from each other. Therefore, for example, when the system 1 is stopped after the writing is normally completed, such as between the time t5 and the time t6, the code group stored in the SRAM 22 becomes as shown in FIG. ,
In the area from the first address to the address where the end code is stored, the code flag D7 matches.
Conversely, when the system 1 stops during writing, for example, at time t7, the code group of the SRAM 22 becomes as shown in FIG. 7, and the code group from the first address to the address where the end code is stored is shown. In the area, the value of the code flag D7 changes. Therefore, CPU2
Can read out the code group stored in the SRAM 22 to determine whether the system 1 has stopped during writing. As a result, a data abnormality in the flash memory 3 due to a system stop during writing can be reliably detected.

In addition, if the code group stored in the SRAM 22 is different from the normal procedure, the system 1 malfunctions and the data to be written to another location is erroneously stored in the flash memory 3 at the time of the previous system stop. You can see that I tried to write. Therefore, the data abnormality of the flash memory 3 due to the malfunction of the system 1 can be reliably detected.

Since the above code group has a maximum of 6 bytes, the data written in the flash memory 3 is checked and compared with the prior art in which data abnormality is detected.
The amount of data required for abnormality detection is small, and data abnormality can be detected at high speed. When writing, the flash memory 3
Judgment of the sector from which the data is to be erased from the command given to the device, and storing the sector in addition to the above code, identifies the sector that may be destroyed when an error occurs during writing. it can. In this case, CPU2
Can more accurately grasp the range of data abnormalities that have occurred in the flash memory 3, so that more accurate recovery processing, such as downloading only the contents of a specific sector, can be taken.

In the configuration example shown in FIG. 3, the commands are coded and stored.
2 may be stored as it is. However, in this case, since the bit width of the command is the sum of the number of address buses and the number of data buses of the flash memory 3, if an attempt is made to write a command at a time, the SRAM 22 has a data bus of the same bit width. Is required. As a result, an SRAM device having a normal data bus
When M22 is configured, the number of SRAM elements increases. On the other hand, when the above command is written in a time-division manner using a single SRAM element, the flash memory 3
It is necessary to write data to the SRAM element a plurality of times during one write cycle. Therefore, a high-speed SRAM device having a writing speed several times that of the flash memory 3 is required. In either case, the cost of the SRAM device and the energy required for backup increase.

On the other hand, in the present embodiment, since commands are coded and stored, the flash memory 3
Medium-speed SRA accessible once every write cycle
The SRAM 22 can be constituted by one M element. As a result,
The cost of the abnormality detection circuit 11 (21) and the energy required for backup can be reduced.

The storage element 12 shown in FIG.
The present invention is not limited to the above-described configuration, and has a small capacity
The AM may be created by an ASIC or the like. in this case,
The storage capacity is smaller than when a normal SRAM element is used, and the bit width of the SRAM can be set to a width that allows each command to be written at once. Therefore, even if the command (address / data) is stored as it is without coding, the energy required for backup can be suppressed.

[Second Embodiment] By the way, in the first embodiment, the case where the CPU 2 detects a data abnormality based on a code group stored in the abnormality detection circuit 11 (21) will be described as an example. However, the member that detects the abnormality is not limited to this. Further, the abnormality detection circuit 11 (21)
In this example, data obtained by decoding a given write instruction is sequentially stored, but the method of writing the write procedure is not limited to this. In the present embodiment, as another detection method, a case where the current state is stored among the states that the flash memory can take will be described as an example. Further, in the present embodiment, a case will be described as an example in which a member that monitors the state transition and notifies the CPU of the abnormality is provided separately from the CPU as a member for detecting the abnormality.

More specifically, as shown in FIG. 8, the system 1a according to the present embodiment comprises the abnormality detection circuit 11 shown in FIG.
And an abnormality detection circuit 31 that notifies the CPU 2 of the abnormality when the abnormality is detected. Members having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the system 1a according to the present embodiment, the commands that can be accepted by the flash memory 3 include a command R indicating a reset and commands C1 to C3 indicating a program.
The four states shown in FIG. 9 are set as states that the flash memory 3 can take. 1
One is an IDLE state in which the writing is completed normally and the next writing is awaited, and commands C1, C2 and C
3, the state of the flash memory 3 is changed to the IDL by receiving a command group indicating a program.
From state E to states State1, State2 and St
transition to ate3. In the state State3, when the flash memory 3 receives the write address and the write data, writes the data, and outputs a BUSY signal indicating the end of the write, the flash memory 3 transits from the state State3 to the IDLE state. In addition, each state State1 to State3
, When the reset command R is received, the flash memory 3 shifts to the IDLE state. As shown in Tables 1 and 2, the flash memory 3 itself can receive other commands such as a chip erase command, for example, but the abnormality detection circuit 31 according to the present embodiment Is detected as an invalid command.

More specifically, the abnormality detection circuit 31 identifies the commands C1 to C3 and R given to the flash memory 3 and generates a sequencer control signal SEQ according to the commands C1 to C3 and R. (Monitoring means) 32, if the sequencer control signal SEQ can be accepted in the state of the flash memory 3 held by itself, the state is changed to a new state, and if not accepted, an abnormality notification signal is sent to the CPU 2. And an operation monitoring sequencer (procedure storage means) 33 for outputting Also,
As in FIG. 1, a backup power supply 34 is provided in the abnormality detection circuit 31, and the state stored in the operation monitoring sequencer 33 can be maintained when the system power supply 4 is shut off.

As shown in FIG. 10, the decoder 32 has an address bus Acpu and a data bus Dcpu.
A read signal RD # indicating that the CPU 2 reads data, a write enable signal WE # indicating writing, and a chip select signal CS # indicating that the flash memory 3 is being accessed, of the control bus Ccpu.
When the commands C1 to C3 and R are given to the flash memory 3 based on these signals, the decoder 32 outputs the sequencer control signal S
The signals Sc1 to Sc3 and Sr corresponding to the respective EQs can be set to a high level.

On the other hand, the operation monitoring sequencer 33, as shown in FIG.
Signal and the sequencer control signal SEQ from the decoder 32
And the flash memory 3 stored in the
State transition unit (state transition means) 33a that transitions the state of
If the state stored in the state transition unit 33a at the time of activation of the system 1a is not the IDLE state, it is determined that the system 1a has been terminated while the flash memory 3 is being written, and the CPU 2 is notified of an abnormality. And an end detection unit (abnormality notification unit) 33b. Further, the operation monitoring sequencer 33 has a state determination unit 33c for determining the state stored in the state transition unit 33a, and the flash memory 3 has an illegal state based on the output of the state determination unit 33c and the output of the decoder 32. An unauthorized procedure detection unit (an unauthorized procedure notification unit) 33d that determines whether or not the access has been performed according to a simple procedure and notifies the CPU 2 of the access is provided.

For example, as shown in FIG. 12, the state transition unit 33a according to the present embodiment includes two JK flip-flops F1 backed up by the backup power supply 34 in order to store the current state of the flash memory 3.・ It has F2. Both JK flip-flops F1
F2 is cascaded with each other so as to make a circuit, and forms a Johnson counter. Also, both JK
The clear terminals CLR of the flip-flops F1 and F2
A signal Sr indicating a reset command R is applied from the decoder 32 shown in FIG. Further, the AND signal of the logic signal of the chip select signal CS # and the write enable signal WE # is calculated by the AND circuit L1 having a negative logic input, and the NOR circuit L2 outputs the output of the AND circuit L1. It is generated by calculating the NOT of the logical sum of the BUSY signal and the BUSY signal.

The J input of the JK flip-flop F1 is connected to an AND circuit L3, one of which has a negative logic input, the output Q2 of the JK flip-flop F2 is at a low level, and the signal Sc1 indicating the command C1. Is at a high level, a high-level signal is input. On the other hand, the J input of the JK flip-flop F2 is
It is connected to the ND circuit L4, and is set to the high level only when both the output Q1 of the JK flip-flop F1 and the signal Sc2 indicating the command C2 are at the high level. Similarly, by the positive logic AND circuit L5, a high-level signal is input to the K input of the JK flip-flop F1 only when both the signal Sc3 indicating the command C3 and the output Q2 are at a high level. Further, the AND circuit L6 having one negative logic input sets the K input of the JK flip-flop F2 to high level only when the BUSY signal is at high level and the output Q1 is at low level.

Therefore, both JK flip-flops F1
The Johnson counter constituted by F2 indicates that the correct write command C1 to the flash memory 3 in each state State1, State2 and IDLE state
The count is incremented only when .about.C3 is given and when the BUSY signal indicates normal end in state State3. The timing of counting up is the point in time when the clock signal is input. Thus, when data is written to the flash memory 3 in a correct procedure, the values held by the two JK flip-flops F1 and F2 change to values indicating the next state for each procedure.
When a reset command R is given to the flash memory 3, the values of both JK flip-flops F1 and F2 are reset to 0 so as to indicate the IDLE state.

On the other hand, as shown in FIG. 13, in the abnormal termination detecting section 33b, the OR circuit L11 includes the output Q1 of the JK flip-flop F1 and the JK flip-flop F
2 is calculated with the output F2. Further, the D flip-flop F11 holds the output of the OR circuit L11 at the rising timing of the signal RESET # and outputs it as an abnormal end detection signal. Note that the signal RESET # indicates reset of the system 1a, and rises at the time of activation of the system 1a. The D flop F11 is reset by a signal Sr indicating a reset command R. Accordingly, if the JK flip-flops F1 and F2 do not hold a value indicating the IDLE state at the time of activation of the system 1a, the abnormal end detection unit 33b outputs a high-level abnormal end detection signal and outputs the CPU 2 Can be notified of the occurrence of an error.

Further, as shown in FIG. 14, the state determination unit 33c includes the JK flip-flops F1 and F shown in FIG.
2 are decoded, and the state stored in both JK flip-flops F1 and F2 is determined. Specifically, the AND circuit L21 having a negative logic input has two outputs Q
When both 1 and Q2 are at the low level, the high-level signal S
Outputs i to notify that it is in the IDLE state. The AND circuit L22 having one negative logic input outputs the output Q1.
Is at a high level and the output Q2 is at a low level, a high-level signal Ss1 is output to notify that the state is State1. Similarly, when both outputs Q1 and Q2 are at the high level, the AND circuit L23 outputs the state State.
2 and outputs the high-level signal Ss2, and the AND circuit L24 having one negative logic input determines that the state is State3 when the output Q1 is at the low level and the output Q3 is at the high level. Then, the signal Ss3 is set to the high level.

As shown in FIG. 15, in the illegal procedure detecting section 33d, the 4-input NOR circuit L31 outputs a D flip-flop when any of the output signals Sc1 to Sc3 of the decoder 32 and the BUSY signal is at a high level. F3
1 clock input to a high level. Further, the four-input OR circuit L32 outputs the logical product of the negation of the signal Sc1 and the signal Si, the logical product of the negation of the signal Sc2 and the signal Ss1, the logical product of the negation of the signal Sc3 and the signal Ss2, and BUSY The logical sum of the negation of the signal and the logical product of the signal Ss3 is calculated and applied to the D input of the D flip-flop F31. A clear input R of the D flip-flop F31 has a signal Sr indicating a reset command R.
Is applied. Thus, when a command is input in a procedure that is not a regular procedure, the unauthorized procedure detection unit 33d
The D flip-flop F31 outputs a high-level illegal procedure detection signal to notify the CPU 2 of the occurrence of an abnormality.

According to the above configuration, in the abnormality detection circuit 31 shown in FIG.
The sequencer control signal SEQ corresponding to each command is supplied to the operation monitoring sequencer 33 by monitoring the write command given to the command. At the end of writing, BUSY is sent from the flash memory 3 to the operation monitoring sequencer 33.
A signal is input. On the other hand, in the operation monitoring sequencer 33, the state transition unit 33a shown in FIG. 11 determines the state of the flash memory 3 based on the current state of the flash memory 3 held by itself and the sequencer control signal SEQ and the BUSY signal. Is updated and stored.

As a result, when the flash memory 3 is written in the normal writing procedure, the state stored in the state transition section 33a is changed from the IDLE state to the states State1, State2 and State as shown in FIG.
3 sequentially, and transitions to the IDLE state when the writing to the flash memory 3 is completed. Therefore, when the system 1a ends normally, the state transition unit 33a stores the IDLE state, and this state is held until the next start time. At the next start-up, FIG.
The abnormal termination detection unit 33b shown in (1) refers to the storage contents of the state transition unit 33a to determine whether or not the system 1a has terminated during the writing to the flash memory 3. In this case, since the state transition unit 33a stores the IDLE state, the abnormal end detection unit 33b determines that the system 1a has ended after the writing of the flash memory 3 has ended (normal end), and Does not report an error.

On the contrary, if the system 1a is terminated (abnormal termination) while the flash memory 3 is being written,
The state transition unit 33a stores states other than the IDLE state. Therefore, at the time of the next startup, the abnormal end detection unit 33b determines from the storage contents of the state transition unit 33a that
It determines that the system 1a has terminated abnormally, and outputs an abnormal termination detection signal to the CPU 2. Thus, the CPU 2 performs the same return processing as in the first embodiment, and returns the system 1a to a normal state.

Further, based on the sequencer control signal SEQ and the BUSY signal and the contents stored in the state transition section 33a determined by the state determination section 33c, the unauthorized procedure detection section 33d determines that the procedure for writing to the flash memory 3 is illegal. Detects that there is, and immediately notifies the CPU 2 of an illegal procedure detection signal. As a result, the CPU 2 can immediately detect that the CPU 2 has gone out of control, and can perform the return process. As a result, it is possible to reliably prevent the data in the flash memory 3 from being destroyed by an unexpected operation of the CPU 2 at the time of runaway, and to protect the data in the flash memory 3.

In the first and second embodiments, the case where the abnormality detection circuits (11, 21 and 31) and the flash memory (3) are provided separately has been described. Not limited to this, both may be formed integrally. This makes it possible to reduce the number of parts constituting the system (1.1a). However, even if they are formed integrally, it is better that both power supply lines are provided separately so that the abnormality detection circuit can maintain the writing procedure during the period when power is not supplied to the flash memory. Good. If the abnormality detection circuit and the flash memory are formed separately, for example, even if a failure occurs in the flash memory such as application of a high voltage or a power failure, the abnormality detection circuit can operate the abnormality of the flash memory without any trouble. Can be detected.

Further, in each of the above embodiments, the case where it is determined whether or not the internal processing of the flash memory has been completed based on the BUSY signal has been described as an example. However, the present invention is not limited to this. For example, the determination may be made by software using a method (polling) of issuing a command for inquiring whether or not writing to the flash memory is possible at predetermined intervals. In this case, even a flash memory that does not output a BUSY signal can detect the end of processing of the flash memory.

Further, in each of the above embodiments, the case where the backup power supply (14, 24, 34) is a battery has been described as an example. However, for example, a large capacity capacitor such as an electric double layer capacitor may be used. Even if power is not supplied to the flash memory, the same effect as that of the present embodiment can be obtained as long as the write procedure stored in the procedure storage means (12, 22, 33) can be held.

[0078]

As described above, the abnormality detection circuit for a flash memory according to the first aspect of the present invention stores monitoring means for monitoring a writing procedure when writing data to the flash memory, and stores the writing procedure. And a procedure storage unit for retaining the stored writing procedure even while power is not supplied to the flash memory.

According to the above configuration, since the procedure storing means stores the procedure for writing to the flash memory, it is possible to reliably detect data destruction of the flash memory due to power interruption during writing. further,
Since the storage capacity required for storing the above write procedure is extremely small compared to the storage capacity of the flash memory,
In addition, the data abnormality can be detected in a short time.

According to a second aspect of the present invention, in the flash memory abnormality detecting circuit according to the first aspect of the present invention, each of the write commands sequentially input to the flash memory at the time of data writing is further provided. And a code generation means for generating a code corresponding to the above, and the procedure storage means is configured to sequentially store the codes.

According to the above configuration, the code group corresponding to each command is stored instead of the write command group, so that the storage capacity required for storing the write procedure can be reduced. Therefore, it is possible to further reduce the time required for detecting the data abnormality and to reduce the energy required for maintaining the writing procedure.

In the flash memory abnormality detecting circuit according to the third aspect of the present invention, as described above, in the configuration of the first aspect of the present invention, the procedure storage means stores the current state of the flash memory as a writing procedure. Along with remembering,
The abnormality detection circuit of the flash memory further includes state transition means for updating a state stored in the procedure storage means in response to a write command newly input to the flash memory.

In the above configuration, since the procedure storage unit stores the current state of the flash memory, the storage capacity required for storing the write procedure can be reduced. Therefore, it is possible to further reduce the time required for detecting the data abnormality and to reduce the energy required for maintaining the writing procedure.

Further, in the flash memory abnormality detecting circuit according to the fourth aspect of the present invention, as described above, in the configuration of the third aspect of the present invention, the write command newly input to the flash memory is the same as the above-described procedure. If the data cannot be accepted in the state stored in the storage means, the flash memory is determined to have been accessed in an unauthorized procedure, and an unauthorized procedure notifying means is provided for notifying an arithmetic processing unit accessing data in the flash memory. Configuration.

In the above configuration, the arithmetic processing unit runs away,
If an illegal access to the flash memory is to be repeated, the illegal procedure notifying unit can notify that the arithmetic processing unit is running out of control and instruct to take an appropriate action. As a result, even if the arithmetic processing unit runs away,
This has the effect of reliably protecting the data in the flash memory.

According to a fifth aspect of the present invention, there is provided a flash memory abnormality detecting circuit according to the first, second, third or fourth aspect of the present invention, wherein the procedure storage means is provided when the arithmetic processing unit is started. And an abnormality notifying unit that determines whether or not an abnormality has occurred during the writing of the flash memory with reference to the writing procedure stored in the flash memory and notifies the arithmetic processing unit of the abnormality.

In the above configuration, since the abnormality is detected by the abnormality notification means provided separately from the arithmetic processing unit, regardless of the range in which the data in the flash memory is destroyed,
This has the effect of reliably detecting data abnormalities.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main configuration of a system including a flash memory and an abnormality detection circuit.

FIG. 2 is a timing chart showing an operation at the time of writing to a flash memory in the above system.

FIG. 3 is a block diagram illustrating a configuration example of the abnormality detection circuit.

FIG. 4 is a block diagram illustrating a configuration example of a code generation unit in the abnormality detection circuit.

FIG. 5 is a diagram illustrating an operation at the time of writing to a flash memory in the above system, and is an explanatory diagram illustrating codes stored in an abnormality detection circuit.

FIG. 6 is an explanatory diagram showing a code group stored in an abnormality detection circuit when writing is normally completed in the system.

FIG. 7 is an explanatory diagram showing a group of codes stored in an abnormality detection circuit when the system stops during writing in the system.

FIG. 8 illustrates another embodiment of the present invention, and is a block diagram illustrating a main configuration of a system including a flash memory and an abnormality detection circuit.

FIG. 9 is an explanatory diagram showing a state transition of a flash memory in the above system.

FIG. 10 is a block diagram showing inputs and outputs of a decoder in the abnormality detection circuit.

FIG. 11 is a block diagram showing a main configuration of an operation monitoring sequencer in the abnormality detection circuit.

FIG. 12 is a circuit diagram showing a configuration example of a state transition unit in the operation monitoring sequencer.

FIG. 13 is a circuit diagram showing a configuration example of an abnormal end detection unit in the operation monitoring sequencer.

FIG. 14 is a circuit diagram showing a configuration example of a state determination unit in the operation monitoring sequencer.

FIG. 15 is a circuit diagram showing a configuration example of an unauthorized procedure detection unit in the operation monitoring sequencer.

FIG. 16 is a flowchart illustrating an example of a procedure for writing data to a flash memory.

[Explanation of symbols]

 2 CPU (arithmetic processing unit) 3 flash memory 12 storage element (procedure storage unit) 13 sequencer (monitoring unit) 22 SRAM (procedure storage unit) 25 code generation unit (code generation unit) 32 decoder (monitoring unit) 33 operation monitoring sequencer (Procedure storage unit) 33a State transition unit (state transition unit) 33b Abnormal termination detection unit (abnormal notification unit) 33d Illegal procedure detection unit (illegal procedure notification unit)

Claims (5)

[Claims] 1. A monitoring means for monitoring a writing procedure when writing data to a flash memory, and storing the writing procedure and storing the stored writing procedure even when power is not supplied to the flash memory. A flash memory abnormality detection circuit, comprising: 2. The apparatus according to claim 1, further comprising: code generation means for generating a code having a smaller bit width in response to each write command sequentially input to said flash memory at the time of data writing, wherein said procedure storage means stores said code. 2. The abnormality detection circuit for a flash memory according to claim 1, wherein the abnormality is sequentially stored. 3. The procedure storage means stores, as a write procedure, a current state of the flash memory among states that can be taken by the flash memory at the time of data writing, and an abnormality detection circuit of the flash memory further comprises: Based on the state stored in the procedure storage unit and a write command newly input to the flash memory,
2. The flash memory abnormality detection circuit according to claim 1, further comprising a state transition means for updating a state stored in said procedure storage means. 4. If the write command newly input to the flash memory cannot be accepted in a state stored in the procedure storage means, it is determined that the flash memory has been accessed in an illegal procedure, and the flash memory is accessed. 4. The flash memory abnormality detection circuit according to claim 3, further comprising an unauthorized procedure notification unit that notifies an arithmetic processing unit that accesses data in the memory. 5. When an arithmetic processing unit for accessing data in said flash memory is started, referring to a write procedure stored in said procedure storage means, it is determined whether or not an abnormality has occurred during writing to said flash memory. 5. The flash memory abnormality detection circuit according to claim 1, further comprising abnormality notification means for determining and notifying the arithmetic processing unit.