JPH11249618A - Display controller and control method for display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device capable of displaying a picture having a pixel ratio roughly equal to the pixel ratio of the horizontal direction and the vertical direction of a supplied picture on a display device. SOLUTION: An internal clock generating part 12 generates an internal clock signal from an inputted reference clock signal CK to supply it to a horizontal counter 14 and a dot clock generating part 15, which generates a dot clock signal DCK in which the internal clock signal is thinned every fixed interval according to a dot clock thinning clock DRES. A horizontal decoder 13 generates a horizontal control signal and a vertical control signal according to internal clock signals counted by the horizontal counter 14. An LCD(liquid crystal display) controller supplies the generated horizontal control signal and vertical control signal to an LCD driving part to display a picture on the LCD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display control method capable of displaying an image having a pixel ratio substantially equal to a horizontal and vertical pixel ratio of a supplied image on a display device.

[0002]

2. Description of the Related Art A conventional LCD (Liquid Crystal Display) controller for a monitor or the like uses a CCD (Cold Circuit Device) supplied from a CCD circuit block when displaying an image picked up by a CCD (Charge Coupled Device) image sensor on the LCD.
Divide the synchronization signal of the CD according to the display pixel of the LCD,
A control signal is generated and supplied to the LCD driver. Conventional L
The manner in which an image is displayed on the LCD in the CD controller and its peripheral circuits will be described below.

A CCD circuit block receives light from a subject by CCD image pickup devices arranged in a matrix of i columns × j rows (i and j are natural numbers of 1 or more), and outputs RGB signals, horizontal synchronization signals H, A vertical synchronization signal V and a reference clock signal CK are generated. The CCD circuit block supplies the generated RGB signals to the inverting amplifier, and supplies the horizontal synchronization signal H, the vertical synchronization signal V, and the reference clock signal CK to the LCD controller. The inverting amplifier inputs RGB signals from the CCD circuit block, and changes the polarity of the RGB signals to the LCD.
And generates an RGB inversion signal obtained by inverting the common voltage (V _COM ) of the liquid crystal display element as a center, and supplies the inverted signal to the signal side driver.

The LCD controller receives a horizontal synchronizing signal H, a vertical synchronizing signal V and a reference clock signal CK from a CCD circuit block, and generates a horizontal control signal, a vertical control signal, and a frame pulse signal FRP. The LCD controller supplies the generated horizontal control signal to the signal side driver, supplies the vertical control signal to the scan driver, and supplies the frame pulse signal FRP to the inverting amplifier and the amplifier. The amplifier receives the frame pulse signal F from the LCD controller.
Input RP, generate common voltage signal (V _COM ) and LC
D.

[0005] The scan driver drives a scan line GL of the LCD according to a vertical control signal supplied from the LCD controller. The signal side driver drives the LCD signal line DL according to the horizontal control signal supplied from the LCD controller. As a result, the LCD has x columns × y
An image is displayed on a liquid crystal display element arranged in a matrix of rows (x and y are natural numbers of 1 or more).

[0006]

However, such L
The CD controller outputs the horizontal synchronizing signal H and the reference clock signal CK to the x columns × y rows of the liquid crystal display device of the LCD on the x columns to display the image of the pixels of i columns × j rows supplied from the CCD circuit block. A horizontal control signal and a vertical control signal are generated by dividing the frequency so as to approximate a display image of × y rows. For example, the LCD controller controls the horizontal synchronization signal and the reference clock signal in order to display the image of 640 columns × 480 rows of pixels supplied from the CCD circuit block on the LCD having the 280 columns × 220 rows of liquid crystal display elements. CK
Is divided so as to approximate a display image of 280 columns × 220 rows to generate a horizontal control signal and a vertical control signal. That is, the LCD controller generates a vertical control signal for 240 rows by dividing the horizontal synchronizing signal H for 480 rows by １ ／, supplies the vertical control signal for 240 rows to the scan driver, and supplies a reference clock C for 640 columns.
K is frequency-divided by を to generate a horizontal control signal for 320 columns, which is supplied to the signal side driver. As a result, the LCD
An image composed of pixels of 80 columns × 220 rows is displayed.

The image composed of 280 columns × 220 rows of pixels displayed on the LCD is not directly proportional to the image composed of 640 columns × 480 rows of pixels generated by the CCD circuit block. That is, (640/280) / (48
0/220) ≒ 1.05, and the image displayed on the LCD is an image which is extended (flattened) in the horizontal direction by about 5% compared to the image generated by the CCD circuit block. Therefore, when the pixel ratio of the liquid crystal display element of the LCD is not equal to the horizontal and vertical pixel ratio of the image supplied from the CCD circuit block, the LCD controller
A flat image was displayed on the LCD.

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and has a display control device and a display device capable of displaying an image having a pixel ratio substantially equal to a pixel ratio in a horizontal direction and a vertical direction of a supplied image on a display device. It is an object to provide a control method.

[0009]

In order to achieve the above object, a display control apparatus according to a first aspect of the present invention has a pixel ratio of a: b (where a and b are 1 or more) in a horizontal direction and a vertical direction. A synchronizing signal input means for inputting a synchronizing signal of a (natural number) image; and a pixel ratio of c: d (c and d are natural numbers of 1 or more) in the horizontal and vertical directions from the synchronizing signal input by the synchronizing signal input means. Control signal generation means for generating a control signal for controlling a display device in a display area, and control signal output means for outputting a control signal generated by the control signal generation means,
The display control device comprising: the control signal generation means, the frequency of the synchronization signal input by the synchronization signal input means, to generate a control signal by thinning out the frequency-divided signal, the horizontal direction and the vertical direction An image having a pixel ratio closer to a: b than to c: d is displayed on a display device.

According to the present invention, the control signal generating means includes:
A control signal for controlling a display device in a display area in which the pixel ratio in the horizontal direction and the vertical direction is c: d (c and d are natural numbers of 1 or more) is generated from the synchronization signal input by the synchronization signal input means. At this time, the control signal generation means generates a control signal in which the pixel ratio of the image displayed on the display device in the horizontal and vertical directions is closer to a: b than to c: d. As a result, an image having a pixel ratio substantially equal to the horizontal and vertical pixel ratios of the supplied image can be displayed on the display device.

In order to achieve the above object, a display control apparatus according to a second aspect of the present invention comprises: i columns × j rows (i and j are 1
A synchronizing signal input means for inputting a synchronizing signal of a frame image composed of a matrix of pixels of the above (natural number), and k columns × h
Control signal generating means for generating a horizontal control signal and a vertical control signal for controlling a display device comprising matrix-shaped display pixels in rows (k and h are one or more natural numbers); and a horizontal control signal generated by the control signal generating means. A control signal output unit that outputs a signal and a vertical control signal, wherein the control signal generation unit has a pixel ratio of k: h in a horizontal direction and a vertical direction of an image displayed on the display device. And generating a horizontal control signal and a vertical control signal closer to i: j.

According to the present invention, the control signal generating means includes:
K columns × h from the synchronization signal input by the synchronization signal input means
A horizontal control signal and a vertical control signal for controlling a display device composed of matrix-shaped display pixels in rows (k and h are one or more natural numbers) are generated. The control signal generation means determines that the pixel ratio of the image displayed on the display device in the horizontal direction and the vertical direction is k: h
A horizontal control signal and a vertical control signal closer to i: j are generated. As a result, an image having a pixel ratio substantially equal to the horizontal and vertical pixel ratios of the supplied image can be displayed on the display device.

[0013] The control signal generation means may generate a horizontal control signal by thinning out the synchronization signal input by the synchronization signal input means.

The control signal generation means generates a horizontal control signal by thinning out the synchronization signal input by the synchronization signal input means. As a result, an image having a pixel ratio substantially equal to the horizontal and vertical pixel ratios of the supplied image can be displayed on the display device.

[0015] The control signal generation means may generate a horizontal control signal while changing the timing of thinning out the synchronization signal input by the synchronization signal input means for each frame.

The control signal generation means generates a horizontal control signal while changing the timing of thinning out the synchronization signal input by the synchronization signal input means for each frame. As a result,
An image having a pixel ratio substantially equal to the pixel ratio in the horizontal direction and the vertical direction of the supplied image can be displayed on the display device while compensating for a partial decrease in resolution.

The display device may be a liquid crystal display device.

The synchronizing signal input by the synchronizing signal input means includes, for example, a horizontal synchronizing signal, a vertical synchronizing signal, and a reference clock. k rows x h
A horizontal control signal, a vertical control signal, and a reference clock (a dot clock in the case of a liquid crystal display device) of a display device including display pixels arranged in a matrix of rows are generated.

In order to achieve the above object, a method for controlling a display device according to a third aspect of the present invention comprises the steps of: i columns × j rows (i,
a synchronization signal input step of inputting a synchronization signal including a horizontal synchronization signal, a vertical synchronization signal, and a reference clock of a frame image composed of a matrix of pixels (j is one or more natural numbers), and a synchronization signal input in the synchronization signal input step A control signal generating step of generating a horizontal control signal and a vertical control signal for controlling a display device comprising a matrix of liquid crystal display pixels of k columns × h rows (k and h are natural numbers equal to or more than 1); A control signal output step of outputting a horizontal control signal and a vertical control signal generated by the step, wherein the control signal generation step includes the step of: outputting the synchronization signal input by the synchronization signal input step. Divide the frequency, thin out the divided signal to generate the horizontal control signal and the vertical control signal, and calculate the pixel ratio between the horizontal direction and the vertical direction. k: than h i: Near composed image is displayed on the display device to j, it is characterized.

In the control signal generation step, the synchronizing signal inputted in the synchronizing signal input step is k columns × h rows (k, h
Generates a horizontal control signal and a vertical control signal for controlling a display device composed of a matrix of liquid crystal display pixels of one or more natural numbers. The control signal generation step generates a horizontal control signal and a vertical control signal in which the pixel ratio of the image displayed on the display device in the horizontal and vertical directions is closer to i: j than to k: h. As a result, an image having a pixel ratio substantially equal to the horizontal and vertical pixel ratios of the supplied image can be displayed on the display device.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display control device according to a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram illustrating an example of a display control device and peripheral circuits according to an embodiment of the present invention. These circuits include a CCD circuit block 1, an inverting amplifier 2, a scanning driver 3, an LCD 4, a signal-side driver 5, an amplifier 6, and an LCD controller 7.

The CCD circuit block 1 comprises a CCD image sensor and its peripheral circuits. CCD circuit block 1
Receives light from a subject by CCD image pickup devices arranged in a matrix of 640 columns × 480 rows, and receives RGB light.
A signal, a horizontal synchronizing signal H, a vertical synchronizing signal V, and a reference clock signal CK are generated. The CCD circuit block 1 supplies the generated RGB signals to the inverting amplifier 2, and outputs the horizontal synchronizing signal H, the vertical synchronizing signal V, and the reference clock signal CK to the LCD.
It is supplied to the controller 7.

The inverting amplifier 2 receives an RGB signal from the CCD circuit block 1, generates an RGB inverted signal in which the polarity of the RGB signal is inverted for each frame, and supplies it to the signal driver 5.

The scanning driver 3 includes an LCD controller 7
The scanning lines GL of the LCD 4 are sequentially selected in accordance with the vertical control signal supplied from, and a gate pulse is applied to the selected scanning lines GL. The vertical control signal includes a gate reset signal GRES and a gate pulse clock signal GP.
CK and a gate start signal GSRT. Details of each signal will be described later.

The LCD 4 is composed of a TFT type liquid crystal display element, and has pixel electrodes and TFTs (Thin Film Transistors) arranged in a matrix of 260 columns × 220 rows, and a common electrode opposed to the pixel electrodes via a liquid crystal. It has. Each pixel electrode is connected to a corresponding signal line DL via a current path of a corresponding TFT. In addition, TFT of each row
Are connected to a common scanning line GL. The LCD 4 controls the orientation of the liquid crystal to display an image by charging the capacitance (pixel capacitance C _LC ) formed of the pixel electrode, the common electrode, and the liquid crystal through the scanning line GL and the signal line DL. .

The signal driver 5 outputs an RGB inversion signal to the signal line DL of the LCD 4 in accordance with the horizontal control signal supplied from the LCD controller 7. Note that the horizontal control signal includes a dot clock signal DCK, a data line start signal SRT, an output enable signal OE, and the like. Details of each signal will be described later.

The amplifier 6 inverts the polarity of the common voltage signal (V _COM ) for each frame in accordance with the frame pulse signal FRP supplied from the LCD
4

As shown in FIG. 2, the LCD controller 7 includes an internal horizontal synchronizing signal generator 11, an internal clock generator 12, a horizontal decoder 13, a horizontal counter 14, a dot clock generator 15, Field discriminator 16, vertical decoder 17, vertical counter 18 and F
It comprises an RP (frame pulse) generator 19, a thinning decoder 20, and a thinning counter 21.

The internal horizontal synchronizing signal generation section 11 divides the horizontal synchronizing signal H input from the CCD circuit block 1 by １ ／, generates an internal horizontal synchronizing signal (line clock signal), and generates a horizontal counter 14 and a vertical counter. 18 and the FRP generator 19 respectively.

The internal clock generator 12 divides the frequency of the reference clock signal CK input from the CCD circuit block 1 by １ ／, generates an internal clock signal, and
It is supplied to the dot clock generator 15 and the thinning counter 21.

The horizontal decoder 13 receives the count number from the horizontal counter 14, generates a data line start signal SRT and an output enable signal OE according to the count number, and supplies them to the signal driver 5. Further, the horizontal decoder 13 generates a gate reset signal GRES and a gate pulse clock signal GPCK and supplies them to the scanning driver 3.

The data line start signal SRT is a signal for the signal side driver 5 to start sampling the RGB inversion signal supplied from the inversion amplifier 2. The output enable signal OE is obtained by converting the RGB inverted signal sampled by the signal-side driver 5 into one line (one horizontal scanning period).
This is a signal to be output to the signal line DL in parallel in units. The gate reset signal GRES is a signal for the scanning driver 3 to thin out a video signal during a horizontal scanning period. The gate pulse clock signal GPCK is a signal for the scan driver 3 to shift the gate start signal GSRT.

The horizontal counter 14 receives an internal clock signal from the internal clock generator 12, counts the number of clocks, and supplies it to the horizontal decoder 13. The horizontal counter 14 is reset when the internal horizontal synchronization signal is supplied from the internal horizontal synchronization signal generator 11.

The dot clock generator 15 includes an internal clock signal supplied from the internal clock generator 12, a thinning signal DRES supplied from the thinning decoder 20,
To generate the dot clock signal DCK and supply it to the signal side driver 5. Dot clock signal D for horizontal control signal
CK is a signal for the signal side driver 5 to sample each dot in one line (during one horizontal scanning period) from the RGB inversion signal supplied from the inversion amplifier 2.

The synchronization control / field determination unit 16
An internal vertical synchronization signal is generated from the vertical synchronization signal V supplied from the D circuit block 1 and the decode signal supplied from the vertical decoder 17. The synchronization control / field determination unit 16 outputs the generated internal vertical synchronization signal to the vertical counter 1
8 and the FRP generator 19.

The vertical decoder 17 receives the count number from the vertical counter 18, generates a gate start signal GSRT according to the count number, and supplies it to the scan driver 3. The vertical decoder 17 generates a decode signal and supplies it to the synchronization control / field determination unit 16. The gate start signal GSRT is a signal for the scan driver 3 to start applying a gate pulse to the scan line GL.

The vertical counter 18 receives an internal horizontal synchronizing signal (line clock signal) from the internal horizontal synchronizing signal generator 11.
, And counts the number of clocks to read the vertical decoder 17.
To supply. The vertical counter 18 is reset when an internal vertical synchronization signal is supplied from the synchronization control / field determination unit 16.

The FRP (frame pulse) generating section 19
According to the internal horizontal synchronizing signal supplied from the internal horizontal synchronizing signal generating unit 11 and the internal vertical synchronizing signal supplied from the synchronization control / field determination unit 16, a frame pulse signal FRP is generated to generate the inversion amplifier 2 and the amplifier 6. To supply.

The thinning-out decoder 20 has a thinning-out counter 2
The count number is input from 1 and a thinning signal DRES corresponding to the count number is generated and supplied to the dot clock generator 15.

The thinning counter 21 receives an internal clock signal from the internal clock generator 12, counts the number of clocks, and supplies the counted number to the thinning decoder 20. The thinning counter 21 is reset when a reset signal is supplied from the horizontal decoder 13.

Hereinafter, a control operation performed by the display control device according to this embodiment will be described. The CCD circuit block 1 converts the generated image into an RGB signal, a horizontal synchronization signal H,
Separated into a vertical synchronization signal V and a reference clock signal CK,
The GB signal is supplied to the inverting amplifier 2, and the horizontal synchronization signal H, the vertical synchronization signal V, and the reference clock signal CK are supplied to the LCD controller 7.

The inverting amplifier 2 operates in accordance with the frame pulse signal FRP supplied from the LCD controller
An inverted RGB signal is generated by inverting the polarity of the RGB signal input from the D circuit block 1 for each frame, and is supplied to the signal driver 5.

The LCD controller 7 receives the input horizontal synchronization signal H, vertical synchronization signal V, and reference clock signal CK.
To generate a horizontal control signal and a vertical control signal.

Hereinafter, the operation of generating the horizontal control signal and the vertical control signal performed by the LCD controller 7 will be described. First,
A dot clock signal DCK serving as a horizontal control signal, a data line start signal SRT, and an output enable signal OE
Will be described. The internal clock generator 12 of the LCD controller 7 receives the reference clock signal CK shown in FIG. The internal clock generator 12 sets the reference clock CK for 640 columns to L
In order to approximate a liquid crystal display element of 280 columns of CD4, the internal clock signal is generated by dividing the reference clock signal CK by に as shown in FIG. The internal clock generation unit 12 outputs the generated internal clock signal to the horizontal counter 1
4. Dot clock generator 15 and thinning counter 21
To supply.

The thinning counter 21 counts the falling edges of the input internal clock signal 21 by 21 as shown in FIG. The thinning decoder 20 generates the dot clock thinning signal DRES when the count value of the thinning counter 21 becomes 9 as shown in FIG. 3D (timing of T1) and supplies it to the dot clock generating unit 15. .

The dot clock generating section 15 is provided in FIG.
As shown in (1), a dot clock signal DCK is generated by dividing the internal clock signal by １ ／. When the dot clock thinning signal DRES is at a low level (timing of T1), the dot clock generator 15 outputs the dot clock signal DRES.
CK is maintained at a high or low level as it is (in FIG. 3E, it is maintained at a low level). Thereafter, when the dot clock thinning signal DRES becomes high level (timing of T2), the dot clock generation unit 15 restarts the generation of the dot clock signal DCK.

As a result, while the count number of the thinning counter 21 is 21, the dot clock signal DCK has 20 rising and falling timings, which is originally 21.

The internal horizontal synchronizing signal generating section 11
A horizontal synchronizing signal H shown in FIG. The internal horizontal synchronizing signal generation unit 11 divides the horizontal synchronizing signal H by よ う as shown in FIG. 4B in order to approximate the horizontal synchronizing signal H of 480 rows to the liquid crystal display element of 220 rows of the LCD 4. To generate an internal horizontal synchronizing signal.
The internal horizontal synchronizing signal generator 11 outputs the generated internal horizontal synchronizing signal to the horizontal counter 14, the vertical counter 18, and the FRP.
It is supplied to the generator 19.

The horizontal counter 14 is reset when the internal horizontal synchronizing signal shown in FIG. The horizontal decoder 13 sets the output enable signal OE to a low level when the horizontal counter 14 is reset as shown in FIG. 4E (timing of T3). After resetting, the horizontal counter 14 restarts counting internal clocks. The horizontal decoder 13 sets the data line start signal SRT to a high level when the count of the horizontal counter 14 reaches a predetermined value as shown in FIG. 4D (at timing T4).

The LCD controller 7 sequentially outputs the dot clock signal DCK of the horizontal control signal thus generated,
The data line start signal SRT and the output enable signal OE are supplied to the signal driver 5.

Next, a gate reset signal GRES, a gate pulse clock signal GPCK, and a gate start signal GSR serving as vertical control signals performed by the LCD controller 7
The operation of generating T will be described. The horizontal counter 14 is shown in FIG.
It is reset when the internal horizontal synchronizing signal shown in FIG. The horizontal decoder 13 sets the gate reset signal GRES to low level when the horizontal counter 14 is reset as shown in FIG. After resetting, the horizontal counter 14 counts an internal clock. As shown in FIG. 5C, when the count number of the horizontal counter 14 reaches a predetermined value (timing of T5), the horizontal decoder 13 outputs the gate start signal GSR.
Set T to high level. The horizontal decoder 13 similarly outputs
As shown in FIG. 5D, when the count number of the horizontal counter 14 reaches a predetermined value (timing of T5).
Next, the gate pulse clock signal GPCK is set to the high level.

The LCD controller 7 sequentially outputs the gate reset signal GRES, the gate pulse clock signal GPCK and the gate start signal GSRT generated in this manner.
Is supplied to the scanning driver 3.

Hereinafter, the signal side driver 5 operates the LCD 4 according to the horizontal control signal supplied from the LCD controller 7.
The display of an image for one line (one column) will be described. Note that the gate line GL is in a drivable state by the vertical control signal supplied to the scanning driver 3.

The signal side driver 5 inputs the input image from the inverting amplifier 2 as an RGB inversion signal as shown in FIG. The signal side driver 5 can drive the data line DL of the LCD 4 when the output enable signal OE shown in FIG. Further, the signal side driver 5 outputs the data line start signal S shown in FIG.
When RT goes high, driving of the data line DL of the LCD 4 is started.

The signal side driver 5 starts displaying an image on the LCD 4 after a lapse of a certain period (timing of T6) after the data line start signal SRT shown in FIG. As shown in FIG. 6E, the signal side driver 5 displays the RGB inversion signal supplied from the inversion amplifier until the timing of T7 according to the dot clock signal DCK from the timing of T6. At this time, the dot clock signal DCK is set to 21 as shown in FIG.
Since each pixel is thinned out at a rate of one, the image displayed on 280 liquid crystal display pixels in one line (one column) of the LCD 4 is thinned out from an image of 294 pixels instead of 280 pixels as it is. The image is displayed.

The LCD controller 7 has one line (1
After the output of the horizontal control signal (column), the gate pulse clock signal GPCK of the vertical control signal is set to the high level, and the next gate line GL can be driven. Thus, LC
The D controller 7 displays an image composed of 294 columns × 220 rows of pixels on the LCD 4.

Thus, the image displayed on the LCD 4 is (640/294) / (480/220) ≒ 1, which is almost directly proportional to the image generated by the CCD circuit block 1. That is, the LCD controller 7 converts the image generated by the CCD circuit block 1
Can be displayed.

In the first embodiment, the timing for thinning out the dot clock signal DCK is fixed, but it may be changed for each field (screen). FIG. 7 shows the timing of thinning out the dot clock signal DCK in the field (screen).
A display control device according to a second embodiment of the present invention which can be changed every time is shown.

The display control device shown in FIG. 7 has the same configuration as that of the display control device shown in FIG. 2, but a field signal (FIEL) generated by the synchronous control / field determination unit 16.
D) is supplied to the thinning decoder 20. The field signal (FIELD) is supplied to the thinning-out decoder 20 by the synchronization control / field determination unit 16 by changing values indicating two fields (one field or two fields) alternately for each field (screen).

Hereinafter, the operation of generating the dot clock signal DCK of the horizontal control signal performed by the LCD controller 7 will be described with reference to FIG. The internal clock generation unit 12
In order to approximate the reference clock CK for one column to the liquid crystal display elements of 280 columns of the LCD 4, the reference clock signal CK is set to 1 /
The frequency is divided by 2 to generate the internal clock signal shown in FIG. The internal clock generator 12 converts the generated internal clock signal into a horizontal counter 14, a dot clock generator 15
And to the thinning counter 21.

The thinning counter 21 counts the falling edges of the input internal clock signal 21 by 21 as shown in FIG. 8B. The thinning decoder 20 outputs the field signal (FI) supplied from the synchronization control / field determination unit 16.
If ELD) is determined to be frame 1, FIG.
As shown in (c), when the count value of the thinning counter 21 becomes 9 (timing of T8), the dot clock thinning signal DRES is generated, and the dot clock generating unit 1
5

The dot clock generator 15 is provided as shown in FIG.
As shown in (1), a dot clock signal DCK is generated by dividing the internal clock signal by １ ／. When the dot clock thinning signal DRES is at a low level (timing at T8), the dot clock generator 15 outputs the dot clock signal DRES.
CK is maintained at a high or low level as it is (in FIG. 8D, it is maintained at a low level). After that, when the dot clock thinning signal DRES becomes high level (timing of T9), the dot clock generating unit 15 restarts the generation of the dot clock signal DCK.

On the other hand, the thinning-out decoder 20 performs synchronization control and
Field signal D supplied from field determination unit 16
When the RES is determined to be frame 2, FIG.
As shown in (e), when the count value of the thinning counter 21 becomes 19 (timing of T10), a dot clock thinning signal DRES is generated and supplied to the dot clock generating unit 15.

The dot clock generator 15 is provided as shown in FIG.
As shown in (1), a dot clock signal DCK is generated by dividing the internal clock signal by １ ／. When the dot clock thinning signal DRES is at a low level (timing of T10), the dot clock generation unit 15 maintains the dot clock signal DCK at a high or low level as it is (in FIG. 8F, a high level). Will be maintained). Thereafter, when the dot clock thinning signal DRES becomes high level (timing of T11), the dot clock generating unit 15 restarts the generation of the dot clock signal DCK.

In any of the fields, the dot clock signal DCK has the number of rising and falling timings of 21 while the count of the thinning counter 21 is 21, and the number of the rising and falling timings is originally 21.

As a result, by changing the timing of thinning out the dot clock signal DCK for each field (screen), it is possible to compensate for a partial decrease in resolution.

In the above embodiment, the pixel ratio of the image displayed by thinning out the horizontal control signal is adjusted. However, the pixel ratio of the image displayed by thinning out the vertical control signal may be adjusted.
For example, when the pixel ratio is an image that is flat in the vertical direction, an appropriate image can be displayed by adjusting the pixel ratio of the image to be displayed by thinning out the vertical control signal.

In the above embodiment, the display control device (L
CD controller) controlled the matrix type LCD, but the display device to be controlled is arbitrary. For example, a matrix-type plasma display may be controlled.

[0069]

As described above, an image having a pixel ratio substantially equal to the horizontal and vertical pixel ratio of the supplied image can be displayed on the display device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a display control device and peripheral circuits according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a display control device according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing a generation operation of the display control device that generates the dot clock signal DCK according to the first embodiment of the present invention.

FIG. 4 is a timing chart illustrating a generation operation of the display control device that generates the horizontal control signal according to the first embodiment of the present invention.

FIG. 5 is a timing chart illustrating a generation operation of the display control device that generates the vertical control signal according to the first embodiment of the present invention.

FIG. 6 is a timing chart illustrating a generation operation of the display control device that generates an image for one line (one column) according to the first embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a display control device according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing a generation operation of a display control device that generates a dot clock signal DCK according to a second embodiment of the present invention.

[Explanation of symbols]

1 ... CCD circuit block, 2 ... Inversion amplifier, 3 ... Scan driver, 4 ... LCD, 5 ... Signal side driver, 6 ...
・ Amplifier, 7 ・ ・ ・ LCD controller, 11 ・ ・ ・ Internal horizontal synchronization signal generator, 12 ・ ・ ・ Internal clock generator, 13 ・ ・ ・
Horizontal decoder, 14 horizontal counter, 15 dot clock generator, 16 synchronous control / field discriminator,
17 ... vertical decoder, 18 ... vertical counter, 19 ...
FRP generation unit, 20: thinning decoder, 21: thinning counter

Claims (7)

[Claims] 1. A pixel ratio between a horizontal direction and a vertical direction is a: b.
A synchronization signal input means for inputting a synchronization signal of an image (a and b are natural numbers of 1 or more); and a pixel ratio c: d (c, c) in the horizontal and vertical directions from the synchronization signal input by the synchronization signal input means. d is a natural number of 1 or more, and a: b and c: d are different from each other). A control signal generating means for generating a control signal for controlling a display device in a display area, and a control signal generated by the control signal generating means A control signal output unit that outputs a control signal, wherein the control signal generation unit generates a control signal by dividing a frequency of the synchronization signal input by the synchronization signal input unit and thinning out the divided signal. And the pixel ratio between the horizontal and vertical directions is c: d
A display control device, wherein an image closer to a: b is displayed on the display device. 2. A synchronizing signal input means for inputting a synchronizing signal of a frame image composed of pixels in a matrix of i columns.times.j rows (i and j are natural numbers of 1 or more), and a synchronizing signal inputted by the synchronizing signal input means. Control signal generating means for generating a horizontal control signal and a vertical control signal for controlling a display device comprising matrix display pixels of k columns × h rows (k and h are natural numbers of 1 or more) from the signal; Control signal output means for outputting a horizontal control signal and a vertical control signal generated by the means, a control signal generation means, wherein the control signal generation means, the horizontal direction and the vertical direction of the image displayed on the display device A display control device for generating a horizontal control signal and a vertical control signal whose pixel ratio is closer to i: j than to k: h. 3. The display control device according to claim 2, wherein said control signal generation means generates a horizontal control signal by thinning out a synchronization signal input by said synchronization signal input means. 4. The control signal generating means according to claim 2, wherein said control signal generating means generates a horizontal control signal while changing a timing of thinning out a synchronization signal inputted by said synchronization signal input means for each frame. The display control device according to the above. 5. The display control device according to claim 2, wherein the display device is a liquid crystal display device. 6. The synchronizing signal input by the synchronizing signal input means includes a horizontal synchronizing signal, a vertical synchronizing signal, and a reference clock, and the control signal generating means outputs the horizontal synchronizing signal, the vertical synchronizing signal, and the reference clock. The display control according to any one of claims 2 to 5, wherein a horizontal control signal, a vertical control signal, and a reference clock for a display device including display pixels arranged in a matrix of k columns x h rows are generated. apparatus. 7. A synchronizing signal input for inputting a horizontal synchronizing signal, a vertical synchronizing signal, and a synchronizing signal including a reference clock of a frame image composed of matrix pixels of i columns × j rows (i and j are natural numbers of 1 or more). And a horizontal control signal and a vertical control signal for controlling a display device comprising a matrix of liquid crystal display pixels of k columns × h rows (k and h are natural numbers of 1 or more) from the synchronization signal input in the synchronization signal input step. A control signal generation step of generating a horizontal control signal and a vertical control signal generated by the control signal generation step, and a control signal output step of outputting a vertical control signal, wherein the control signal generation step includes: Dividing the frequency of the synchronization signal input in the synchronization signal input step and generating a horizontal control signal and a vertical control signal by thinning out the frequency-divided signal. , K is the pixel ratio of the horizontal and vertical directions: than h i: displaying on the display device becomes closer image j, the control method of a display device, characterized in that.