JPH1124807A - Composite electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a composite electronic equipment which has plural functions despite the use of only a single connection part to secure high expandability even to a compact computer having low expandability and also can improve its performance to reduce the restriction to expansion of the computer function, to secure its sure operation and also to reduce its power consumption. SOLUTION: A card module includes a main control part IC 14 connected to a main connector 11, an EEPROM 15, a flash memory 16 and a parallel interface part 17. The IC 14 has a function to simultaneously use the memory 16 and an internal parallel input/output function and then divides and synthesizes various types of signals which are inputted and outputted via the connector 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite electronic device, and more particularly to a technique suitable for a memory card to be mounted on a small computer.

[0002]

2. Description of the Related Art Conventionally, there is a card type electronic device as one of peripheral devices such as a small computer, for example, a notebook type personal computer, or one of input / output devices. Currently the most widely used is PCMCIA (Personal Co.
mputer Memory Card International Association). Most notebook personal computers are provided with card slots conforming to the PCMCIA standard, so that various card modules satisfying the above standard can be mounted.

The card module includes a memory card having a built-in semiconductor memory, a card-type hard disk having a built-in hard disk, an interface card having a built-in external interface such as SCSI, a modem card having a FAX modem or the like, and a PC having a built-in microcomputer. There are cards.

[0004]

Incidentally, in recent years, the above-mentioned notebook personal computers have been often used on a desk in a company to save space. It is often used with many external peripheral devices connected at the same time, or expanded in function by connecting various external peripheral devices.

However, in the case of a notebook computer,
In order to reduce the size and weight, there is a tendency to sacrifice the connectivity to external peripheral devices and the expandability of functions, and the usage mode is often limited as compared with a normal desktop personal computer.

For example, in most cases, only one serial port and one parallel port are prepared as external interfaces, and a slot for mounting an interface board for adding ports is usually also prepared. Absent.

[0007] On the other hand, the notebook personal computer is provided with a card slot in order to enhance expandability, so that the functions can be expanded by installing a card module in this card slot. However, since at most two card slots are provided in most cases, there is a limit to the function expansion using this card slot.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a high expandability even for a small computer having poor expandability while providing a single computer with only a single connection. By configuring a composite electronic device that combines the functions of the above, the restrictions on the expansion of the functions of the computer are reduced, the reliable operation of the composite electronic device is guaranteed, and its performance is reduced, such as by reducing the power consumption. To improve it.

[0009]

Means taken by the present invention to solve the above-mentioned problems are the main port connected to the computer main body in a composite electronic device connectable to the computer main body. Memory means capable of storing data input / output via a parallel port, parallel input / output means capable of inputting / outputting the data via a parallel port, the main port, the memory means, and the parallel input / output Input / output control means for controlling the exchange of the data with the means.

According to this means, as the composite electronic device, the memory means controlled by the input / output control means and the parallel input / output means are combined, so that only one connection section (main port) is prepared in the computer main body. It is possible to connect an external peripheral device that can be connected to a parallel port such as a printer or a scanner in addition to the memory for storing data, thereby improving the expandability of the computer and the degree of freedom of usage. Can be increased.

Further, in a multifunction electronic device connectable to a computer main body, first processing means for processing data input / output via a main port connected to the computer main body; A main processing unit, and an input / output control unit for controlling exchange of the data between the first processing unit and the second processing unit. Means for converting the main definition information input / output via the main port, the first definition information relating to the first processing means, and the second definition information relating to the second processing means to / from each other; It is characterized by having.

According to this means, the first processing means and the second processing means
The processing means can be connected to the computer main body by only one connection unit (main port), and the main definition information for responding to the computer main body, the first definition information and the second processing of the first processing means Since the computer has the definition information converting means for mutually converting the second definition information with the means, the computer main body only needs to access a single main definition information as in the past, so that the setting of the computer main body is changed. Without this, the first definition information and the second definition information can be accessed indirectly by the definition information conversion means.

Here, the input / output control means includes a virtual address corresponding to the main definition information, which is used when reading and writing the first definition information and the second definition information simultaneously by the main definition information. Is preferred.

According to this means, since the virtual address corresponding to the main definition information is provided, both the first definition information and the second definition information are accessed at once by designating the virtual address from the computer main body. It becomes possible.

In this case, when the address input through the main port is the virtual address,
An address conversion unit for converting the address into an address belonging to a first address area corresponding to the first definition information and an address belonging to a second address area corresponding to the second definition information may be provided. desirable.

According to this means, since there is provided the address conversion means for converting the virtual address designated by the computer main body into the addresses in the first address area and the second address area, the computer main body has a simple configuration. The addresses of the first definition information and the second definition information for the specified address can be specified at the same time.

Further, a plurality of signal lines of the parallel input / output means are introduced into the parallel port, and at least a part of the signal lines is constantly drawn to a predetermined potential via a high resistance. The parallel input / output means is provided with connection state detection means for detecting a connection state in which a cable or another electronic device is connected to the parallel port and a non-connection state in which the connection is not connected. It is preferable that at least a part of the signal line is fixed to a potential state closer to the predetermined potential.

According to this means, when the parallel port is in the non-connection state, at least a part of the signal line is fixed to a potential state closer to the predetermined potential, so that the amount of current flowing through the high resistance is reduced. Power consumption can be reduced.

In this case, when the non-connection state is detected, the parallel input / output means switches the output gate of the signal line while maintaining the output potential of the output gate in the potential state. Is desirably configured so as to prohibit.

According to this means, the power consumption can be reliably reduced with a simple configuration that only controls the output gate.

[0021] In these cases, the connection state detecting means may further include:
It is desirable that the connection between a constant potential terminal in the parallel port and one of the signal lines be switched between a conductive state and a non-conductive state.

According to this means, the connection state can be detected by changing the potential of the signal line due to conduction or non-conduction with the constant potential terminal in the parallel port. In addition, the potential of the signal line can be reliably set.

[0023]

Next, an embodiment according to the present invention will be described with reference to the accompanying drawings. FIG. 1 shows an overall configuration of an embodiment of a composite electronic device according to the present invention. The present embodiment is configured as a normal PCMCIA standard card module 10. The card module 10 has a size that can be inserted into a card slot of the computer main body.

The card module 10 includes a main connector 11 forming a main port connectable to a connection terminal in the card slot, a parallel connector 12 forming a connection portion of the parallel port, and an internal mode of the card module 10. And a change-over switch 13 for changing the value of. The main connector 11 and the parallel connector 12 are formed at ends opposite to each other, and are respectively mounted on ends of a circuit board housed inside. The parallel connector 12 connects the card module 10 to a computer main body. It is configured so that it can be connected to a connection cable such as a printer or a scanner while being inserted into the card slot.

The changeover switch 13 is a double dip switch, is mounted on the back surface of a circuit board housed inside the card module 10, and is connected to the outside through an opening provided on the back surface of the case body of the card module 10. It is exposed. One of the DIP switches is for switching and selecting between multifunction definition information and ATA format definition information, which will be described later, and switching the mode. The other DIP switch is for switching clock control. belongs to.

Inside the card module 10, a main control IC 14 connected to the main connector 11, an EEPROM (electrically erasable rewritable read only memory) 15 connected to the main control IC 14, A flash memory 16 connected to the control IC 14 and a parallel interface unit 17 similarly connected to the main control IC 14 are provided.

The main control IC 14 has a function of enabling both a flash memory 16 to be described later and an internal parallel input / output function, and various signals input / output via the main connector 11. , Division processing, and the like. In addition to having a configuration register (C register Z) for the parallel port,
It has a virtual configuration register (C register X) for multifunction described later.

The flash memory 16 includes a memory controller 16a and one or more memory chips 16b connected to the memory controller 16a. A configuration register (C register Y) for the ATA interface is provided inside the memory controller 16a.

The parallel interface unit 17 is provided between the parallel connector 12 and a plurality of signal lines drawn from a parallel input / output function unit, which will be described later, provided in the main control IC 14, and includes a driver and a receiver. Parallel buffer 17 functioning as a buffer
a and a pull-up circuit section 17b for pulling up the potential of the signal line. Parallel buffer 17a
Has a protection function of preventing a current from flowing from a cable or the like connected to the parallel connector 12.

FIG. 2 shows a schematic configuration of the main control IC 14 described above. When viewed from a functional point of view, the inside of the main control IC 14 functions as a card interface and S
It is roughly divided into a card function block 14A having a function of controlling the bus and the P bus, and a parallel function block 14B having a parallel port interface function. Here, the card function block 14A constitutes input / output control means for controlling the flash memory and the parallel input / output circuit, and the parallel function block 14B constitutes parallel input / output means together with the parallel interface unit 17.

In the card function block 14A, address signals input / output via the main connector 11;
Various data including a status signal and other signals are transmitted / received via a connection [A] connected to the PCMCIA bus, and data is transmitted / received to / from the flash memory 16 via a connection [B] connected to an ATA interface. Further, various data are internally transmitted / received to / from the parallel function block 14B. The card function block 14A has a built-in input / output register 14a, and is configured to permit or prohibit transmission / reception of data to / from the parallel function block 14B depending on the state of a flag in the input / output register 14a.

The main control IC 14 is provided with a common interface [C] which operates in common with the card function block 14A and the parallel function block 14B. An oscillating circuit 32 including a crystal oscillator, which is a clock generating means for generating a clock signal used for the operation of the parallel function block 14B, is connected to the common interface. Further, a dip switch for mode switching of one of the changeover switches 13 is also connected to the common interface.

The parallel function block 14B is provided with a connection section [D] having a plurality of the signal lines connected to the parallel interface section 17 so as to connect to external peripheral devices connected via the parallel connector 12. To send and receive various data. Further, an input / output timer 14b for measuring the time from the time of the last access to the parallel port via the main connector 11 is built in the parallel function block 14B. The connection [E]
Is a connection part to the EEPROM 15.

FIGS. 3 and 4 show a memory map of the attribute memory space of the card module 10 in the present embodiment. FIG. 3 shows a memory map when the multi-function mode is selected by the changeover switch 13, and corresponds to, for example, a general PC-AT compatible machine. In this case, as will be described later, the access from the personal computer is executed for the definition information of the entire card.

On the other hand, FIG. 4 is a memory map when the mode for the ATA format is selected by the changeover switch 13, and corresponds to, for example, HP-200LX (Hewlett Packard, product number).

In FIG. 3, 0200h to 020Fh
An address of a virtual configuration register (hereinafter, simply referred to as a “C register”) X that holds definition information of the entire card is allocated to the address space up to. By specifying this address, it is possible to simultaneously access the ATA interface definition information and the parallel port definition information, as described later.

In the address space from 0A00h to 0A0Fh, the address of the C register Z holding the definition information of the parallel port is allocated. The C register Z is configured inside the parallel function block 14B. Further, the address of the C register Y for the ATA interface of the flash memory 16 is 1200h.
１２０120Fh, and the memory space W for the ATA interface is allocated to 1000h〜1FFFh.

In the memory map of FIG. 4, the memory space W allocated to addresses 1000h to 1FFFh in the memory map of FIG. 3 is allocated to addresses 0000h to 0FFFh by address conversion. 0200 assigned to the virtual C register X holding the entire definition information
Addresses from h to 020Fh are directly replaced by the addresses of the C register Y holding the definition information for the ATA interface.

With the memory configuration shown in FIG.
By specifying an address in the memory space W, the flash memory 1 is directly connected via the ATA interface.
6 can be accessed. At this time, to simultaneously access both the definition information of the ATA interface and the definition information of the parallel port, it is necessary to use 1200 to 120
It is necessary to specify an address in the range of Fh.

FIG. 5 conceptually shows the relationship among the C registers X, Y, and Z. The address signal AS from the computer connected to the main connector is
, The predetermined address specifying the C register X is converted into both the corresponding address in the C register Y and the corresponding address in the C register Z by the address conversion. The definition information to be read is read by the reading operation of the computer main body, or written by the writing operation of the computer main body.

As a result, since it appears that only the C register X holding the definition information is present in the card module 10 from the computer main unit, it is necessary to control the computer main unit using a normal peripheral device interface structure. Becomes possible.

FIG. 6 is a block diagram showing an example of functional blocks for realizing the conceptual structure shown in FIG. When a read command or a write command arrives from the computer via the main connector 11, an address signal AS specified by the computer is input to the address decoder 21 and the address converter 22, which virtually constitute the C register X. The address decoder 21
When the address signal AS specifies the address of the virtual C register X that holds the definition information of the entire card, the combination CR selection signal CS is changed from a low potential (hereinafter simply referred to as “L”) to a high potential (hereinafter simply referred to as “L”). Hereinafter, it is simply referred to as “H”) and supplied to the address conversion unit 22, the data conversion unit 23, and the data synthesis unit 24.

In the address converter 22, if the combination CR selection signal CS is H, the address signal A
The address specified by S is converted according to the following equations (1) and (2) to form an ATA address AA and a parallel address PA.

AA = CS (bar) × AS + CS × 0200h --- (1) PA = CS (bar) × AS + CS × 1A00h --- (2) Here, CS is the combination selection signal CS. It is 1 when it is H, 0 when it is L, and CS (bar) is 0 when the combination selection signal CS is H and 1 when it is L.
It is. AS indicates an address specified by the address signal AS. Therefore, when the memory map is in the state of FIG. 4, if the address specified by the address signal AS of the computer body is, for example, 1200h (the head address of the C register X), the ATA address AA becomes 0200h (C
The parallel address PA is added to the start address of the register Y).
Is 1A00h (the start address of the C register Z).

The ATA address AA is sent to the address decoder 25 of the C register Y, and the ATA address selection signal ACS selects an area in the data holding unit 26. Also,
The parallel address PA is sent to the address decoder 27 of the C register Z, and the parallel address selection signal PCS selects an area in the data holding unit 28.

The data holding unit 2 thus selected
The data conversion unit 23 converts the write data WDS from the computer main body into the ATA write data WAS and writes it into the data holding unit 26, and converts the write data WDS from the computer into the parallel write data WPS. To the data holding unit 28.

FIG. 7 schematically shows the internal structure of the data conversion unit 23. Here, the write data WDS sent from the computer body is 6-bit data, of which the data portion corresponding to the C register Y is the 0th to second bits, and the data portion corresponding to the C register Z is The third to fifth bits. This is because, in the definition information in the C register Y, predetermined information is included in the 0th to 2nd bits, and the 3rd to 5th bits are fixed to 0 in advance.
This is because the definition information in the register Z is set so that the 0th to 2nd bits are fixed to 0 and the 3rd to 5th bits include predetermined information. Such a configuration can be appropriately set according to the situation such as the bit configuration of the definition information of both.

The data converter 23 is supplied with a combination selection signal CS sent from the address decoder 21 shown in FIG. The combination selection signal CS is inverted by the NOT circuit 23-6 and
(Bar), and AND circuits 23-0, 23-1, 23
−2, 23-3, 23-4, and 23-5.

The 6-bit write data WDS of the computer main unit transmits the contents of the 0th and 2nd bits as they are, and the contents of the 3rd to 5th bits are transferred to the AND circuit 23.
-3, 23-4, and 23-5 take the logical product with CS (bar) to obtain the ATA write data WAS.
Is converted to

Similarly, the write data WDS is 0 to 2
Regarding the contents of the order bits, the AND circuits 23-0, 23
By taking the logical product with CS (bar) by -1, 23-3,
By transmitting the contents of the third to fifth bits as they are, they are converted to parallel write data WPS.

The address signal from the computer body is C
When the address of the register X is specified, the combination selection signal CS becomes H and CS (bar) becomes L, so that the ATA write data WAS has the third to fifth bits fixed to 0, and the parallel write data WAS. In the WPS, the 0th to 2nd bits are fixed to 0. Therefore, when the card module 10 is used as a composite electronic device,
By using the address from the computer as the address assigned to the C register X, both the definition information data corresponding to the ATA interface and the definition information data corresponding to the parallel port can be simultaneously written.

When reading the definition information data of the C register Y and the C register Z, the conversion and address designation of the address signal AS from the computer are the same as described above. In this case, as shown in FIG.
6, ATA read data RAS read from
The parallel read data RPS read from the data holding unit 28 is combined in the data combining unit 24,
The data is taken into the computer as integrated read data RDS.

The configuration of the data synthesizing section 24 is such that the read data RAS for ATA and the read data RPS for parallel are simply added by an OR circuit for each bit. In the above example, the read data RDS synthesized by the data synthesizing unit 24 includes the 0th to 2nd bits of the ATA read data RAS as the 0th to 2nd bits, and the 3rd to 5th bits of the parallel read data RPS. Is provided as the third to fifth bits.

When the address signal from the computer is C
When an address other than the register X is designated, the combination selection signal CS generated from the address decoder 21 becomes L, and as shown in the above equations (1) and (2), no address conversion is performed and the normal address is not converted. Processed in the same way as specified. In this case, as shown in FIG. 7, the write data WDS of the computer main body is written in an area corresponding to the specified address in all bits in the data conversion unit 23 because CS (bar) becomes H. . Also, in the case of reading, the read data RDS is read as it is from the area corresponding to the specified address.

As described above, the card module can be controlled by the definition information corresponding to the single C register even if the access is made from the computer body, and the definition information held by the card module is also a single definition. C
Since the data can be read as data corresponding to the register, the computer can be connected as a composite electronic device without particularly changing the control configuration of the computer main body.

FIG. 8 shows a schematic configuration of a part of the main control IC 14, the parallel interface unit 17, and the parallel connector 12 of the present embodiment. The parallel signal output from the main control IC 14 is constituted by 25 signal lines.

The first pin of the parallel connector is connected to a line that carries a data strobe signal. 2
Pins 9 to 9 are the data buses of the parallel port,
The pin number is the least significant bit (LSB), and the ninth pin is the most significant bit (MSB). The 10th pin is connected to a signal line of a response signal of an external peripheral device connected to the parallel connector 12.

The eleventh pin is connected to a signal line of a busy signal of an external peripheral device. The twelfth pin is connected to the signal line for the out-of-paper signal of the external peripheral device. 13
The number pin is connected to a signal line of a selection signal of an external peripheral device. The 14th pin is connected to a signal line of a signal indicating a line feed. The fifteenth pin is connected to a signal line of a signal indicating a peripheral device abnormality, and the sixteenth pin is connected to a signal line of a signal indicating a hard reset.
The 17th pin is connected to a signal line of a signal for validating data output to an external peripheral device.

The 18th to 23rd pins are the card module 10
Connected to ground potential. The 24th pin is connected to a signal line of a status signal indicating that the external peripheral device is turned on. The 25th pin is connected to a signal line L25 indicating that the connector 30 of the cable is connected when the potential is L (ground potential), as will be described later. The signal line is configured to be valid.

The parallel buffer 17a of the parallel interface unit 17 is provided with a main control I for an output type signal line (a signal line for sending data to an external peripheral device).
It takes in the potential output from C14 and outputs it to the pull-up circuit 17b. The input signal line (signal line for taking in data from an external peripheral device) takes in the potential output from the pull-up circuit 17b and outputs it to the main control IC 14.

The pull-up circuit 17b of the parallel interface section 17 is connected to the potentials of a plurality of signal lines (signal lines corresponding to the 1st to 17th pins and the 25th pin) connected between the main control IC 14 and the parallel connector 12. Is pulled up toward the VCC potential by a high resistance.

The signal line L25 supplies a connection signal CC to the main control IC 14, and the connection signal CC is supplied to the OR circuit 1
4-2 is input to one input terminal. Further, the connection signal CC is input to the NOT circuit 14-1, and the inverted signal CC
(Bar), and is input to one input terminal of the NAND circuit 14-3. OR circuit 14 for inputting connection signal CC
The NAND circuit 14-3 for inputting -2 and the inverted signal CC (bar) is an output type signal line, that is, the first to ninth (the second to ninth are input / output type), 14 of the parallel connector 12.
It is connected to the signal lines connected to the No. 16, No. 16 and No. 17 pins respectively.

When the parallel connector 30 is not connected, the connection signal CC of the signal line 25 is pulled up to a high potential H, and the outputs of the OR circuit 14-2 and the NAND circuit 14-3 are fixed at H. Regardless of the output signal from the functional block 14B, switching of the output type signal lines is prohibited, and the potentials of these signal lines are constantly maintained at the high potential H. Therefore, in the pull-up circuit 17b, the current flowing into these signal lines via the high resistance can be reduced, so that the power consumption is suppressed.

The connection cable 30 is connected to the parallel connector 12.
Is connected, the 25th pin of the connection cable 30 becomes 23
Since the signal line L25 is connected to the No. 23 pin, the signal line L25 is indirectly connected to the grounded No. 23 pin of the parallel connector 12, so that the connection signal CC has a low potential L. Therefore, the OR circuit 14-2 and the NAND circuit 14
-3 both transmit the switching state of the output potential output from the parallel function block 14B.

As described above, in this embodiment, the connection of the connection cable 30 to the parallel connector 12 is performed by the signal line L.
25, and when not connected to the parallel connector 12, the potential of the output type signal line is fixed to a potential near the pull-up potential of the pull-up circuit 17b or a power supply potential, so that power consumption is suppressed. can do.

In this embodiment, as shown in FIG. 2, the parallel function block 14B in the main control IC 14
An input / output timer 14b is built therein. The input / output timer 14b is connected to the main connector 1
1 and the time from the last access to the parallel function block 14B via the card function block 14A is measured. If there is no access from the computer for a predetermined time, the input / output timer 14b times out as shown in FIG.
When the flag in the input / output register 14a arranged in the card function block 14A changes to L (0) and the oscillator enable signal changes from H to L, the clock signal generated from the oscillation circuit 32 including the crystal oscillator Is to be stopped.

When a read or write signal is sent from the computer when the oscillation circuit 32 is stopped in this manner, the WAIT signal output from the card function block 14A becomes H, and the computer reads or writes the signal. In order to extend the signal cycle and set the input / output register to H (1), the oscillation circuit 32 starts oscillating by setting the oscillator enable signal to H, and the clock signal is stabilized after a while.

The high potential H of the WAIT signal is maintained for a time τ longer than the time from when the oscillation circuit 32 starts oscillating until the oscillation circuit 32 stabilizes. When the time τ has elapsed, the WAIT signal returns to L again. Thereby, the access of the computer main body is performed. When the access of the computer body is completed, the input / output timer 14b is reset again, and the time measurement is started again from that point.

As described above, when there is no access from the computer body, the power consumption can be further reduced by stopping the oscillation circuit 32 that generates the clock signal necessary for the operation of the parallel function block 14B. Here, the above-mentioned predetermined time τ is a time required for the clock signal of the oscillation circuit 32 to stabilize, and is usually about several ms.

It is to be noted that a program for sending a notice signal for starting oscillation in the oscillation circuit 32 is provided in the computer at least a predetermined time τ before the normal access to the parallel port from the computer body is started. The configuration also ensures that the oscillation circuit can be restored.

[0071]

As described above, according to the present invention, the following effects can be obtained.

According to the first aspect, as the composite electronic device, the memory means controlled by the input / output control means and the parallel input / output means are combined, so that only one connection portion (main port) is provided in the computer main body. Just by preparing, in addition to the memory for storing data, it is possible to connect external peripheral devices that can be connected to parallel ports such as printers and scanners, so that it is possible to improve the expandability of the computer and to freely use it. The degree can be increased.

According to the second aspect, the first processing means and the second processing means
The processing means can be connected to the computer main body by only one connection unit (main port), and the main definition information for responding to the computer main body, the first definition information and the second processing of the first processing means Since the computer has the definition information converting means for mutually converting the second definition information with the means, the computer main body only needs to access a single main definition information as in the past, so that the setting of the computer main body is changed. Without this, the first definition information and the second definition information can be accessed indirectly by the definition information conversion means.

According to the third aspect, since the virtual address corresponding to the main definition information is provided, both the first definition information and the second definition information can be accessed at once by specifying the virtual address from the computer main body. It becomes possible to do.

According to the fourth aspect of the present invention, there is provided an address translation means for translating a virtual address designated by the computer into an address in the first address area and an address in the second address area. The address of the first definition information and the address of the second definition information for the specified address can be specified at the same time.

According to the fifth aspect, when the parallel port is in the non-connection state, at least a part of the signal line is fixed to a potential state closer to the predetermined potential, so that the amount of current flowing through the high resistance is reduced. Power consumption can be reduced.

According to the sixth aspect, the power consumption can be reliably reduced with a simple configuration that only controls the output gate.

According to the seventh aspect, the connection state can be detected by changing the potential of the signal line due to conduction or non-conduction with the constant potential terminal in the parallel port. The potential of the signal line can be easily and reliably set.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an overall configuration of an embodiment of a composite electronic device according to the present invention.

FIG. 2 is a schematic configuration diagram showing an overall configuration and a connection state of a main control IC according to the embodiment.

FIG. 3 is a memory map of an attribute memory space in a multi-function mode in the embodiment.

FIG. 4 is a memory map of an attribute memory space in an ATA mode in the embodiment.

FIG. 5 is a schematic explanatory diagram showing functions of a virtual configuration register in the embodiment.

FIG. 6 is a block diagram showing a configuration for realizing a function of a virtual configuration register in the embodiment.

FIG. 7 is a schematic circuit diagram illustrating an internal configuration of a data conversion unit according to the first embodiment.

FIG. 8 is a schematic circuit diagram showing an outline of a means for detecting a state where a parallel connector is not connected and changing a connector state among parallel input / output means in the embodiment.

FIG. 9 is a timing chart showing a procedure of stopping and restoring a clock in the embodiment.

[Explanation of symbols]

 Reference Signs List 10 Card module 11 Main connector 12 Parallel connector 13 Changeover switch 14 Main control IC 14A Card function block 14B Parallel function block 14a Input / output register 14b Input / output timer 15 EEPROM 16 Flash memory 17 Parallel interface 17a Parallel buffer 17b Pull-up circuit 30 Connection cable X C register (virtual) Y C register (for ATA) Z C register (for parallel) L25 signal line

Claims (7)

[Claims] 1. A composite electronic device configured to be connectable to a computer body, a memory means capable of storing data input / output via a main port connected to the computer body, and Parallel input / output means capable of inputting / outputting via a parallel port, the main port, and input / output control means for controlling exchange of the data between the memory means and the parallel input / output means; A composite electronic device comprising: 2. A composite electronic device configured to be connectable to a computer main body, a first processing unit for processing data input / output via a main port connected to the computer main body, A second processing means for processing the data, an input / output control means for controlling the exchange of the data between the main port and the first processing means and the second processing means, Means for converting the main definition information input / output via the main port, the first definition information relating to the first processing means, and the second definition information relating to the second processing means to / from each other; A composite electronic device, comprising: 3. The virtual machine corresponding to the main definition information, wherein the input / output control means is used when the first definition information and the second definition information are simultaneously read and written by the main definition information. A composite electronic device having an address. 4. An apparatus according to claim 3, wherein, when the address input through said main port is said virtual address, said address belongs to a first address area corresponding to said first definition information; A composite electronic device comprising an address conversion means for converting an address belonging to a second address area corresponding to the second definition information into an address belonging to the second definition area. 5. The parallel port according to claim 1, wherein a plurality of signal lines of said parallel input / output means are introduced into said parallel port, and at least a part of said signal lines is always drawn to a predetermined potential via a high resistance. The parallel input / output means is provided with a connection state detection means for detecting a connection state in which a cable or another electronic device is connected to the parallel port and a non-connection state in which the connection is not connected. In the non-connection state, the composite electronic device is configured to fix at least a part of the signal line to a potential state closer to the predetermined potential. 6. The parallel input / output unit according to claim 5, wherein when the non-connection state is detected, the parallel input / output means keeps the output potential of the output gate of the signal line in the potential state, and A composite electronic device configured to prohibit switching. 7. The connection state detecting means according to claim 5, wherein the connection state detection means determines whether a conduction state between a constant potential terminal in the parallel port and one of the signal lines is determined by the connection state and the non-connection state. A composite electronic device configured to be switched between a non-conductive state and a non-conductive state.