JPH11243143A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an element isolation region, as well as a resistant element having stable electrical characteristics on the surface of a semiconductor substrate. SOLUTION: An element isolation region 26 and a resistant element 28 are formed on the surface of a semiconductor substrate 12. The element isolation region 26 and the resistant element 28 are respectively provided with trenches 20, 22 formed on the surface of the substrate 12, while oxide films 20a, 22a are formed on the surface of the trenches 20, 22. Next, the trenches 20, 22 are filled with a non-doped polycrystalline silicon 24. As a result of these procedures, the resistant element 28 having stable electrical characteristics as well as the element separating region 26 can be formed on the surface of the semiconductor substrate 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which an element isolation region and a resistance element are formed on a semiconductor substrate.

[0002]

2. Description of the Related Art As a method for forming a resistance element on a semiconductor substrate, a so-called diffusion resistance in which a region as a resistor is formed by introducing an impurity into a substrate surface has been known for a long time. The diffusion resistance can be easily formed by introducing an impurity of a conductivity type different from that of the substrate to a resistance required for a circuit formed on the substrate, and has been used as a basis of semiconductor technology. However, the diffusion resistance is directly affected by the substrate potential and further greatly dependent on the temperature because the element is provided in the junction of the substrate.

For this reason, as a resistor formed in an IC circuit, a resistor using polycrystalline silicon is widely used at present. When a resistance element is formed using polycrystalline silicon, for example, a polycrystalline silicon film is deposited and formed on a substrate surface, an (SiO ₂ ) oxide film is deposited and formed on the polycrystalline silicon film, and this oxide film is formed by photolithography. Using a patterned oxide film as a mask, impurities are introduced into the polycrystalline silicon, if necessary, using a patterned oxide film as a mask. The polycrystalline silicon into which the impurities have been introduced as described above is etched into a required shape by a photolithography method to form a resistive element having a required resistance value (or resistivity) on the substrate. The polycrystalline silicon resistance element formed in this manner is covered with another element such as a wiring in an insulating state by an interlayer insulating film or a surface protection film.

[0004]

However, since the resistive element made of polycrystalline silicon formed as described above is provided on the surface of the substrate, another insulating film, wiring, or the like is formed by lamination in a subsequent process. In such a case, polycrystalline silicon is deformed or distorted due to a stress effect generated outside and / or inside the polycrystalline silicon due to a temperature change or the like occurring during the manufacturing process.
As a result, there is a problem that a change in resistance characteristics (resistance value, resistivity, etc.) occurs in the formed polycrystalline silicon.

In particular, with the recent progress of high integration and miniaturization of ICs and the like, as the miniaturization of circuit elements of semiconductor devices and the increase of the number of layers of wiring and the like progress, the substrate and the stacking level on the surface side thereof increase. The stress generated between them has also become more apparent,
As described above, the change in the resistance characteristic of the polycrystalline silicon resistance element has become a more prominent problem. On the other hand, with the miniaturization of elements, from the idea of using the substrate not only in the surface area but also in the depth direction, trench technology for forming an element using a trench formed in the inner surface direction of the substrate has been greatly developed. As for the isolation technique, an STI (Shallow Trench Isolation) technique has been put to practical use.

SUMMARY OF THE INVENTION An object of the present invention is to form a resistance element having stable electric characteristics together with an element isolation region on a surface of a semiconductor substrate by a simple method.

[0007]

SUMMARY OF THE INVENTION The present invention is a semiconductor device having an element isolation region and a resistance element on a surface of a semiconductor substrate, wherein the element isolation region and the element isolation region are respectively formed on the surface of the substrate. A trench, an oxide film formed on the inner surface of the trench, and polycrystalline silicon embedded in the trench where the oxide film is formed.

The present invention also relates to a method of manufacturing a semiconductor device in which an element isolation region and a resistance element are formed on a surface of a semiconductor substrate, wherein (a) a plurality of trenches are formed on the surface of the substrate by etching; (C) An oxide film is formed on the inner surface of the formed trench, and (c) a device isolation region and a resistance element are formed by filling the inside of the trench with polycrystalline silicon.

[0009]

Since the resistance element made of polycrystalline silicon is provided not in the outside of the substrate but in the surface of the substrate together with the element isolation region, even a structure in which wirings and the like are multi-layered is caused by heat treatment or the like. There is no possibility of being affected by external stress. Therefore, the resistance element can maintain stable electrical characteristics (resistivity and resistance value) which are not affected by stress deformation and distortion due to external stress. Since the resistance element is formed of polycrystalline silicon, the temperature dependence and the voltage dependence are small as compared with the diffusion resistance, and the reliability as the resistance function is high. When non-doped polycrystalline silicon is used, the resistance value of the resistance element can be determined by the element size (width dimension, depth dimension, length). In the case where an impurity is doped into polycrystalline silicon, the resistance value can be adjusted in accordance with the type of the impurity, the amount to be introduced, the heat treatment, and the like in addition to the above size. Such impurity doping can be performed in a common step with the formation of elements of other elements (eg, gate electrode doping, channel doping, etc.).

[0010]

As described above, the resistance element and the element isolation region can be simultaneously formed in a single substrate, and the process is simplified. Although the resistance element is provided in the substrate, its periphery is defined by an oxide film (SiO ₂ ), so that the resistance element is electrically insulated from the outside. Therefore, since it is not affected by the electrical characteristics due to the substrate side potential such as the diffusion resistance and is located inside the substrate surface, thermal stress, thermal distortion, etc. from other elements (wiring, insulating film), etc. There is no fear of receiving. Further, even when both the element isolation region and the resistance element are formed through an anisotropic etching process, the interface between these elements and the substrate is provided with an R portion at a corner corner by forming a thermal oxide film, for example. Thus, the risk of electric field concentration at corners can be reduced.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to the steps shown in FIG. First, FIG.
As shown in FIG. 1A, a semiconductor substrate 12 made of, for example, silicon is prepared, and an oxide film 14 made of SiO _{2 is} formed on this substrate by thermal oxidation. Then, the oxide film 14
A nitride film 16 made of Si ₃ N _{4 is} deposited and formed on the surface of the substrate by CVD. In order to alleviate the thermal stress generated during the process, an SiO ₂ oxide film 14 is provided between the nitride film 16 and the substrate surface. Further, the nitride film 16 functions as a barrier against contamination by the photoresist used in the process.

Using the resist layer 18 thus formed as a mask, the nitride film 16 and the oxide film 14 are patterned by a photolithography method.
8 is removed, and reactive ion etching (RI) is performed using the patterned oxide film 14 and nitride film 16 as a mask.
By performing anisotropic etching on the substrate surface by the method E),
The trenches 20 and 22 are formed (FIG. 1B). Here, the trenches 20 and 22 are provided for forming an element isolation region and a resistance element, respectively. The anisotropic etching used here is the same as the RIE described above.
Ion beam etching (RIB)
Other etching methods such as E) can be applied.

After the trenches 20 and 22 are formed in the substrate 12, as shown in FIG. 1C, using the oxide film 14 and the nitride film as a mask, the inner walls of the trenches 20 and 22, ie, the side walls of the respective trenches, are formed. Then, thermal oxide films 20a and 22a are thermally grown on the bottom surface. At this time, the oxide film 14 and the nitride film 16 on the substrate surface serve as a mask, and the inner wall of the trench is selectively oxidized. These oxide films 20
In addition to the thermal oxidation, the TEOS method and other oxide film forming techniques can be applied to the a and 22a. In this case, sufficient attention should be paid to the withstand voltage characteristics and step coverage of the oxide film to be formed. is there. After forming the thermal oxide film as described above, the nitride film 18 is peeled off.

Then, as shown in FIG. 1D, the non-doped polycrystalline silicon layer 24 is formed on the thermal oxide films 20a and 22a.
Is formed by deposition under a low pressure CVD (LP-CVD) process. The reaction temperature at this time is set within a range of approximately 600 to 650 ° C. That is, 600
At temperatures below ℃, the reaction rate is slow and impractical,
If the temperature is 650 ° C. or higher, the film surface is roughened and the adhesion is inferior.

After the formation of the polycrystalline silicon layer 24, the polycrystalline silicon layer 24 covering the substrate surface is planarized by performing a CMP method (chemical mechanical polishing) (FIG. 1).
(E)). Here, the CMP method refers to a polishing process that is performed chemically and mechanically using a slurry containing abrasive particles in a suspension state, and is used as a means for planarizing the surface of a semiconductor wafer. By performing such a CMP process on the polycrystalline silicon layer 24, the trench region 2 buried with non-doped polycrystalline silicon, which is substantially planarized on the substrate surface, is obtained.
6, 28 are obtained.

Each of the formed trench regions 26 and 28 has a silicon substrate 1 as shown in FIG.
2 is defined on the surface of the substrate 2 through thermal oxide films 20a and 22a so as to be substantially identical to the substrate surface. The trench regions 26 and 28 each have an oxide film (SiO ₂ ) formed on the surface as necessary, and are used as element isolation regions and resistance elements. That is, the element isolation region 26 and the resistance element 28 of this embodiment are cross-sectional views of main parts in a schematic plan view shown in FIG.

The isolation characteristics (dielectric withstand voltage, etc.) of the element isolation region 26 depend on the width (in the horizontal direction in FIG. 1), the depth, the thickness of the thermal oxide film, and the like. Is determined according to the type and size of the elements to be arranged, the integration density, and the like. In the above embodiment, the resistance element is formed of non-doped polycrystalline silicon whose periphery is defined by a thermal oxide film. However, the resistance element may be formed of polycrystalline silicon doped with impurities such as P + ions. it can. Such impurities can be easily introduced by ion implantation. The resistance value of the formed resistive element is determined by the size (width, depth, length) of the polycrystalline silicon portion, and when impurities are introduced, the type and amount of impurities and the amount of heat treatment are also determinants. .

FIG. 2 shows the shape of the element isolation region and the resistance element formed by the above embodiment. FIG. 2 (A)
FIG. 1B schematically shows a cross section of an element isolation region (or a resistance element) obtained when the trenches 26 and 28 in FIG. 1B are formed by anisotropic etching (for example, RIE method). In the case of this figure, since dry etching is used, it is particularly advantageous when fine processing is required depending on the element dimensions and the degree of integration. Although the corner C1 at the bottom of the trench is square, a slight R portion is provided at the corner by the formation of a thermal oxide film, so that the possibility of electric field concentration is reduced.

FIG. 2B schematically shows a cross section of an element isolation region (or a resistance element) obtained when the trenches 26 and 28 are formed by isotropic etching (for example, a wet etching method). In this case, the corner C at the bottom of the trench
Since a relatively large R portion is given to 2, the possibility of electric field concentration is greatly reduced. FIG. 2C shows a planar shape of an element isolation region (left side) and a resistance element (right side) formed on the substrate according to the process of FIG. Contact regions are formed at both ends of the resistance element, through which an ohmic junction is formed between the wiring conductor such as aluminum and the like (between polycrystalline silicon). As described above, the resistance value of the resistance element is determined by its size and shape. In order to obtain a larger resistance value, for example, the resistance region is formed to be folded or bent so as to extend linearly. By doing so, the arrangement efficiency of the elements can be increased.

Next, an example in which the manufacturing method of the present invention is applied to a CMOS structure will be described with reference to FIG. That is, a well 34 of another conductivity type, that is, an N type is formed in one surface region of a silicon substrate 32 of one conductivity type, for example, P type. The surface of the well 34 has a P-type MOSF
ET42 is formed. That is, the FET 42 has a gate electrode 42G made of polycrystalline silicon provided on the well 34 with an oxide film interposed therebetween, and source and drain regions 42S formed of P-type diffusion regions formed on both sides of the gate electrode 42G on the surface of the well 34; 42D. On the other hand, an N-type M
An OSFET 44 is formed. That is, the FET 44 has a gate electrode 44G made of polycrystalline silicon provided on the substrate 32 via an oxide film, and a gate electrode 4G on the substrate surface.
It has source and drain regions 42S and 44D formed of N-type diffusion regions formed on both sides of 4G. Here, these MOSFETs are insulated from each other by an element isolation region 36 according to the present invention, which is formed across the substrate and the well.

On the other hand, a resistance element 38 is formed in a substrate region adjacent to the N-type FET 44 on the side opposite to the FET 42. The resistance element 38 and the FET 44 are also separated by the element isolation region 46 according to the present invention. These element isolation regions 36 and 46 have the same configuration as the region 26 described with reference to FIG. 1, and the resistance element 38 has the same configuration as the resistance element 28 in FIG. These FET4
2 and 44 and the resistance element 38 are connected to each other by a wiring (not shown) so that a circuit having a certain function, for example, an inverter,
Is configured. The P-type regions indicated by 48 and 50 in FIG. 3 are channel stop regions provided as needed.

The MOS structure having the element isolation region and the resistance element shown in FIG. 3 can be formed according to the following steps. That is, as shown in FIG. 4A, a silicon substrate 32 having an N-type well 34 formed on the front surface side by a conventional technique is prepared, and trenches 36a, 38a, 46a are formed (FIG. 4B). Next, a substrate region corresponding to the channel stops 48 and 50 in FIG.
Portion 46a is implanted with boron (B) ions for channel stop by a focused ion beam implantation method without using a mask. This ion implantation may be performed by a normal ion implantation method using a mask at the stage before the trench formation in FIG. 4B, but in this case, a larger implantation is performed in consideration of the etching amount of the trench. Energy needs to be selected. Next, the formed trenches 36a, 38a,
After forming a thermal oxide film on the inner surface of 46a, a non-doped polycrystalline silicon layer is formed on the entire surface of the substrate including the trench,
Next, the polycrystalline silicon layer except for the inside of the trench is polished and removed by the above-described CMP method.

By forming an oxide film (SiO ₂ ) on the surface of the substrate including the polycrystalline silicon region planarized by the CPM polishing, the element isolation regions 36 and 46 and the resistance element 38 are formed.
Is provided. Next, FET using polycrystalline silicon
Gate electrodes 42G and 44G are patterned on the surface of the well 34 and the substrate 32 via the oxide film (FIG. 4).
(C)). Then, as in the normal CMOS process, P-type impurities (B ions) and N-type impurities (As ions) are implanted using the gate electrodes 42G and 44G as a mask and heat treatment is performed to perform source and drain regions of the FETs 42 and 44. 42S, 42D and 44S, 44D are formed (FIG. 4D). Then, by providing the necessary wiring, the interlayer insulating film, the surface protection film and the like by the conductor such as Al according to the MOS technology, the MOS type semiconductor device having the element isolation region and the resistance element of the present invention can be obtained. .

The resistance element 38 thus formed is made of non-doped polycrystalline silicon deposited on an oxide film (SiO ₂ ) formed on the interface with the substrate and on the upper surface, and has a resistance value. As described above, it goes without saying that the adjustment can be made by the type and the amount of the introduced dopant, in addition to the shape of the device. For example, although the description is omitted in the embodiment of FIG. 4, it is also possible to inject the resistive element into polycrystalline polysilicon at the time of impurity implantation into the polysilicon gate or channel doping.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing main steps of a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an element isolation region and a resistance element formed according to the embodiment of FIG.

FIG. 3 is a sectional view of a main part of a semiconductor device having a MOS structure to which the manufacturing method of the present invention is applied.

4 is a fragmentary cross-sectional view showing main processes of the semiconductor device of FIG. 3;

[Explanation of symbols]

12 ... semiconductor substrate 14 ... SiO ₂ oxide film 16 ... Si ₃ N ₄ nitride film 18 ... photo-resist 20, 22 ... trench 20a, 22a ... thermal oxide film 26 ... isolation region 28 ... resistance element 34 ... well 36, 46 ... Element isolation region 38 Resistive element 42 P-type FET 44 N-type FET

Claims (4)

[Claims] 1. A semiconductor device having an element isolation region and a resistance element on a surface of a semiconductor substrate, wherein the element isolation region and the element isolation region each include a trench formed on a surface of the substrate, A semiconductor device comprising: an oxide film formed on an inner surface of a trench; and polycrystalline silicon buried inside the trench where the oxide film is formed. 2. The semiconductor device according to claim 1, wherein said polycrystalline silicon is non-doped polycrystalline silicon. 3. A method of manufacturing a semiconductor device, comprising forming an element isolation region and a resistance element on a surface of a semiconductor substrate, comprising: (a) forming a plurality of trenches on the surface of the substrate by etching; (C) forming an oxide film on the inner surface of the trench, and then forming an element isolation region and a resistance element by filling the inside of the trench with polycrystalline silicon. 4. The method according to claim 3, wherein in the step (b), the oxide film is formed by thermal oxidation, and in the step (c), non-doped polycrystalline silicon is embedded.