JPH11242649A - Expander for system bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively utilize the idle slot of a bus rack by providing a bus expander compatible with the VME bus standard even when a board having an address allocated to the slave means of a bus expander board inserted to the slot of its own bus rack is inserted and connected to the slot of its own bus rack. SOLUTION: Between two expander boards 5A and 5B, a gate circuit is bidirectionally provided for supplying data acknowledge and bus error signals generated at one system bus 4A (4B), wherein the gate circuit is opened corresponding to a bus use detecting signal provided when one of respective bus master means 6A and 6B acquires the right to use the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus for arbitrating the right to use a board inserted into a slot of a bus rack by a system controller, in order to increase the number of usable boards, by connecting two bus racks bidirectionally. Regarding the bus expander to be coupled, in particular, this bus expander adopts a method of allocating a part of the address of one system bus for access to the other system bus, so that a board having a fixed address is used. An object of the present invention is to solve the problem that a bus rack that can be inserted is specified, and even if one of the bus racks has an empty slot, it cannot be inserted into the empty slot.

[0002]

2. Description of the Related Art A VME bus is known as a typical standardized bus. This VME bus is connected to the bus master C
A bus system is configured by inserting a PU board or a memory board serving as a bus slave into a slot of a rack and connecting it to a connector of a motherboard having a common bus line composed of an address line, a data line, and a control line.
This VME bus arbitrates bus use requests from a plurality of boards by a bus arbiter of the system controller, and allows only the bus master who has obtained the bus use right to access the bus master.

The above-mentioned VME bus rack is manufactured with the number of slots equal to or less than the maximum number defined by the VME standard. Therefore, when actually constructing a computer system, V
In some cases, the required number of boards cannot be inserted into the ME bus rack. Therefore, a bus expander has been proposed in which a plurality of VME bus racks are bidirectionally connected so that a computer system can be constructed by a plurality of VME bus racks (Japanese Patent Laid-Open Nos. 2-178752 and 2-178).
753). This enables mutual access of boards inserted in different VME bus racks.

FIG. 3 shows an example of connecting a bus rack using this bus expander. The VME bus racks A and B to be connected include, in their slots, system controller boards 1A and 1B for arbitrating bus use requests, CPU boards 2A and 2B as bus masters, and memory boards 3A and 3B as bus slaves. Each of the inserted boards is mutually connected by sharing the system buses 4A and 4B.

The bus expander 5 for connecting the bus racks A and B includes two expander boards 5A and 5B each having a bus master means 6A (6B) and a bus slave means 7A (7B) by connecting an address line and a data line. , And connection lines 8A and 8B composed of access request lines and the like. Two expander boards 5A, 5
B is inserted into the slots of the VME bus racks A and B, respectively, and connected to the system buses 4A and 4B.

The address of the board to be inserted into the bus rack B is assigned to the bus slave means 7A of the expander board 5A, and the address of the board to be inserted into the bus rack A is assigned to the bus slave means 7B of the expander board 5B. ing. This is because the bus slave means 7A (7B) accepts an access request to the other bus rack in its own bus rack. When an access to the address is made in its own bus rack, the bus slave means 7A (7B) transmits the other request through the access request line. Issue an access request to the bus master means 6A (6B) of the bus rack. When the bus master means 6A (6B) receives an access request from the bus slave means 7B (7A) of the other bus rack, issues a bus use request to its own system bus and acquires the bus use right. The access to the own bus rack is relayed from the other bus rack.

This operation will be described for the case where the CPU board 2A of the bus rack A accesses the memory board 3B of the bus rack B as shown in FIG.

When the CPU board 2A, which is the bus master, attempts to access the memory board 3B and issues its address to the system bus 4A, the bus slave means 7A of the expander board 5A to which the address is assigned receives the address. Bus master means 6B of expander board 5B through access request line of connection line 8A
Issues an access request to. The bus master means 6B of the expander board 5B issues a bus use request to its own system bus 4B, and when the bus use permission is received from the system controller 1B, the bus master means 6B performs through the connection line 8A.
The access (read / write of data) of the PU board 2A to the memory board 3B is relayed. Such an access procedure is similarly performed when the CPU board 2B of the bus rack B accesses the memory board 3A of the bus rack A.

Since the bus expander 5 connects two bus racks in two directions as shown in FIG. 5, the number of bus expanders required is the number of combinations of each bus rack. , Used bus rack A,
There is a practical limit to the number of B, C, D,... To solve this, as shown in FIG. 6, a bus rack E having a function of arbitrating a bus use request may be provided for relaying. In the case of FIG. 6, the number of used bus expanders 5 is a number obtained by subtracting 1 from the total number of bus racks, and as in the case of FIG. There will be no exponential increase.

[0010]

When the bus expander 5 has its own bus rack, for example, A, the bus expander 5 assigns the address assigned to the bus slave means 7A of the expander board 5A inserted into the bus rack A to its own. It is assumed that it is not used with a board such as a memory inserted in the bus rack A. Therefore, when a board having an address to be inserted into another bus rack B is inserted into its own bus rack A, a violation of the VME bus standard occurs in the other bus rack B, and the operation of the arbiter of the system controller 1B is disrupted. There was a problem.

This will be described in detail. As shown in FIG. 7, the bus slave means 7A of the expander board 5A
It is assumed that the memory board X having the address assigned to the bus rack A has been inserted. At this time, the bus rack A
In the case where the memory board X is accessed from the CPU board 2A, consider the access signal waveform diagram of FIG. C
An address signal (ADD), an address strobe signal (AS *), and a data strobe signal (DS *) issued from the PU board 2A to the system bus 4A of the bus rack A.
Is received by the bus slave means 7A of the memory board X and the expander board 5A. In response to this, the memory board X returns a data signal (DATA) and a data acknowledge signal (DTACK *) to the system bus 4A. Therefore, in the bus rack A, one cycle of data reading ends normally. On the other hand, expander board 5A
Bus slave means 7A makes the bus master means 6B of the expander board 5B of the bus rack B make a bus use request, and when the expander board 5B obtains the bus use right, the address signal (ADD) and address strobe signal (AS *), data strobe signal (DS
*) Flows to the system bus 4B of the bus rack B. However, since the memory board X does not exist in the bus rack B, one cycle of data reading ends in the bus rack B without outputting the data signal (DATA) and the data acknowledge signal (DTACK *). This is V
This is a violation of the ME bus standard and upsets the operation of the bus arbiter of the system controller 1B of the bus rack B.

Therefore, the present invention provides a bus rack A of its own.
The board having the address assigned to the slave means 6A (6B) of the bus expander board 5A (5B) inserted into the slot (B) is transferred to its own bus rack A (B).
It is an object of the present invention to provide a bus expander that does not violate the VME bus standard even if it is inserted and connected to a slot of a bus rack, so that an empty slot of a bus rack can be used effectively.

[0013]

An expander of a bus system provided by the present invention is a bidirectional bus rack having a system bus for arbitrating a bus use request of a plurality of boards connected to a common bus line by a system controller. In order to allow mutual access between the board connected to one system bus and the board connected to the other system bus,
Two expander boards to be inserted are connected by an address line, a data line, an access request line, and the like. The expander board is assigned an address of a system bus to which the other expander board is connected. A bus slave means for issuing an access request to the other expander board through the access request line when receiving an access to this address on its own system bus, and an access request from the other expander board through an access request line. When a bus expander having a bus master means for issuing an access request to its own system bus when receiving it, when accessing the other system bus from one system bus, the bus master means of the other expander board is Get usage rights Open by the signal obtained when he,
A gate circuit for supplying a data acknowledge signal and a bus error signal generated on one system bus to a bus line of the other system bus is provided bidirectionally between two expander boards.

In the bus expander, even if the board to be accessed is not inserted into the bus rack at the original insertion position determined by address assignment to the expander board, but is inserted into the bus rack to be accessed, One cycle of access on the bus rack side, which is the original insertion position, can be terminated by a data acknowledge signal or a bus error signal sent from the accessing bus rack without violating the bus standard. Therefore, when there is no empty slot in one bus rack into which a board is to be inserted, the board can be inserted into an empty slot in the other bus rack, and the empty slot in the bus rack can be used effectively.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a connection circuit for connecting two expander boards 5A and 5B of a bus expander according to the present invention, with an improved portion.

The connection circuit includes a bus use right detection circuit 9 which outputs when the bus master means 6A (6B) of the expander board acquires the bus use right in its own system bus, and a bus use right detection circuit 9 from the system bus of one bus rack. Bidirectional gate circuits 10A and 10B for controlling the opening and closing of a bus acknowledge signal flowing to the system bus of the other bus rack
It is composed of

The bus use right detection circuit 9 is provided with a bus master means 6A (6) of the bus expander board 5A (5B).
B) is for determining whether or not the system controller 1A (1B) has permitted use of the bus in response to a bus use request issued to its own system bus 4A (4B). 5A and 5B have each independently. The bus use right detection circuit 9 in FIG. 1 shows these in one block, and outputs a high level when one of the bus master means 6A, 6B acquires the bus use right. The bus use right detection circuit 9
May be provided separately for exclusive control of opening and closing of the gate circuit 10A or the gate circuit 10B.

The gate circuit 10A is used when accessing the bus rack B from the bus rack A. The data acknowledge signal (DTA) of one bus rack A is used.
CK *) is received by the input buffer 11A, and the three-terminal NA
The data is supplied from the output buffer 13A to the data acknowledge signal line of the other bus rack B via the ND gate 12A.

The gate circuit 10B includes a bus rack B
, An input buffer 11B, a three-terminal NAND gate 12
B, and the data acknowledge signal (DTACK *) of the bus rack B is supplied to the data acknowledge signal line of the bus rack A via the output buffer 13B.

The three-terminal NAND gates 12A and 12B are used to exclusively open these gates. That is, each of the three-terminal NAND gates 12A (12B) is opened under the condition that the bus usage right detection circuit 9 outputs a high level and the other three-terminal NAND gate 12B (12B) is not opened,
Pass the data acknowledge signal.

The gate circuits 10A and 10B are for data acknowledge signals.
In order to allow a bus error signal to flow bidirectionally between B, the same ones as the gate circuits 10A and 10B are independently provided in parallel (not shown). This is because when the access to the board to be accessed is inserted into the bus rack (for example, A) and the access to the board fails, and the processing is performed by the bus error signal, the other bus rack (for example, B) is also used. If a bus error signal is not supplied, the above V
This is because a problem that violates the ME bus standard remains.

The data access when the circuit of FIG. 1 is employed will be described with reference to the operation waveform diagram of FIG. As shown in FIG. 7, a memory board X having an address assigned to another bus rack B by the bus expander board 5A.
Into the own rack A, and the CPU of the rack A
It is assumed that data is read from the memory board X on the board 2A. The CPU board 2A is a bus rack A
An address (ADD) signal, an address strobe signal (AS *), and a data strobe signal (DS *) are issued to the system bus 4A. In response to this, the memory board X outputs a data signal (DATA) and a data acknowledge signal (DTACK *) to the system bus 4A. In the bus rack A, one cycle of data reading ends normally.

On the other hand, the address signal (ADD) and address strobe signal (AS) generated by the CPU board 2A
*), The data strobe signal (DS *) is also output to the system bus 4B of the bus rack B after the bus master means 6B of the expander board 5B has acquired the right to use the bus. Since the board X does not exist in the bus rack B, unless some other signal is supplied from the other,
The data read (DATA) and the data acknowledge signal (DTACK *) are not output and the data read 1
The cycle ends, and the VME bus standard is violated.

However, according to the present invention, when the bus master means 6B of the expander board 5B acquires the bus use right, the bus use right detection circuit 9 and the gate circuit 10A cause the bus board A to transmit data and data generated by the memory board X in the bus rack A. An acknowledgment signal (DTACK *) is supplied to the bus acknowledgment signal line of the bus rack B. Therefore, one access cycle can be completed in a manner that satisfies the VME bus standard.

When data reading of the memory board X fails in the bus rack A, the bus error signal is supplied to the bus error signal line of the bus rack B, thereby satisfying the VME bus standard. .

As shown in FIG. 6, when a relay bus rack E is used, a data acknowledge signal and a bus error signal are supplied through the relay bus rack E.

As described above, the fact that the empty slots of each bus rack can be used without restrictions on addresses is particularly useful in the short I / O space (FFFF0000 to FFFF0000) having a narrow address space.
This is highly useful in that when a large number of interface boards using FFFFFFFF) must be used, the number of additional bus racks can be minimized.

[0028]

According to the present invention, when a computer system is constructed by connecting a plurality of bus racks by a bus expander, a board is assigned to an empty slot of each bus rack without being restricted by the address assignment of the bus expanders. Can be inserted. Therefore, the number of bus racks can be minimized, and when the number of boards needs to be increased, the number of bus racks does not need to be increased in many cases, and space and cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a connection circuit diagram of an expander board improved according to the present invention.

FIG. 2 is a block diagram showing an example of a configuration of the connection circuit of FIG. 1 in which a board X having an address assigned to another bus rack B is inserted into its own bus rack A;
Each bus rack A, B explaining that it does not violate the standard
Access signal waveform diagram

FIG. 3 is a view showing bus racks A and B connected by a bus expander;

4 is an access signal waveform diagram in each of the bus racks A and B in the connection of FIG.

FIG. 5 is a diagram showing a state in which a plurality of bus racks are mutually connected by a bus expander;

FIG. 6 is a diagram showing a state in which a plurality of bus racks are connected using a relay bus rack in order to reduce the number of bus expanders used;

FIG. 7 is a connection diagram showing a state in which a memory board X having an address assigned to another bus rack B is inserted and connected to its own bus rack A;

FIG. 8 is a diagram illustrating bus racks A and B for explaining that the use of a conventional bus expander in the connection of FIG. 7 results in a violation of the VME bus standard in another bus rack B;
Access signal waveform diagram

[Explanation of symbols]

 A bus rack B bus rack 1A, 1B system controller 2A, 2B CPU board 3A, 3B memory board 4A, 4B system bus 5A, 5B expander board 6A, 6B bus master means of expander board 7A, 7B bus slave of expander board Means 8A, 8B Connection line of expander board 9 Bus use right detection circuit 10A, 10B Gate circuit

Claims (1)

[Claims] A bus rack provided with a system bus that arbitrates a bus use request of a plurality of boards connected to a common bus line by a system controller;
In order to enable mutual access between a board connected to one system bus and a board connected to the other system bus, two expander boards respectively inserted into slots of two bus racks are assigned address lines, The expander board is connected by a data line, an access request line, or the like, and the expander board is assigned an address of a system bus to which the other expander board is connected, and performs access to this address on its own system bus. A bus slave means for issuing an access request to the other expander board through the access request line when receiving the access request, and an access request to its own system bus when receiving an access request from the other expander board through the access request line. Bus expert having bus master means When one system bus accesses the other system bus, the bus is opened by a signal obtained when the bus master means of the other expander board acquires the right to use the bus, and a data acknowledge generated on one system bus is performed. A system bus expander characterized in that a gate circuit for supplying a signal and a bus error signal to a bus line of the other system bus is provided bidirectionally between two expander boards.