JPH11242057A - Digital tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a digital tester that automates the judgment of AC/DC for an input signal and the switching of AC/DC of a measurement system and to achieve a highly responsive measurement and also to handle the change in an input potential as that in a potential region for measuring a pulse width. SOLUTION: A potential region discrimination part 40 outputs whether there is an input potential VIN into either of potential regions A, B, and C that are divided by reference voltages +1V and -1V as a potential region signal Sa, and a start signal generation part 50 detects that the input potential VIN exceeds a reference potential and is switched to a different potential region from the potential region signal Sa and outputs a start signal S1. After this, a stop signal generation part 60 detects that the input potential VIN exceeds the first exceeded reference potential and the potential region is switched from the potential region signal Sa and outputs a stop signal S2. A clocking part 70 measures the pulse width of an input signal based on the start signal S1 and the stop signal S2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital tester, a technique for determining whether an input signal of the digital tester is AC or DC, a technique for measuring a pulse width relative to an input potential of the digital tester, and a structure of the main body of the digital tester. About technology.

[0002]

2. Description of the Related Art A digital tester as a circuit meter is composed of a voltmeter, an ammeter, an ohmmeter, and the like.
With a wide measurement range and easy handling,
It is widely used for failure detection and repair of electronic devices.

Here, the measurement system of a digital tester is generally switched between an AC signal and a DC signal, and a digital tester is used to switch the measurement system from outside. A mode change switch is provided.

In using the digital tester, a probe having a measuring terminal at one end is used, and the test lead connected to the other end is connected to the digital tester main body. When carrying the digital tester, the digital tester body is housed in an outer case, and the probe is housed using the gap.

[0005]

However, in the conventional digital tester, in order to switch the measurement system to the AC side or the DC side, it is necessary to determine whether the voltage input by the user based on the circuit configuration or the like is AC. There is a first problem that it is inconvenient for those who do not have electrical knowledge because it is necessary to recognize whether the current is direct current.

In view of the above-mentioned first problem, a first object of the present invention is to provide an automatic and high responsiveness determination of an AC / DC judgment on an input signal and switching of a measurement system to an AC side or a DC side. An object of the present invention is to realize a digital tester that can be performed by using a digital tester.

On the other hand, as the circuit configurations of various devices are being digitized, there are many opportunities to measure the pulse width to check the circuit configurations. Does not have a pulse width measurement circuit, which is inconvenient for digital circuit designers. In other words, measuring the pulse width requires a circuit or relay circuit that detects the rising and falling of the pulse by time-dividing the input signal and sequentially comparing the changes. The reason for this was that it could not be mounted.

In view of the above-mentioned second problem, a second object of the present invention is to determine a change in input potential as switching of a potential region, thereby achieving a pulse width with a simple configuration and high reliability. It is to realize a digital tester capable of measuring the temperature.

Further, in the conventional digital tester, it is necessary to store the probe together with the digital tester main body inside the outer case every time the digital tester is carried. The third, which is not easy to use because the storage is separate
There is a problem. Also, when storing the probe inside the outer case, the test lead is often wound around the grip portion of the probe and stored, and when stored in this state,
When using a digital tester, there is also the inconvenience that test leads must be rewound before use.

In view of the above third problem, a third object of the present invention is to improve the structure of the digital tester main body so as to provide a digital tester having improved usability such as easy handling on the probe side. Is to make it happen.

[0011]

Means taken to solve the first problem in the digital tester according to the present invention are as follows: As shown in the claim correspondence diagram in FIG. High-speed operable high-speed A / D conversion means (high-speed A / D conversion unit 35) for digitizing input signal 90 and outputting it as AC / DC determination signal 91
And the level of the input signal is compared with the DC determination range defined by the positive threshold and the negative threshold based on the AC / DC determination signal 91, and the level of the input signal is within a predetermined comparison period. When the input signal exceeds both the positive side and the negative side from the DC determination range, the input signal is determined to be AC, and an AC / DC determination unit (AC / DC determination unit 36) that issues a determination signal 92 corresponding to AC and DC. ) And the judgment signal 9
And a switching unit (switching unit 32) for switching the measurement system between the AC side and the DC side based on the above.

Here, the AC / DC determination means (AC / DC determination unit 36) compares the level of the input signal with the DC determination range at least twice with a predetermined time interval, and in any comparison period, the input signal 90. If the level of the input signal 90 exceeds both the positive side and the negative side from the DC determination range within a predetermined period, it is preferable that the input signal 90 is determined to be AC and a determination signal 92 is issued.

The switching means (switching unit 32) normally holds the measurement system on one of the AC side (the rectifying and smoothing circuit 34 side) and the DC side (the input path 33 side). In addition, when an input signal to be set to the other side of the measurement system is input, the AC / DC determination unit (AC / DC determination unit 36) switches the measurement system from the normal side to the other side. Is preferably issued as a determination signal 92. In this case, the switching means (switching unit 32) preferably sets the measurement system to the DC side as one side and sets the measurement system to the AC side as the other side in a normal state.

Further, a double-integrated high-voltage type A / D conversion means for digitizing an input signal and outputting it as a measurement signal in a state where the measurement system is set on the AC side or the DC side corresponding to the input signal. Resolution A / D conversion means (high resolution A / D
When the D conversion unit 37) is used, the input current is switched between alternating current and direct current to the double integration type high resolution A / D conversion means (high resolution A / D conversion unit 37). It is preferable to provide a reset signal generating means (reset signal generating unit 38) for outputting a reset signal 93 when necessary.

Means taken in the digital tester according to the present invention to solve the second problem is shown in FIG.
As shown in the block diagram and the explanatory diagram corresponding to the claims in (a) and (b), the input region V _IN has a potential region defined by at least two reference potentials, for example, +1 V and -1 V (potential regions A, A potential region discriminating unit (potential region discriminating unit 40) for discriminating which potential region is present in the potential region B and the potential region C) and outputting a result of the decision as a potential region signal Sa; Based on the potential region signal Sa output from the means, it is detected that the input potential V _IN has switched to a different potential region beyond any one of the reference potentials, and the pulse width measurement is started. Start signal generating means (start signal generating section 50) for outputting a start signal S1 of the following, and output from the potential area determining means after the start signal generating means outputs the start signal S1. Reference potential is the input potential V _IN based on the potential domain signal Sa exceeds at least the first which, namely, detects that the switched potentials region again beyond the reference potential beyond when start signal S1 is output A stop signal generating means (stop signal generating unit 60) for outputting a stop signal Sb to end the pulse width measurement, and a start signal Sa
And a time measuring means (time measuring unit 70) for measuring a period from when is output to when the stop signal Sb is output.

Here, a forced stop command signal generating means (forced stop command signal generating means) for outputting a forced stop command signal St for forcibly outputting a stop signal Sb to the stop signal generating means based on an external operation. It is preferred to provide a part 80).

Means taken to solve the third problem in a digital tester according to the present invention is to provide a digital tester main body, a measurement terminal portion at one end side, and a measurement terminal portion at the other end side. In a digital tester having a probe connected to a test lead conductively connected to a tester main body side, a probe storage groove capable of storing a probe and an outer periphery of the probe stored in the probe storage groove are provided on side surfaces of the digital tester main body. And a drop-off prevention mechanism for preventing the probe from dropping out of the probe storage groove by engaging with the groove. Here, as the falling-off preventing mechanism, for example, an engagement elastic contact portion that projects inward from both side walls forming the probe housing groove and elastically contacts the outer periphery of the probe in the probe housing groove can be used.

In the present invention, by providing a probe housing groove or a test lead housing groove connected to the probe housing groove on any side surface of the digital tester main body, the digital tester main body is rotated around the side surface thereof. It is preferable that the probe can be accommodated in the probe accommodating groove in a state where the set test lead is accommodated in the test lead accommodating groove and the probe accommodating groove.

Further, a portion of the side wall forming the probe housing groove where the measuring terminal portion of the probe housed in the probe housing groove is located is housed in the probe housing groove from the open edge toward the inside. It is preferable to form a measurement terminal portion exposing recess for exposing the measurement terminal portion of the probe to the exposed state. The concave portion in the present invention means a shape having an outer shape line inside the outer shape contour line, and is not necessarily limited to a shape having a large concave shape.

Furthermore, the portion of the both side walls forming the probe housing groove where the grip portion of the probe housed in the probe housing groove is located is housed in the probe housing groove from the open edge toward the inside. It is preferable that a concave portion for taking out the probe be formed so that the grip portion is exposed.

In the present invention, the rotary switch for measuring mode selection provided on the upper surface of the digital tester body preferably has a small protrusion for preventing slippage on the surface side.

In this case, small projections are formed in the circumferential direction at a predetermined pitch near the outer peripheral edge of the rotary switch for measurement mode selection, and the formed pitch is provided on the outer periphery of the rotary switch for measurement mode selection. It is preferable to dispose it so as to be different from the formation pitch of the measurement mode selection index.

Further, it is preferable that an upper surface side recess is formed on the upper surface side of the digital tester main body from the formation region of the measurement mode selecting rotary switch to the upper surface side edge of the digital tester main body.

[0024]

In the digital tester according to the present invention, when a signal is input to the digital tester, the high speed A / A
The D conversion means digitizes the input signal and outputs it as an AC / DC determination signal. Based on the AC / DC determination signal, the AC / DC determination means determines that the level of the input signal is positive within a predetermined period. It is determined whether or not the current value exceeds the DC determination range defined by the value and the negative threshold value on either the positive side or the negative side. Here, the AC / DC determination means determines that the input signal is AC when the level of the input signal exceeds both the positive side and the negative side from the DC determination range within a predetermined period, and outputs the determination signal. The switching means switches the measurement system between the AC side and the DC side based on the determination signal. That is, if the level of the input signal exceeds the DC determination range within a predetermined time period to both the positive side and the negative side, the input signal is determined to be AC. If only one of the negative side and the negative side is exceeded, it is determined that the current is direct current, and the measurement system is switched by the switching means. Therefore, in the digital tester according to the present invention, since the measurement system is automatically switched in response to the input signal, the input can be made without knowing whether the input signal to the digital tester is AC or DC. It can be measured under the conditions corresponding to the signal. A high-resolution A / D conversion means for digitizing an input signal and outputting it as a measurement signal is required. However, the A / D conversion means for outputting an AC / DC determination signal has a high resolution. Regardless of the height, the high-speed A / D conversion means is employed to obtain only the high operation speed, so that the switching between the DC side and the AC side with respect to the measurement system is speeded up, and the input signal High responsiveness.

On the other hand, in another mode of the digital tester according to the present invention, when a signal is input, first, the potential region discriminating means (potential region discriminating section 40) sets the input potential V _IN to the potential region A, the potential region It is determined which of the potential area B and the potential area C it is in, and the result of the determination is output as a potential area signal Sa. In this state, the input potential V _IN
If the voltage does not exceed the reference potential and remains in the same potential area even if the voltage changes, the same potential area signal Sa is still output from the potential area determination means, so that the start signal generation means (start signal generation unit 50) Does not output the start signal S1. On the other hand, when the input potential V _IN exceeds the reference potential and the potential area changes, the potential area signal Sa output from the potential area determination means changes, and this change in the potential area is determined by the start signal generation means. Is detected, the start signal generation means outputs a start signal S1 to start measuring the pulse width. When the potential region changes after the input potential V _IN exceeds the reference potential which has first exceeded, the potential region signal Sa output from the potential region determining means changes, and this change in the potential region is stopped. When the generating means (stop signal generating unit 60) detects, the stop signal generating means outputs a stop signal S2 to end the pulse width measurement. Then, the timer means (timer 70) measures a period from the output of the start signal S1 to the output of the stop signal S2 as a pulse width.

In the digital tester according to the present invention, the test leads are connected to the main body of the digital tester so that the main body of the digital tester and the measuring terminal are electrically connected to each other. The voltage value between the measurement terminals is measured based on the information inputted. On the other hand, in the digital tester according to the present invention, when the probe is housed inside the probe housing groove formed on the side surface of the digital tester main body, a fall prevention mechanism using an elastic contact portion for engagement or the like is provided therein. As a result, the probe does not fall out of the probe housing groove, so that the digital tester can be carried in this state. Therefore, there is no need to store the probe in an outer case every time the digital tester is carried, and when using the digital tester,
Usability is good because the probe can be removed from the probe housing groove and used as it is.

[0027]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

[Internal Configuration of Digital Tester] The digital tester 1 of the present embodiment has various functions in the digital tester main body 10 that correspond to each measurement mode, which is a part of a function equivalent to NJU9210 manufactured by New Japan Radio Co., Ltd. And a measuring circuit such as a resistance measuring circuit having a selector and a buffer amplifier for selecting a reference potential and a reference resistance for resistance measurement, and automatically determining whether an input signal is alternating current or direct current to measure the measuring system. Is automatically switched, and the voltage value of the input signal and the like are measured while the measurement system is switched by the AC / DC determination switching unit.

That is, as shown in the block diagram of FIG. 4, a probe 20a,
The probe 20a on the positive side of the probe 20b has a pull-down resistor 31 and a switching unit 32 connected to the subsequent stage of the pull-down resistor 31. Has a rectifying / smoothing circuit 34 connected in parallel. Here, the rectifying and smoothing circuit 34
Has a rectifier circuit for full-wave rectification when an alternating current is input, and a smoothing circuit for smoothing the input.
Is an input stage (measurement system) when is an alternating current. On the other hand, the input path 33 is an input stage (measurement system) when the input signal 90 is DC. Here, the switching unit 32
Are switches 3 for the DC terminal 321 on the input path 33 side and the AC terminal 322 on the rectifying and smoothing circuit 34 side.
In the switching section 32, the switch 323 is connected to the DC terminal 321 as shown by a solid line in a normal state where no signal is input. Further, a high-resolution A / D converter 37 for digitizing the input signal 30 and outputting it as a measurement signal 35 to a measuring unit (not shown) is provided at the subsequent stage of the switching unit 32. The / D converter 37 is a double integration type A / D converter with a high resolution of 3200 counts, and is used for measuring the input signal 90.

The digital tester 1 of this embodiment also has a high-speed A / D converter 35 on the subsequent stage of the switching unit 32. The high-speed A / D converter 35 has a sequential comparison with a resolution of 64 counts. Although it is a type A / D converter, it can operate at a high speed although the resolution is lower than the resolution of the high resolution A / D converter 37. Here, the high-speed A / D converter 35 converts the input signal 90 into a digital signal at a high speed and outputs the digital signal to the AC / DC determination unit 36 as an AC / DC determination signal 91. The AC / DC determination unit 36 is configured by a microcomputer, and determines whether the input signal 90 is based on the AC / DC determination signal 91 output from the high-speed A / D conversion unit 35 based on the operation program stored in the microcomputer. It is determined whether the switching is DC or not, and the switching unit 3
2 is controlled. That is, when the AC / DC determination unit 36 determines that the input signal 90 is DC, the AC / DC determination unit 36 keeps the switch 323 connected to the DC terminal 321 side with respect to the switching unit 32 (shown by a solid line). While the determination signal 92 is output so as to hold the input signal 90, the input signal 90 is determined to be AC.
A switching command signal (judgment signal 92) for switching to the state of connection to the side (to the state shown by the broken line) is issued. Specifically, the AC / DC determination unit 36 sets the level of the input signal 90 to a positive value in a DC determination range (+ 3V to -3V) defined by 3V (+ 3V, -3V) as a threshold value within a predetermined comparison period. The input signal 90 is determined to be AC when it is determined that the input signal 90 has exceeded either the negative side or the negative side. If the input signal 90 does not exceed one of the threshold voltages of +3 V and -3 V, the input signal 90 is switched to AC. Even if it is, it is determined as a DC voltage. Here, the AC / DC determination unit 36 compares the level of the input signal 90 with the DC determination range (+3 V to −3 V) twice at predetermined time intervals, and in any comparison period, When the input signal 90 is in the DC determination range (+
When the input signal 90 exceeds 3 V to -3 V) on both the positive side and the negative side, the input signal 90 is determined to be AC.

Further, the digital tester 1 of this embodiment outputs a reset signal 93 to the high resolution A / D converter 37 when the input current is switched between AC and DC. The high-resolution A / D converter 37 converts the arithmetic processing to the reset signal 9 by the reset signal 93 output from the reset signal generator 38.
3, the process returns to the initial state, and the process for the new input signal 90 can be started at an early stage.

Such a digital tester has a function corresponding to NJU9210 manufactured by New Japan Radio Co., Ltd.
A digital tester IC having high-speed A / D conversion means (high-speed A / D conversion section 35) capable of high-speed operation and switching means (switching section 32) for switching a measurement system between an AC side and a DC side. Comparing the level of the input signal with a DC determination range defined by a positive threshold value and a negative threshold value based on the AC / DC determination signal 91, so that the input signal level falls within a predetermined comparison period. AC / DC determination means (AC / DC determination unit 36) that determines that the input signal is AC when it exceeds both the positive side and the negative side from the determination range and issues a determination signal 92 corresponding to AC and DC. Can be realized by adding

On the other hand, in the digital tester 1 of this embodiment, an NJU manufactured by
In addition to having a measuring circuit such as a resistance measuring circuit including a selector and a buffer amplifier for selecting a reference potential and a reference resistance for resistance measurement, corresponding to each measurement mode, which is a part of a function equivalent to 9210. And a pulse width measurement circuit for measuring the pulse width of the input signal. The pulse width measurement circuit sets the mode auxiliary selection with the measurement mode selection rotary switch 13 set to the index 14c for selecting the frequency measurement. It operates by pressing the button 12a. This pulse width measurement circuit has a schematic configuration in which the input potential V _IN is equal to two reference potentials as shown in the block diagrams of FIGS. 9 (a) and 9 (b) and the explanatory diagram for explaining the operation principle thereof. Potential region determining unit 40 which determines which of the potential regions A, B, and C is defined by +1 V and -1 V as the potential region, and outputs the determination result as potential region signal Sa.
The pulse width is measured based on the potential area signal Sa output from the potential area determination section 40. That is, in the digital tester 1 of the present example, the input potential V
_It has a start signal generation unit 50 that detects that _IN has exceeded the reference potential and switches the potential region and outputs a start signal S1 to start measuring the pulse width. On the other hand, the start signal generation unit 50 outputs the start signal S1.
Is output, the potential width is detected based on the potential region signal Sa output from the potential region determination section 40, and the potential region is switched again after the input potential _VIN exceeds the first reference potential again. And a stop signal generation unit 60 that outputs a stop signal S2 for ending the measurement of. Therefore, in the timer 70, the counter 71 measures the number of clocks from when the start signal S1 is output to when the stop signal S2 is output, and the pulse width can be measured.

Next, the circuit configuration and functions of the potential region determination section 40, start signal generation section 50, stop signal generation section 60, etc. will be described in detail with reference to FIGS.

FIG. 10 is a circuit block diagram of a pulse width measurement circuit configured in the digital tester of this embodiment, and FIG.
FIG. 4 is a timing chart illustrating waveforms of signals input and output in the pulse width measurement circuit.

In these figures, the potential region discriminating section 40
A first comparator 411 that compares the first reference potential +1 V with the input potential V _IN and outputs a signal “H” when the input potential V _IN is more positive than +1 V; A second comparator 412 that compares the second reference potential -1V with the input potential V _IN and outputs a signal “H” when the input potential V _IN is a potential more negative than −1 V is used. Have. Here, the output from the first comparator 411 is
12 is input to an AND circuit 421 together with the inverted output of the output from the signal line 4 when the input potential V _IN is a potential more positive than +1 V (potential region B).
The signal “H” is output to 31. Also, the first comparator 4
The output from the comparator 11 and the output from the comparator 412 are input to the NOR circuit 422. From the NOR circuit 422, when the input potential V _IN is in the range of +1 V to -1 V (potential region A), the signal line 432 is output. Output the signal "H". Further, the output from the second comparator 412 is input to the AND circuit 423 together with the inverted output of the output from the first comparator 411. From the AND circuit 423, the input potential _VIN is more negative than -1V. In the case of the potential (potential region C), the signal “H” is output to the signal line 433. Therefore, it is possible to identify in which of the potential regions A, B, and C the input potential V _IN is currently based on which of the signal lines 431 to 433 is output with “H” from the potential region determination unit 40. That is, the signal output to the signal lines 431 to 433 is the potential region signal Sa.

The start signal generator 50 is connected to the signal line 43
D latch circuit 51 to which signals from 1 to 433 are input
And the signal (region signal Sb at reset) held by D latch circuit 51 and signal lines 431 to 4
A start detection unit 53 that detects the rise or fall of the input potential V _{IN based on} the potential area signal Sa input from the control unit 33. The start detection unit 53 includes two OR circuits 541 and 542 and four AND circuits 53
1, 532, 533 and 534, while D
The CK terminal of the latch circuit 51 is connected to a pull-up reset signal generator 55. Therefore, when the reset signal R input from the reset signal generator 55 to the CK terminal of the D latch circuit 51 switches from “H” to “L” based on an external operation, the signal lines 431 to 433 are output.
Is held as data at the time of reset by the D latch circuit 51 as the region signal Sb at the time of resetting.
It is determined whether or not the potential region of the input potential V _IN has been switched based on the current potential region signal Sa directly input to the terminal 3. Then, when the potential region of the input potential V _IN switches, the signal “H” can be output from any of the AND circuits 531 to 534.

The start signal generator 50 has an OR circuit 56, a D latch circuit 57 and an OR circuit 58 on the subsequent stage of the start detector 53, and the signal output from the start detector 53 is D latch circuit 57 and OR circuit 5
8 and can be input to the AND circuit 59 as an inverted signal, and the signal output from the start time detection unit 53 is input to the AND circuit 59 via the OR circuit 56. I have. Here, the AND circuit 59
Is output to the CK terminal of the D latch circuit 57. A reset terminal of the D latch circuit 57 has a reset signal R from the reset signal generator 55.
When the reset signal R switches from “H” to “L”, the D latch circuit 57 is reset, and “L” is output from the OR circuit 58 to the subsequent stage. In this state, when the signal “H” is output from any of the AND circuits 531 to 534 of the start detection unit 53, the signal input to the CK terminal of the D latch circuit 56 becomes “L”. From “H” to “H”, and the signal “H” from the start detection unit 53 is held in the D latch circuit 57 as the start region signal Sc. For this reason, the clock unit 7 on the subsequent stage from the OR circuit 58
The start signal S1 output to 0 rises from “L” to “H”, and the rise of the start signal S1 defines the start time of the pulse width measurement in the timer 70 as a substantial start signal. When the start signal output from the OR circuit 58 is switched to “H” in the timer 70, the signal output from the stop signal generator 60 is “L” and the inverted signal And circuit 6
6 has been entered. Accordingly, the count signal C output from the AND circuit 66 to the counter 71 becomes “H”, and the internal clocking gate of the counter 71 becomes “H”.
It is possible to start counting the clock signal.

Further, the stop signal generator 60 has a stop detector 61 to which signals from the D latch circuit 57 and the signal lines 431 to 433 are input.
Has two OR circuits 631, 632 and four AND circuits 621, 622, 623, 624. In the stop time detecting section 61, when any of the signals input from the D latch circuit 57 is “L”, the signal “L” is output to the OR circuit 64 and any of the signals output from the D latch circuit 57 is output. Signal (start time area signal Sc) is “H”, the potential area of the input potential V _IN at the start of the pulse width measurement, which is meant by the start time area signal Sc, and the input from the signal lines 431 to 433 When there is no change from the potential region of the input potential V _IN that is indicated by the current potential region signal Sa, the signal “L” is output to the OR circuit 64. On the other hand, there is a change between the potential region of the input potential V _IN defined by the start region signal Sc and the potential region of the input potential V _IN defined by the potential region signal Sa. _When the potential region is switched after _IN exceeds the reference potential that has at least initially exceeded, the signal “H” is output to the OR circuit 64. For this reason, the OR circuit 64
, The signal input to the CK terminal of the D latch circuit 65 switches from “L” to “H”, and the signal “H”, which is a 5 V potential from the power supply, is input to the timer 70 as the stop signal S2. Has become.

Here, when the signal output from the D latch circuit 65 switches from “L” to “H” in the timer 70, the signal is inverted and input to the AND circuit 66, and the output from the AND circuit 66 is output. Switches to “L”. For this reason,
The count signal C output from the AND circuit 66 is "L"
As a result, the counting of the clock signal by the counter 71 is stopped, and the period obtained from the number of clocks counted during the period is displayed on the display unit 11 of the digital tester 1 as the pulse width.

In the digital tester 1 of this embodiment, a pull-up forced stop command signal generator 80 is provided for the OR circuit 64 of the stop signal generator 60, and the forced stop command is generated by an external operation. When the “H” forced stop command signal St is output from the signal generation unit 80 to the OR circuit 64, the signal “H” is input to the D latch circuit 65, and the D latch circuit 65 stops the “H”. Since the signal S2 is output and the output from the AND circuit 66 is switched to "L", the counting of the clock signal in the timer 70 is forcibly stopped.

[Usage of Digital Tester] In the digital tester 1 having such a configuration, the test leads 22a and 22b are connected to the digital tester main body 10 so that the digital tester main body 10 and the measuring terminals 21a and 21b are connected. Are electrically connected to each other, and in this state, the measuring terminals 21a and 21b are electrically connected to an electric circuit or the like to measure a voltage value between the measuring terminals 21a and 21b.

Here, resistance measurement and the like are performed by a well-known method. Therefore, referring to FIG. 5 and FIG. Switching unit 32, high-speed A / D conversion unit 3
5. Only operations performed in the AC / DC determination unit 36 and the like will be described. The switching operation of the AC / DC determination of the digital tester 1 is performed based on a program stored in a microcomputer including the AC / DC determination unit 36 and the like. The AC / DC determination switching operation will be described with reference to a flowchart showing the switching operation and a flowchart as a subroutine showing an operation of comparing the input signal 90 with the threshold shown in FIG.

Note that, until the input signal 90 is input, that is, in a normal state, the switching unit 32 operates the switch 3
23 is connected to the DC terminal 321 side.

First, in step ST1, when the input signal 90 is input to the digital tester 1 via the measuring terminal 21a of the probe 20a, the AC / DC as a threshold for determining the AC / DC of the input signal 90 is set. +3 V is set in the determination unit 36.

Next, in step ST2, the input signal 90 is compared with the threshold value (+3 V) based on the AC / DC determination signal 91. In this process, after the start is performed in step ST51 of the flowchart shown in FIG. 6, in step ST52, 60 is set as the repetition number index (n).

Next, in step ST53, the absolute value of the input voltage (input signal 90) at this time is compared with the absolute value of +3 V set as the threshold, that is,
A comparison is made between the input voltage at time t1 in the waveform diagram shown in FIG. 7 and +3 V set as the threshold value. Here, when it is determined that the input voltage is a voltage higher than +3 V as at time t3, step ST
After the over flag indicating this is set at 54, the process returns (step ST55). On the other hand, if it is determined that the input voltage is lower than +3 V as at time t1, the process proceeds to step ST5.
At 6, the overflag is reset.

Then, in step ST57, the repetition number index becomes 59 by dividing 1 from 60.

Next, in step ST58, it is determined whether or not the index of the number of repetitions is 0. Here, since the index of the number of repetitions is not 0, it is determined that the comparison period has not elapsed, and the process returns to step ST53.

Such an operation (step ST53 to step ST58) is performed at time t in the waveform diagram shown in FIG.
As a comparison between the input voltage at 1, t2, t3,... T60 and +3 V set as a threshold value, the process is repeated every 0.366 msec until the repetition number index becomes 0, and this process is repeated for 60 cycles. About 2
If it is determined that the input voltage is higher than +3 V during 0 msec (comparison period), step ST
At 54, after the over flag indicating that is set, step ST4 of the flowchart shown in FIG.
Is returned (step ST55). Therefore, 20
An input signal 90 having a half cycle of msec or more, that is, an input signal 90 of 25 Hz or less, is not determined as an alternating current.

On the other hand, if the input voltage is not determined to be higher than +3 V, and if the repetition index is determined to be 0 in step ST58, the over flag Are returned to step ST4 of the flowchart shown in FIG. 5 (step ST55).

In step ST4, it is determined whether or not the overflag is set. If the overflag is set, the processing after step ST5 is performed. If not, in step ST9, it is determined that the input current is DC, and the AC flag (determination signal 92) is reset.

On the other hand, when the over flag is set, it is determined by the processing after step ST5 whether or not the input voltage is lower than -3V. That is, even if the input voltage is DC, +3
This is because a DC voltage of V or more may be input, and if the input voltage is AC, a voltage of −3 V or less (a negative voltage having an absolute value of 3 V or more) should be input.

Accordingly, in step ST5, after -3V is set as the threshold, in step ST6, the input voltage (input signal 90) is compared with -3V as the threshold. In this comparison, as in step ST3, the processing of steps ST51 to ST58 in the flowchart shown in FIG. 6 is performed. That is, step S
At T52, 60 is set as the repetition number index (n), and the absolute value of -3V set as the threshold value is compared with the absolute value of the input voltage. If it is determined that
At T54, the process returns after the over flag indicating that is set (step ST55). On the other hand, even if the input voltage is compared with -3V set as the threshold value and the input voltage is performed 60 times, if the input voltage lower than -3V is not input during that time, the over flag is set. Are returned to step ST7 of the flowchart shown in FIG. 5 (step ST5).
5).

Also in this step ST7, it is determined whether or not the over flag is set. If the over flag is set, the process A is performed, whereas if the over flag is not set. In
In step ST9, the AC flag is reset assuming that it is DC.

In the process A, the same processes as those in the steps ST2 to ST4 are repeated, and when the over flag is set, the process B is performed, whereas when the over flag is not set. In
In step ST9, the AC flag is reset assuming that it is DC. In the process B, step ST5
Steps ST7 to ST7 are repeated, and if the overflag is set, the process proceeds to step ST8.
When the AC flag is set and the over flag is not set, step ST9
Then, the AC flag is reset assuming that it is DC.

Here, as processing A and processing B, processing of step ST2 to step ST4 and step ST
The reason why the processing of Step 5 to Step ST7 is repeated twice is that, as shown in FIG. 8A, after a voltage lower than -3V is input, a DC voltage higher than + 3V is input. In this case, if the input signal 90 is a direct current, it is erroneously recognized as an alternating current if the determination is made only based on the determination result in the transition period. Similarly, FIG.
As shown in FIG. 7, even when a DC voltage lower than -3 V is input after a voltage higher than +3 V is input, if the determination is made only based on the determination result in this transition period,
This is because even if the input signal 90 is DC, it is mistaken for AC.

The AC / DC determination unit 3 based on such processing
When the AC flag is reset as a result of the AC / DC determination operation in step 6, the AC / DC determination unit 36 does not output the switching command signal (determination signal 92) to the switching unit 32, and the switching unit 32 , Switch 323 to DC terminal 321
, And the input signal 90 is transmitted to the subsequent stage via the input path 33. And the input signal 9
After being converted into a digital signal by the high-resolution A / D converter 37, 0 is output as a measurement signal 95 to the measurement system.

On the other hand, when the AC flag is set, the AC / DC determining section 36 outputs a switching command signal (determining signal 92) to the switching section 32, and the switching command signal The switching unit 32 changes the state in which the switch 323 is connected to the DC terminal 321 (normal state) to the state in which the switch 323 is connected to the AC terminal 322. , High resolution A
After being converted into a digital signal by the / D converter 37, the signal is output to the measurement system as a measurement signal 95.

Here, the process returns from step ST10 to step ST1, and even during measurement,
Whether the input signal 90 is AC or DC is monitored. For this reason, even when the input signal 90 changes from AC to DC, the switching unit 32 automatically switches the switch 323 from the DC terminal 321 to the AC terminal 322. On the other hand, when the positive probe 20a is detached from the portion to be measured such as a circuit and the input signal 90 is pulled down, a DC voltage is input and A
The C flag is reset. In this case, since the AC flag is reset in the AC / DC determination unit 36, the switching unit 32 sets the switch 323 to the AC terminal 322.
Is returned to the state of connection to the DC terminal 321 side.

The reset signal generator 38 outputs the reset signal 93 to the high-resolution A / D converter 37. Therefore, the high-resolution A / D converter 37 comprises a double integral type A / D converter. Even so, the signal held by the high-resolution A / D converter 37 is reset, and the calculation is started based on the newly input signal.

[Operation of Digital Tester] In the digital tester 1 configured as described above, the test leads 2
By connecting the digital tester main body 10 to the measuring terminal portions 21a and 21b by connecting the sides of the digital tester 2a and 22b to the digital tester main body 10, the measuring terminal portions 21a and 21b are electrically connected to an electric circuit or the like in this state. By making the connection, the potential value between the measurement terminals 21a and 21b is measured. Here, since the measurement of the resistance and the like are performed by a known method, only the operation of measuring the pulse width, which is a feature of the digital tester 1 of the present embodiment, will be described with reference to FIGS. In addition,
To switch the digital tester 1 to the pulse width measurement mode, the mode auxiliary selection button 12a is pressed with the measurement mode selection rotary switch 13 set to the index 14c for selecting the frequency measurement.

Here, the change in the potential at which the pulse width is measured by the digital tester 1 is indicated by the input potential V _IN in FIG. 11, and the result of the determination of the potential region is indicated by the potential region signal Sa from the time t1 as shown in FIG. In the period up to time t4,
In the range of -1V to + 1V (potential region A), during the period from time t4 to time t5, the potential is more positive than + 1V (potential region B). In the range (potential region A) and after time t6, the potential changes from -1V to a negative potential (potential region C). The case where the pulse width of the pulse P in the period from the time t4 to the time t5 among the input potentials V _IN indicating such a change is measured will be described as an example. Therefore, during a period from time t1 to time t2 corresponding to a state before switching the digital tester 1 to the pulse width measurement mode, the signal “H” is output from the NOR circuit 422 of the potential region determination unit 40 to the signal line 432. On the other hand, the signal “L” is output from the AND circuits 421 and 423 to the signal lines 431 and 433. That is, the potential region signal S
a indicates that the input potential V _IN is in the potential region A.

In this state, the measurement mode selection rotary switch 13 is operated to select the frequency measurement.
At time t2, when the mode auxiliary selection button 12a is pressed, the digital tester 1 switches to the pulse width measurement mode. First, the reset signal R output from the reset signal generator 55 switches from "H" to "L". Instead, it is in the initial state (reset state). For this reason, in the D latch circuit 51, the signals of the signal lines 431 to 433 are taken into the D latch circuit 51, and the data is held as the reset-time area signal Sb. Here, of the reset-time area signals Sb input from the D-latch circuit 51 to the start-time detection unit 53, only the signal input to the AND circuit 532 is “H”.
And the signal input to the other AND circuit is “L”. However, during the period from time t1 to time t4, the current potential region signal Sa input from the signal lines 431 to 433 to the start detection unit 53 is also in a state indicating that the input potential _VIN is in the A potential region. Accordingly, the signal input from the signal line 431 to the AND circuit 532 is “L”. Therefore, all the signals output from the AND circuits 531 to 534 remain at "L". Therefore, since the signal output from the start detection unit 53 to the AND circuit 59 via the OR circuit 56 is also “L”, the start signal S1 output from the OR circuit 58 and the count signal output from the OR circuit 66 C remains at "L".

From this state, at time t4, when the input potential V _IN switches from the potential area A to the potential area B by exceeding the reference potential +1 V, the potential area determination unit 40 outputs the signal from the AND circuit 421 to the signal line 431. Signal changes from “L” to “H” while the NOR circuit 422
Changes from “H” to “L”.

The signal output from AND circuit 423 remains at "L". That is, the potential region signal S
a means that the current input potential V _IN is in the potential region B. Therefore, the AND circuit 532 is connected to the signal line 431.
Becomes "H", the AND circuit 53
2 switches from “L” to “H”. Therefore, the CK of the D latch circuit 57
The signal input to the terminal switches from “L” to “H”, the signal from the start detection unit 53 is taken into the D latch circuit 57, and the data is held as the start area signal Sc. As a result, the start signal S1 output from the OR circuit 58 to the timer 70 switches from “L” to “H”. At this time, the stop signal generator 60 outputs the start area signal S
the potential region of the input voltage V _IN which c means, while the potential region of the input potential V _IN, which means the current potential zone signals Sa match, the signal "L" is output to the OR circuit 64 Therefore, the stop signal output from the D latch circuit 65 remains “L”. Therefore, at time t4 when the start signal S1 output from the OR circuit 58 to the timer 70 switches from “L” to “H”, the AND circuit 6
The count signal C output from 6 changes from “L” to “H”, and the timer 70 starts counting clocks.

From this state, at time t5, when the input potential V _IN switches from the potential area B to the potential area A by exceeding the reference voltage +1 V (first exceeded reference voltage), the NOR circuit 422 connects to the signal line 432. The output signal is "L"
From “H” to “H”, while the signal output from the AND circuit 421 switches from “H” to “L”. In addition,
The signal output from the AND circuit 423 remains “L”. That is, the potential region signal Sa is the input potential V _IN
Is the potential region A. In contrast, D
The start area signal Sc held by the latch circuit 57 remains in a state indicating that the input potential _VIN is in the potential area B. Therefore, in the stop time detecting section 61, the signal held in the AND circuit 622 from the D latch circuit 57 is “H” and the signal line 432
, The signal input from the AND circuit 622 to the OR circuit 64 changes from "L" to "H". Therefore, the signal input to the CK terminal of the D latch circuit 65 switches from “L” to “H”, and the potential of +5 V from the power supply is taken into the D latch circuit 65 as the signal “H”, and The stop signal S2 output from the circuit 65 to the timer 70 switches from “L” to “H”. As a result, the count signal C output from the AND circuit 66 is output.
Is switched from “H” to “L”, and the clock counting in the timer 70 is stopped.

Therefore, in the timekeeping section 70, after the start signal S1 rises at the time t4 and until the stop signal S2 rises at the time t5, that is, at the time t5 after the count signal C rises at the time t4. A period corresponding to the number of clocks counted until the falling edge is displayed on the display unit 11 of the digital tester 1 as a pulse width.

Note that, as shown in FIG.
5, the input potential V _IN changes from the potential region A to the potential region C.
In the case of a waveform that falls to, for example, even if the fall is steep and it cannot be detected that the input potential V _IN has passed through the potential region B, it functions normally as follows. That is, at time t5, even if the input potential V _IN switches from the potential area B to the potential area C, the start area signal Sc held by the D-latch circuit 57 retains the input potential V _IN in the potential area B. Is present, that is, the signal input to the AND circuit 622 is held at “H”, and the signal output from the signal line 433 to the AND circuit 622 via the OR circuit 631 is “ Since the signal is switched from “L” to “H”, the signal input from the stop detection unit 61 to the CK terminal of the D latch circuit 65 is switched from “L” to “H”, and the count signal C is also normally “H”. Is switched to “L”, and the clock counting in the timer 70 is stopped. FIG.
As shown in (b) and (c), in the initial state, the input potential V _IN is in the potential area B, and thereafter, the waveform returns to the potential area B after switching to the potential area A or the potential area C. As shown in FIG. 12D and FIG. 12E, the input potential V _IN is in the potential area C in the initial state, and after the input signal is switched to the potential area A or the potential area B, The pulse width of the input signal having the waveform returning to the region C can be measured normally.

In the digital tester 1 according to the present embodiment, the forced stop command signal generator 80 capable of forcibly inputting the "H" forced stop command signal St to the OR circuit 64 of the stop detector 61 is provided. Is provided. Here, an external operation for issuing a forced stop command signal St to the forced stop command signal generation unit 80 is performed via the range selection button 12b. For example, when the pulse width of the input signal is abnormally long, if the user presses the range selection button 12b when he or she wants to interrupt the measurement of the pulse width, the state in which the start signal S1 is output (counting by the counter 71). Pressing the range selection button 12b in the middle state)
“H” as the forced stop command signal St is forcibly input to the OR circuit 64 from the forced stop command signal generator 80. Therefore, the signal “L” is sent to the OR circuit 64 forever.
Can be forcibly input to the OR circuit 64 as the signal “H”, the signal output from the D latch circuit 65 is switched from “L” to “H”, and the output from the OR circuit 66 is output. Count signal from “H” to “L”
To stop the measurement.

In the digital tester 1 of this example, when the mode auxiliary selection button 12a is pressed, the counter 7
When the range selection button 12b is pressed in this state, the pulse width measurement is started. When the range selection button 12b is pressed again, the forced stop command signal generation unit 80 sends a signal to the OR circuit 64. Since "H" is forcibly input as the forced stop command signal St, the pulse width can be measured manually.

In the digital tester 1 of this embodiment, an NJU manufactured by New Japan Radio Co., Ltd.
It has a measuring circuit such as a resistance measuring circuit having a selector and a buffer amplifier for selecting a reference potential and a reference resistance for resistance measurement, corresponding to each measurement mode, which is a part of a function equivalent to 9210. Since the current value or the resistance value can be converted to the voltage value, the time interval at which the current value or the resistance value has changed can be measured. That is, the ON time or OFF time of the relay used in the control machine can be measured as a change in the current value or the resistance value.

[External Configuration of Digital Tester] FIG. 1 is a perspective view showing a state in which a digital tester according to an embodiment of the present invention is used. FIG. 2 is a perspective view showing a state in which the digital tester of the present example is carried. 3A is a front view of the digital tester of this example, FIG. 3B is a left side view thereof, FIG. 3C is a right side view thereof, FIG. 3D is a top view thereof, and FIG. e) is a rear view thereof.

In these figures, a digital tester 1 of the present embodiment includes a digital tester main body 10 in which two plastic main body cases are bonded together, and a pair of probes 2.
0a, 20b, and which of the probes 20a, 20b
b also has metal measuring terminals 21a, 21b on one end side.
And test leads 22a and 22b for electrically connecting the measuring terminals 21a and 21b to the digital tester body 10 at the other end. These probes 20
a, 20b are provided on the plastic gripping parts 23a, 23b with flanges 24a, 24b for safety measures at the front end side.
Is provided. On the upper surface side of the digital tester main body 10, from the upper side to the lower side, a measurement result display section 11, a mode auxiliary selection button 12a (shift button), a range selection button 12b (range button), and a measurement mode A selection rotary switch 13 and the like are provided.
An index 14 for selecting the OFF state is provided around 3.
a, an index 14b for selecting a voltage measurement, an index 14c for selecting a frequency measurement, an index 14d for selecting a resistance measurement, an AC / DC automatic switching 14e, etc. are marked. By rotating, a measurement mode can be selected. Here, the measurement mode selection rotary switch 13
When the mode auxiliary selection button 12a is pressed in a state where is set as the index 14c for selecting the frequency measurement, a function for measuring the pulse width of the input potential can be selected as described later in detail. On the other hand, if this mode is selected and the mode auxiliary selection button 12a is selected for 2 seconds or more, the function returns to the frequency measurement function.

Here, on the upper surface side of the measuring mode selecting rotary switch 13, a small protrusion 132 for preventing slip is formed in a circumferential direction at a predetermined pitch near an outer peripheral edge thereof. Rotary switch 13
It is easy to press the inside of the fingertip against the upper surface side of the and rotate it. In addition, since the small projections 132 are used to prevent slippage, the thickness of the rotary switch is made thinner and the digital tester body 10 is made thinner. The pitch of the small projections 132 formed on the upper surface of the rotary switch 13 for measuring mode selection and the rotary index 131, the indices 14a, 14b,.
Is set to a value different from the formation pitch of the small projection 132 in any of the measurement modes.
4a, 14b,.
This prevents the currently selected measurement mode from being erroneously recognized. Furthermore, the digital tester body 1
0, a rotary switch 1 for selecting a measurement mode
The upper surface side recess 15 is formed from the formation region of the digital tester 3 to the upper surface side edge of the digital tester main body 10. Therefore, it is possible to reliably capture the measurement mode selection rotary switch 13 inside the fingertip.

Further, in the digital tester 1 of this embodiment, a peripheral groove is formed on the side surface of the digital tester main body 10, and the groove formed on the right side surface 101 of the digital tester 1 has the probes 20a and 20b arranged in parallel. The grooves formed in the upper side surface portion 102, the left side surface portion 103, and the lower side surface portion 104 are the test lead storage grooves 18 for storing the test leads 22a and 22b in a parallel state. In addition, the probe storage groove 1
7 is formed in a size that can accommodate two test leads 22a and 22b in addition to the two probes 20a and 20b in a parallel state.
Are the test leads 22a, 2
2b is the test lead storage groove 17 and the probe storage groove 1
8, the probes 20a and 20b can be stored in the probe storage groove 17.

The probe housing groove 17 protrudes inward from both side walls 17a and 17b constituting the probe housing groove 17 and has the outer periphery of the probes 20a and 20b inside the probe housing groove 17 (the end side of the gripping portions 23a and 23b). The engaging elastic contact portions 171 and 172 are formed so as to resiliently contact the probes 20a and 20b accommodated in the probe accommodating groove 17 with respect to the outer periphery of the probes 20a and 20b. The probes 20a, 20b are elastically deformed or elastically deformed on both side walls 17a, 17b, and function as a falling-off preventing mechanism for preventing the probes 20a, 20b from falling off from the probe housing groove 17 by engaging.

Further, as shown in FIGS. 2 and 3A, both side walls 17a, 1a constituting the probe accommodation groove 17 are formed.
7b, the probes 20a, 20
0b are stored when the measuring terminals 21a, 21
b is located at the portion where the probe 20a, 20a,
The measuring terminal portions 21a and 21b of the 20b are formed with concave portions 173 and 174 for exposing the measuring terminal portions to be exposed. 21a and 21b are
Since both are in the exposed state, the measurement terminals 21a and 21b can be brought into conductive contact with the terminals of the system to be measured in this state, and measurement can be performed without removing the probes 20a and 20b. ing.

When the probes 20a and 20b are stored in the probe storage groove 17 of the side walls 17a and 17b constituting the probe storage groove 17,
In portions where the 3a and 23b are located, the probe taking-out recesses 175 and 176 for exposing the grip portions 23a and 23b of the probes 20a and 20b housed in the probe housing groove 17 from the open edge toward the inside. Are formed, and it becomes easy to insert the fingertip from the probe removal concave portions 175 and 176 to pick out the probes 20a and 20b.

FIG. 1 shows test leads 22a and 22b.
Is indicated by a dotted line L,
5 and 176, the test leads 22a and 22b are wound around the digital tester body 10,
The digital tester 1 has a structure with improved functionality such that the digital tester 1 can be temporarily carried.

Further, when the probes 20a and 20b are housed in the probe housing groove 17 of the side walls 17a and 17b constituting the probe housing groove 17, their flanges 2 are formed.
The flanges 24a and 24b of the probes 20a and 20b accommodated in the probe accommodating groove 17 and the side walls 17a are located in the portions where the 4a and 24b are located inward from the open edges thereof.
a, 17b for avoiding interference with a and 17b
7, 178 are also formed, so that the probes 20a, 2
0b is stored in the probe storage groove 17,
2 and 3 (a), the test leads 22a, 22b are housed in the test lead housing groove 17 and the probe housing groove 18, as shown in FIGS. While making a round around the side of the digital tester body 10
When the probes 20a and 20b are housed in the probe housing groove 18, the probes 20a and 20b housed therein are engaged with the engagement elastic contact portions 1 respectively.
71, 172 and the probes 20a, 2b via the test leads 22a, 22b.
0b (in the direction of arrow A)
24b and lower edge 17 of interference preventing recesses 177, 178
It has a structure that acts on an interference portion with 7a and 178a and is used as a holding force.

On the back side of the digital tester main body 10, supporting small projections 19 are formed at the four corners, to secure stability when the digital tester main body 10 is placed on a table or the like.

[Effects of Embodiment] As described above, in the digital tester 1 of this embodiment, the high-speed A / D converter 35
The level of the input signal 90 exceeds the DC determination range set to -3V to + 3V to both the positive side and the negative side within a predetermined period based on the AC / DC determination signal output from An AC / DC determination unit 36 that issues a determination signal 92 indicating that the input signal 90 is AC, and a switching unit 32 that switches the measurement system between the AC side and the DC side based on the determination signal 92. Therefore, in the digital tester 1, the measurement system is automatically switched in response to the input signal 90, and the AC / DC determination signal 9
Since the successive approximation type high-speed A / D converter 35 is employed as the A / D converter that outputs 1, the switching response to the measurement system is high. For example, when the determination of AC / DC is performed using the high-resolution A / D conversion unit 37, about 0.3 to
When the high-speed A / D converter 35 is used, one determination can be made in about 20 msec, while 0.4 seconds is required.

The reset signal generator 38 outputs a reset signal to the high resolution A / D converter 37 when the input signal 90 switches from AC to DC.
The high-resolution A / D converter 37 stops the calculation processing by the reset signal and returns to the initial state. Therefore, the high-resolution A / D conversion unit 37 starts the operation with high responsiveness to the input signal 90 after the switching, and thus the responsiveness of the measurement is high.

Further, as processes A and B, the processes of steps ST2 to ST4 and
5 to step ST7 are repeatedly performed, and the level of the input signal 90 and the DC determination range are compared twice with a predetermined time interval. The input signal 90 is determined to be alternating current when it exceeds either of the side and the negative side. For this reason, since it is not determined only by the determination result in the transition period, there is no possibility that DC is erroneously recognized as AC.

In this example, the DC determination range is-
Although the voltage is set to 3 V to +3 V, the setting of this range is a property that should be set to the optimum condition according to the use of the digital tester 1 and the like, and the positive and negative thresholds thereof are set. May have different absolute values. Further, in setting the DC determination range, a configuration that can be set from outside may be used.

Also, the current value can be converted to a voltage value only by adding a reference resistor for the current (this is already required for providing a current mode). , Respectively, and the measurement can be performed quickly and automatically.

As described above, in the digital tester 1 of this embodiment, the input potential V _IN is the reference potential +1 V,
A potential region signal Sa indicating which of the potential regions A, B, and C is defined by -1V.
, The start and stop times of the pulse width measurement by detecting the rise and fall of the input potential V _IN are defined. For this reason, the pulse width measurement circuit can be configured with a simple circuit configuration, and even if there is noise, the malfunction does not occur unless the potential exceeds the reference potential, so that the pulse width measurement can be performed with high reliability. it can. For example, as shown in FIG. 12F, in the initial state, the input potential V _IN is in the potential region C, and
After that, when the potential returns only to the potential region A after switching to the potential region B, the input potential V _IN first exceeds-
Since the voltage does not exceed the reference voltage of 1 V, the measurement of the pulse width is not stopped. Therefore, even if there is meaningless switching of the potential region due to noise or the like, no malfunction occurs. Further, after the measurement of the pulse width is completed, even if the input potential V _IN switches from the potential area A to the potential area C at time t6,
The stop signal S2 remains held in the D latch circuit 65. In this state, reset signal generator 5
5 outputs a reset signal R to each of the D latch circuits 51,
Since the pulse width measurement is not restarted unless the data holding at 57 and 65 is reset, even if noise or the like is input, the pulse width measurement due to a malfunction does not start.
Moreover, since no relay circuit is used, the resolution is high,
Although the resolution of several μsec was the limit in the case of the conventional circuit meter, the digital tester 1 of the present embodiment can improve the resolution to, for example, 0.1 μsec.

Further, when the pulse width is abnormally long and the measurement is to be interrupted, the forced stop command signal St must be forcibly input from the forced stop command signal generating section 80 to the OR circuit 64 of the stop signal generating section 60. The measurement can be interrupted by this and the convenience is good.

The configuration described in the above embodiment is an example of a digital tester according to the present invention, and for example, a circuit configuration shown in FIG. 13 may be employed.

A digital tester according to a modification of the present embodiment shown in FIG. 13 has substantially the same configuration as that of the digital tester according to the embodiment. Only the circuit configuration of the stop-time detector 61 of the generator 60 is different. Therefore, in the following description, the start detection unit 53 and the stop detection unit 61
Only the circuit configuration described above will be described, and other configurations will be denoted by the same reference numerals and description thereof will be omitted.

That is, in the digital tester shown in FIG. 13, the start detection section 53 of the start signal generation section 50 is composed of three OR circuits 540a to 540c and three AND circuits 530a to 530c. The stop-time detection unit 61 of the unit 60 is connected to three AND circuits 620a.
To 620c. The other configuration is the same as the circuit configuration of the digital tester shown in FIG.

In the digital tester having such a configuration as well, in the start detecting section 53, the input potential V _IN differs from the potential area immediately after the reset based on the potential area signal Sa output from the potential area determination section 40. , The start signal S1 can be output. Further, in the stop time detecting section 61, after the start signal generating section 50 outputs the start signal S 1, the start area signal Sc held by the D latch circuit 57 and the potential output from the potential area determination section 40 are output. Based on the area signal Sa,
It is possible to output the stop signal S2 by detecting that the input potential V _IN has returned to the original potential area again after exceeding the reference potential that has first exceeded.

Although the pulse width detection function may be constituted by a digital circuit as in the above-described embodiment and its modified example, the determination of the potential area and the detection of the switching are performed by a program stored in the microcomputer. In such a case, the start signal and the stop signal may be output. In this case, in place of the D-latch circuit, it is determined that the input potential exceeds the reference potential based on the presence or absence of a flag. Good. Further, regarding the reference potential,
Not limited to +1 V and -1 V, a reference potential setting means such as a trimmer may be provided to make these values variable.

On the other hand, in the digital tester 1 of the present embodiment, the probes 20a and 20
0b is stored therein, the engagement elastic contact portions 171 and 17
Since a fall prevention mechanism using 2 etc. is provided,
Since the probes 20a and 20b do not fall out of the probe storage groove 17, they can be carried in this state. Therefore, it is not necessary to store the probes 20a and 20b in an outer case every time the digital tester 1 is carried, and when using the digital tester 1, the probes 20a and 20b can be removed from the probe housing groove 17 and used as it is. Usability is good. In addition, in the digital tester 1 of this embodiment, a test lead storage groove 18 is formed in addition to the probe storage groove 17. Therefore, when the digital tester 1 is carried, as shown in FIGS. 2 and 3A to 3E, the test lead storage groove 17 and the probe storage groove are kept in a state where the test leads 22a and 22b are arranged in parallel. After the probe 20a and 20b are turned around the side surface of the digital tester main body 10 while being housed in the
Probe 20a, 20b
And the test leads 22a and 22b can be stored without using an external case or the like, and the probes 20a and 20b and the test leads 22a and 22b
Is easy to handle and easy to use.

[0096]

As described above, in the digital tester according to the present invention, the AC / DC determination means determines the level of the input signal and the DC determination range based on the AC / DC determination signal output from the high-speed A / D conversion means. The switching unit is characterized in that the switching unit switches the measurement system between the AC side and the DC side based on the determination signal output from the determination result. . Therefore, according to the present invention, the AC and DC of the input signal are automatically determined, and the measurement system is automatically switched, so that the AC and DC of the input signal can be handled without having electrical knowledge. It can be measured under conditions.

In addition, a high resolution A / D converter is required for the measurement A / D converter, but a high-speed A / D converter is used as the A / D converter for outputting the AC / DC determination signal. Therefore, the switching response to the measurement system is high.

When the level of the input signal is compared at least twice with a predetermined time interval between the level of the input signal and the DC determination range, the AC / DC determination means determines the DC / AC of the input signal only by comparing in the transition period. Since it is not performed, AC and DC can be reliably determined.

In the case where there is a reset signal generating means for outputting a reset signal when the input current is switched between AC and DC, a double integration type high resolution A is used for outputting as a measurement signal. Even if the A / D converter is used, the A / D converter has a high measurement response because the arithmetic processing is returned to the initial state by the reset signal.

Further, as described above, the digital tester of the present invention detects whether or not the input potential has switched to a different potential region beyond the reference potential by the potential region signal from the potential region discriminating means. It is characterized in that the start signal generation means and the stop signal generation means output a start signal and a stop signal for pulse width measurement. Therefore, according to the present invention, since a circuit or a relay circuit for performing time division or successive comparison on an input signal is not required, the pulse width can be measured with a simple configuration, and even if the input signal has noise or the like, the potential of the signal can be reduced. Has no influence on the measurement as long as it does not exceed the reference potential, and a highly reliable pulse width measurement such as high resolution can be performed.

When the pulse width is abnormally long and the measurement is to be interrupted, the measurement can be interrupted by the forced stop command signal from the forced stop command signal generating means.
Easy to use.

As described above, in the digital tester according to the present invention, the probe can be housed in the probe housing groove of the digital tester main body, and the fall prevention mechanism using the engaging elastic contact portion or the like is provided therein. It is characterized by being provided. Therefore, according to the present invention, since the probe does not fall out of the probe housing groove, the probe can be carried in this state. Therefore, there is no need to store the probe in an outer case every time the digital tester is carried, and when the digital tester is used, the probe can be removed from the probe housing groove and used as it is.

When the test lead accommodating groove is formed in addition to the probe accommodating groove, the test lead is wrapped around the side of the digital tester body while being accommodated in the test lead accommodating groove and the probe accommodating groove. later,
Since the probe can be housed in the probe housing groove, the handling of the test leads is easy and the usability is good.

When the concave portion for exposing the measuring terminal portion is formed on both side walls forming the probe accommodating groove, the probe is in an exposed state. The measurement can be performed using the measurement terminal. Further, when the probe removing recesses are formed on both side walls, the probes are in an exposed state, so that the probes stored in the probe storing grooves can be easily removed.

Furthermore, when small projections are provided on the surface side of the measurement mode selection rotary switch, it is possible to prevent slippage without increasing the thickness. Here, if the formation pitch of the small projections and the formation pitch of the measurement mode selection index are set differently, when the measurement mode is selected, the small projections and the measurement mode selection index are aligned. Since it does not enter the state, the selected state of the measurement mode is not mistaken.

When the upper surface side concave portion is formed on the upper surface side of the digital tester main body, the surface of the rotary switch for measuring mode selection can be easily grasped with a fingertip, so that it is easy to rotate it. It is.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a state when a digital tester according to an embodiment of the present invention is used.

FIG. 2 is a perspective view showing a state when the digital tester shown in FIG. 1 is carried.

3A is a front view of the digital tester shown in FIG. 1, FIG. 3B is a left side view thereof, FIG. 3C is a right side view thereof,
(D) is a top view thereof, and (e) is a rear view thereof.

FIG. 4 is a block diagram showing an internal configuration of the digital tester shown in FIG.

FIG. 5 is a flowchart showing an AC / DC determination operation in the digital tester shown in FIG. 1;

FIG. 6 is a flowchart showing a comparison operation between an input signal and a threshold value in the digital tester shown in FIG. 1;

FIG. 7 is a waveform chart of an input signal for describing an operation of comparing the input signal shown in FIG. 6 with a threshold.

8 (a) and 8 (b) are waveform diagrams of input signals for explaining the AC / DC determination operation shown in FIG.

9A is a block diagram illustrating an internal configuration of the digital tester illustrated in FIG. 1, and FIG. 9B is an explanatory diagram illustrating a potential region according to a basic operation thereof.

10 is a circuit block diagram showing a configuration of a pulse width measurement circuit in the digital tester shown in FIG.

FIG. 11 is a timing chart for explaining a pulse width measurement operation in the digital tester shown in FIG. 1;

12A to 12F are explanatory diagrams showing waveforms of input signals which may be input to the digital tester shown in FIG.

FIG. 13 is a circuit block diagram illustrating a configuration of a pulse width measurement circuit of a digital tester according to a modification of the embodiment of the present invention.

FIG. 14A is a front view of a digital tester according to a modified example of the embodiment for describing the effect of the configuration of the measurement mode selection switch of the digital tester shown in FIG. 1;
(B) is a right side view thereof.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Digital tester 20a, 20b ... Probe 21a, 21b ... Measurement terminal part 22a, 22b ... Test lead 31 ... Pull-down resistance 32 ... Switching part (switching means) 33 ... Input path (measuring system on DC side) 34 rectifying / smoothing circuit (measuring system on AC side) 35 high-speed A / D converter (high-speed A / D converter) 36 AC-DC determination Section (AC / DC determination section) 37 high-resolution A / D converter (high-resolution A / D converter) 38 reset signal generator (reset signal generator) 90 input signal 91 ..AC / DC determination signal 92 ... determination signal 93 ... reset signal 95 ... measurement signal 40 ... potential area determination unit 50 ... start signal generation unit 51,57,65 ... D latch circuit 53: Start detection Unit 55: Reset signal generation unit 60: Stop signal generation unit 61: Stop detection unit 70: Clock unit 80: Forced stop command signal generation unit 431 to 433: Signal line C ... Count signal R ... Reset signal Sa ... Potential domain signal Sb ... Reset domain signal Sc ... Start domain signal S1 ... Start signal S2 ... Stop signal V _IN・ Input potential

Claims (5)

[Claims] 1. A high-speed A / D conversion means operable at high speed for digitizing an input signal and outputting it as an AC / DC determination signal, and determining whether the level of the input signal is positive based on the AC / DC determination signal. A threshold value and a DC determination range defined by a negative threshold value are compared, and the level of the input signal exceeds both the positive side and the negative side from the DC determination range within a predetermined comparison period. AC / DC determination means for determining that the input signal is AC and issuing determination signals corresponding to AC and DC, and switching the measurement system between an AC side and a DC side based on the determination signal. Means for digital testers. 2. The method according to claim 1, wherein the AC / DC determination unit compares the level of the input signal with the DC determination range at least twice with a predetermined time interval, and in any comparison period, A digital tester that determines that the input signal is AC and outputs the determination signal when the level of the input signal exceeds the DC determination range on both the positive side and the negative side. 3. The switching device according to claim 1, wherein the switching unit holds the measurement system on one of an AC side and a DC side in a normal state, and the measurement system is connected to the other side. When an input signal to be set to the input side is input, the AC / DC determination unit issues a switching command signal for switching the measurement system from one side, which is a normal state, to the other side, as the determination signal. Digital tester featuring. 4. The switching device according to claim 3, wherein the switching unit sets the measurement system to the DC side as the one side in a normal state, and sets the measurement system to the AC side as the other side. Digital tester featuring. 5. The measurement signal according to claim 1, wherein the input signal is digitized in a state where the measurement system is set on an AC side or a DC side in accordance with the input signal. A double integration type high resolution A / D conversion means is used as the measurement A / D conversion means for outputting as
A digital tester having reset signal generating means for outputting a reset signal when the input current switches between AC and DC with respect to the high resolution A / D conversion means.