JPH06101898B2 - Power frequency discrimination circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply frequency discriminating circuit that automatically discriminates whether the frequency of a power supply is 50 Hz or 60 Hz.

2. Description of the Related Art A conventional power supply frequency discriminating circuit has a circuit configuration as shown in FIG. That is, the power supply synchronization pulse generation circuit 2 connected to the AC power supply 1 generates a pulse train as shown in FIG. 8b in synchronization with the zero point of the voltage of the power supply as shown in FIG. 8a. At the same time, the reference oscillation circuit 3 generates a reference pulse train as shown in FIG. 8C, the gate circuit 4 is opened and closed by the power supply synchronization pulse train, and the reference pulse train is input to the counter 5 at intervals of the power supply synchronization pulse. To do. The output of the counter 5 is input to the comparator 6,
50Hz / 60Hz judgment operation is performed by comparing the magnitude.

Problems to be Solved by the Invention In such a conventional circuit, the circuit configuration is complicated, so that the cost is high, and thus there is a problem that it is difficult to use in a home electric appliance cooker.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a frequency discriminating circuit for a power supply, which has a simple configuration and can surely discriminate the power supply frequency.

Means for Solving the Problems In order to solve the above problems, the present invention has a power supply synchronization pulse generation circuit, a timer circuit, an integration circuit, and a level detection circuit, and the output of the power supply synchronization pulse generation circuit. Is connected to the discharge terminal of the capacitor that determines the time constant of the timer circuit, and the output of the integration circuit is connected to the input terminal of the timer circuit to make the output of the level detection circuit the output for frequency determination, and the timer circuit Is composed of an astable multivibrator, and one time of on / off of the astable multivibrator is set. The time constant of the timer circuit is adjusted by using the time as a monitor signal in accordance with 1/2 of the difference.

Action According to the above configuration, low and high signals can be obtained according to the frequency of the power supply, and the time constant of the timer circuit can be set.
It can be easily set to approximately the middle of the difference between the power supply cycles of 50 Hz and 60 Hz, and the power supply frequency can be reliably determined.

Embodiment One embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a power supply frequency discrimination circuit of the present invention. In FIG. 1, 11 is an AC power supply, 12 is a power supply synchronization for generating a pulse having a time width proportional to the cycle of the power supply voltage. Pulse generator circuit, 13 is a timer circuit,
The timer circuit 13 may be composed of an astable multivibrator that oscillates within a predetermined time width. Reference numeral 14 is an integrator circuit, which performs an integrating operation according to the time constants of R and C. 15
Is a level detection circuit, and this level detection circuit 15 is an integration circuit.
The terminal voltage of 14 capacitors and the reference voltage are compared.

FIG. 2 is a circuit diagram showing an embodiment of the power supply frequency discriminating circuit of the present invention. In FIG. 2, reference numerals 16, 17, 18, 19, 20, and 21 are blocks constituting a power supply synchronizing pulse generating circuit. Reference numeral 21 is a voltage comparator with an open collector output. Since the half-wave rectified waveform is applied to the input terminal of this voltage comparator 21 by the diode 17, the output of the voltage comparator 21 is a half-wave of the power supply. It turns off in a proportional time width.

22,23,24,25,26 are the blocks that make up the timer circuit.
23 is a semi-fixed resistor that determines the operating time of the timer circuit, 2
3, 24 and 25 are charge resistances of the capacitor 26, and 25 is discharge resistance. And the terminal D of this timer circuit 22 is a capacitor
26 discharge terminals, to which the output of the power supply synchronizing pulse generation circuit is connected.

27, 28, 29, 30 are blocks that form an integrating circuit by RC, and when the output signal of the timer circuit 22 is at a high level, the terminal voltage of the capacitor 30 rises to the power supply voltage and the output signal is a pulse train. Then, the terminal voltage of the capacitor 30 becomes a low level.

31,32,33,34 are the blocks that make up the level detection circuit.
The output of the level detecting circuit becomes high or low by comparing the terminal voltage of the capacitor 30 of the integrating circuit with the voltage set by the resistors 31 and 32. Reference numerals 35, 36, 37, 38, 39 are blocks constituting a power supply circuit.

FIG. 3 is a block diagram showing the configuration of the main part of the timer circuit 22, 40, 41, 42 are voltage dividing resistors for generating the reference voltage (1 / 3V _CC , 2 / 3V _CC ), and 43, 44 are Voltage comparators connected to the reference voltages 2 / 3V _CC and 1 / 3V _CC , respectively. Reference numeral 45 is an RS flip-flop, 46 is an inverter, and 47 is a discharging transistor.

The operation of the timer circuit 22 is such that the terminal voltage of the capacitor 26 is charged / discharged between 2 / 3V _CC and 1 / 3V _CC as shown in FIG. 4A to perform an astable multivibrator operation. At this time, a waveform as shown in FIG. 4b is obtained at the output terminal.

In the above circuit configuration, the operation of determining the power supply frequency is performed as follows. Now, as shown in the waveform of FIG. 5a, when the AC power supply 11 has a frequency of 60 Hz, the terminal voltage of the capacitor 26 of FIG. 2 has a waveform as shown in FIG. 5b. Since T ₀₁ is set so that the time width T ₁ of this waveform b is shorter than T ₀₁ in the waveform of FIG. 4a, the terminal voltage of the capacitor 26 does not reach 2 / 3V _CC , Therefore, the output terminal of the timer circuit 22 remains at the high level.

Next, as shown in the waveform of FIG.
At a frequency of 50Hz, the terminal voltage of capacitor 26 is 2 / 3V.
_After reaching _CC , discharge operation is performed during T ₀₂ , and again 1 / 3V _CC
It starts charging from, but is terminated at T ₂ by the power supply synchronization pulse.

The waveform at this time is as shown in FIG. 5d when viewed at the output terminal of the voltage comparator 21, and in T ₂ , the charging period T ₀₁ of the capacitor 26 of the timer circuit and the discharging of the capacitor 26 are included in T _2. There is a period T ₀₂ . Therefore, a waveform as shown in FIG. 6b is generated at the output of the timer circuit for each cycle of the power supply. This waveform becomes a waveform as shown in FIG. 6c by the integrating circuit,
Therefore, at 50 Hz, the output of the level detection circuit becomes low, and it operates in a stable state against external noise.

As described above, low and high signals corresponding to 50 Hz and 60 Hz can be obtained.

Further, as shown in FIG. 5d, a voltage synchronized with the voltage waveform of 50 Hz is generated at the output terminal of the power supply synchronization pulse generation circuit after the charging period T ₀₁ of the capacitor 26 and the discharging period T _{02 have} elapsed. There is. Therefore, if T ₀₁ is adjusted to (T ₂ −T ₁ ) / 2 = T ₀₂ ′ by the semi-fixed resistor 23 in the waveform of FIG. 5D, the set time of the timer circuit becomes 50 Hz. 60Hz
It can be easily set at the center of the cycle. Furthermore, T ₀₂ ′ in FIG. 5d is one of the on and off times of the astable multivibrator, and It is adjusted to about 1/2.

Therefore, when T ₀₁ is changed while looking at this waveform until T ₀₂ −T ₀₂ ′ disappears, T ₀₁ is adjusted to 1/2 of T ₂ −T ₁ .

As a result, accurate measurement is not required, and adjustments and checks in the field can be easily performed.

As described above, according to the present invention, since the time constant of the timer circuit is set by using the output of the power supply synchronization pulse generation circuit as the monitor signal, when setting the pulse width for performing the frequency discrimination operation , The time constant of the timer circuit is 50Hz
It can be easily set to almost the middle of the difference of 60Hz power supply cycle, and as a result, it is possible to realize an automatic power supply frequency discrimination circuit in a stable state with a very simple configuration, which is extremely advantageous in terms of practicality. It will be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a power supply frequency discriminating circuit in an embodiment of the present invention, FIG. 2 is a circuit diagram of the power supply frequency discriminating circuit, and FIG. 3 is a block diagram showing a configuration of a main part of the timer circuit. 4 to 6 are operation waveform diagrams, and FIGS. 7 and 8 are a block diagram and an operation waveform diagram showing a conventional power supply frequency discriminating circuit. 11 ... AC power supply, 12 ... Power supply synchronization pulse generation circuit, 13 ...
… Timer circuit, 14 …… Integrator circuit, 15 …… Level detection circuit, 30 …… Integrator circuit capacitor.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junichi Nakakugi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-56-153933 (JP, A)

Claims (1)

[Claims] 1. A power supply synchronization pulse generation circuit for generating a pulse synchronized with a power supply, and an astable oscillation circuit using a CR charging / discharging circuit capable of independently setting ON / OFF times T ₀₁ and T ₀₂ in one cycle. An integrating circuit having a timer means, a charging path having a constant charging time constant connected to the timer means, and a discharging path having a time constant shorter than the charging time constant; and a level detecting circuit for detecting the output of the integrating circuit. And an output of the power supply synchronization pulse generation circuit, a CR of the astable oscillation circuit.
The output of the timer means is connected to the discharge terminal of the capacitor of the charging / discharging circuit, and the output of the level detecting circuit is used as the output for determining the frequency of the power supply. Set either ON / OFF time T ₀₁ or T ₀₂ to 1/2 × 50 seconds to 1/2 of the difference of 1/2 × 120 seconds, and set the other ON / OFF times T ₀₁ and T _{02 to} CR. A power supply frequency discriminating circuit adapted to be changed by using a means for varying a time constant of a charge / discharge circuit.