JPH11238862A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the transverse etching of a silicide film of a connection part between a bit line and a polycrystalline silicon plug by preventing the unevenness of a polycrystalline silicon plug in a bit line connection hole. SOLUTION: A bit line BL, formed simultaneously with a first layer wiring 18, is made of a laminated film of a titanium film 18a, a titanium nitride film 18b and a tungsten film 18c, and a titanium silicide film 20 containing nitrogen or oxygen is formed in a connection part between the bit line BL and a plug 19. A titanium silicide film 2 containing nitrogen or oxygen may be also formed in a connection part between the first layer wiring 18 and a semiconductor board 1. A tungsten silicide layer containing nitrogen or oxygen, a cobalt silicide layer containing nitrogen or oxygen or a cobalt silicide layer may be formed in place of the titanium silicide film 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art A DRAM is a semiconductor memory that represents a large-capacity memory. The memory capacity of the DRAM tends to increase more and more, and accordingly, the area occupied by the memory cell must be reduced from the viewpoint of improving the integration degree of the memory cell of the DRAM.

However, the storage capacitance of an information storage capacitor (hereinafter simply referred to as a capacitor) in a memory cell of a DRAM requires a certain amount regardless of generation from the viewpoint of considering an operation margin of the DRAM, a soft error, and the like. It is generally known that proportional reduction cannot be performed.

[0004] Therefore, the development of a capacitor structure capable of securing a necessary storage capacity within a limited small occupied area has been promoted. As the structure of such a capacitor,
A three-dimensional capacitor structure in which a plate electrode is formed on a lower electrode made of polysilicon or the like having a three-dimensional structure such as a crown shape via a capacitive insulating film is employed.

In a three-dimensional capacitor, a capacitor electrode is a memory cell selection MISFET (Metal Insulator Semiconductor).
ctor Field Effect Transistor; hereafter simply select MIS
FET)) is generally placed in the upper layer,
In this case, there is a feature that a large storage capacity can be secured with a small occupied area.

As such a three-dimensional capacitor structure, for example, a technique described in Japanese Patent Application Laid-Open No. 7-122654, that is, a so-called capacitor over bit line (Cap) in which a capacitor is arranged above a bit line.
An acitor over bitline (hereinafter abbreviated as COB) structure is known.

In the DRAM having the above-mentioned COB structure, the MIS of the selection MISFET and the MIS of the peripheral circuit are formed on a semiconductor substrate.
An FET is formed, and a bit line for writing and reading data and a first layer wiring of a peripheral circuit are formed above the memory cell via an interlayer insulating film. Thereafter, a capacitor is formed. The capacitor is a storage electrode (lower electrode),
It is formed by sequentially laminating a capacitor insulating film and a plate electrode (upper electrode). The storage electrode of the capacitor is made of polycrystalline silicon doped with an n-type impurity (phosphorus), and is connected to one of the semiconductor regions (source and drain regions) of the n-channel type memory cell selection MISFET. The plate electrode is configured as a common electrode for a plurality of memory cells, and is supplied with a predetermined fixed potential.

The bit line is connected to one of the semiconductor regions (source and drain regions) of the selected MISFET through a connection hole opened in an insulating film covering the selected MISFET.
This connection is made via a polycrystalline silicon plug formed in the connection hole. The other of the semiconductor regions of the selection MISFET is connected to a capacitor. The bit line is made of a low-resistance metal material in order to speed up data write and read operations.

In such a DRAM, a tungsten (W) film is used for a bit line or a first layer wiring of a peripheral circuit. Forming the first layer wiring of the bit line and the peripheral circuit with tungsten having higher electromigration resistance than aluminum (Al) is an effective measure to secure the wiring life of the miniaturized DRAM.

However, in general, at a place where the wiring and the substrate are in contact, a metal material forming the wiring reacts with silicon forming the substrate to form a silicide layer. A silicide (tungsten silicide) layer formed by a reaction between a tungsten film and a silicon substrate exerts a large stress on the substrate. Therefore, the first of the bit lines or peripheral circuits
In the case where the wiring layer is formed of a tungsten film, it is necessary to provide a metal film below the tungsten film so as to form a silicide layer having low stress when reacting with the silicon substrate.

In the above publication, a titanium (Ti) film is exemplified as a metal film for forming such a silicide layer having a small stress. The titanium film has good adhesion to the insulating film, and is formed of titanium silicide (TiSi _x , x ≦
2) The layer exerts less stress on the substrate. For this reason, titanium silicide is a suitable material as a metal film provided below the tungsten film.

Forming a titanium silicide film at the interface between the semiconductor region (source / drain region) of the MISFET constituting the peripheral circuit and the first-layer wiring can also be used as a measure to reduce the contact resistance of the wiring. It is valid.

On the other hand, when a tungsten film is deposited by the CVD method, WF _{6 as} a source gas and silicon (S
There is a problem that i) reacts. Further, when the tungsten film and the silicon are in direct contact, there is a problem that they react by a subsequent heat treatment. Therefore, when a tungsten film is deposited on a titanium film, a barrier layer having good adhesion to these films and preventing contact between WF ₆ and silicon or tungsten and silicon is provided between the titanium film and the tungsten film. Must be provided. In the above publication, a titanium nitride (TiN) film is exemplified as such a barrier layer.

Generally, a DRAM has a memory cell array area, a direct peripheral circuit area, and an indirect peripheral circuit area. Memory cell array area is selected MISFET
And a region where a capacitor is formed, and a sense amplifier and the like for directly detecting the presence or absence of stored charge recorded as information in the capacitor are formed in the peripheral circuit region. The indirect peripheral circuit area is formed around the direct peripheral circuit area. Word lines and bit lines in the memory cell array area are DRAM
Is processed with a minimum processing size in order to maximize the degree of integration. In the direct peripheral circuit region, the MISFET is processed with the minimum processing size in accordance with the pitch of the word line or bit line processed with the minimum processing size, and a connection hole for connecting to the gate electrode or the source / drain region. Is generally processed with a minimum processing size. On the other hand, in the indirect peripheral circuit region, there is a margin in the layout and the influence on the chip area is not so large. Therefore, the connection hole for connecting to the source / drain region of the MISFET has a large diameter. Is ensured.

[0015]

However, as the DRAM is highly integrated, the area occupied by the capacitor is reduced, and the capacitance value must be reduced. For this reason, in order to detect the presence or absence of the stored charge with sufficient sensitivity even with a small storage capacitance value, it is essential to improve the sensitivity of the sense amplifier and to reduce the bit line capacitance. In order to reduce the bit line capacitance, the width of the bit line is reduced to increase the distance between adjacent bit lines, or the thickness of the bit line is reduced, so that the opposition between the adjacent bit lines is reduced. It is necessary to reduce the area.

In order to increase the integration of the DRAM, it is necessary to reduce the area of the memory cell array region occupying a large area of the DRAM, thereby reducing the chip area. In order to reduce the area of the memory cell array region, it is indispensable to optimize the shape and position of the active region of the select MISFET, the word line, the bit line, the capacitor, and the connection hole for connecting each member constituting the memory cell. At the time of this optimization, the shape of each member cannot be a complicated shape. That is, in the memory cell array region, since each member is processed with almost the minimum processing size, it is patterned near the limit of photolithography. This is because if the shape of the member is complicated at the time of patterning, the possibility of occurrence of patterning failure increases due to interference of exposure light between members adjacent to each other. Therefore, the shape of each member is required to be as simple as possible, for example, a linear shape in the case of a word line or a bit line.

However, if the shape of the bit line is to be made straight, or if the width of the bit line is to be reduced,
The connection between the bit line and the polycrystalline silicon plug formed on the source / drain region of the select MISFET, that is, the bit line connection hole cannot be completely covered. Opening structure. That is, when the bit line is etched, the bit line connection hole is also etched at the same time.

When such a bit line processing of the aperture structure is performed, a dug is formed in the polycrystalline silicon plug which is the base of the bit line, and the unevenness of the base caused by the dug is removed by photolithography to be performed later. And adversely affect the etching process, thereby lowering the processing accuracy.

Further, as described in the prior art, a titanium silicide film for reducing contact resistance is formed between a bit line and a polycrystalline silicon plug. When a bit line having an aperture structure is etched, the titanium silicide film is etched, and the titanium silicide film, which is relatively easy to be etched, is also etched in the lateral direction, and a cavity is formed between the bit line and the polycrystalline silicon plug. May occur. The existence of such a cavity,
The conduction between the bit line and the polycrystalline silicon plug is impaired, and D
There is a possibility that the performance of the RAM may be reduced.

On the other hand, as described in the prior art, the bit line and the first layer wiring are formed in the same layer, and a titanium silicide film is also formed at the connection between the first layer wiring and the semiconductor substrate. . The heat resistance of the titanium silicide film is not enough to withstand the heat treatment performed after the formation of the bit line and the first layer wiring, and there is a problem that the leakage current at the connection portion increases. In particular, the present inventors have recognized that when there is a difference in the diameter of the connection hole between the direct peripheral circuit region and the indirect peripheral circuit region, the heat resistance is significantly reduced. Such an increase in leakage current, that is, a decrease in withstand voltage at the connection portion,
This is considered to be particularly noticeable when unreacted titanium remains at the bottom of the connection hole.

An object of the present invention is to provide a technique for preventing unevenness of a polycrystalline silicon plug in a bit line connection hole. Another object of the present invention is to prevent the unevenness, thereby removing an adverse effect in a subsequent process, for example, a photolithography process or an etching process, and increasing a process margin.

It is another object of the present invention to prevent lateral etching of a silicide film at a connection between a bit line and a polycrystalline silicon plug. Another object of the present invention is to prevent the lateral etching of the silicide film, thereby ensuring stable conduction between the bit line and the polycrystalline silicon plug, and improve the yield and reliability of the semiconductor integrated circuit device.

Another object of the present invention is to reduce the capacity of a bit line, reduce the storage capacity required for storing information in a DRAM,
Another object is to improve the operation speed of the DRAM.

Another object of the present invention is to improve the heat resistance of a connection portion between a first layer wiring and a semiconductor substrate when a bit line of a DRAM and a first layer wiring in a peripheral circuit area are shared,
It is an object of the present invention to suppress an increase in leakage current at a connection portion in a subsequent thermal process, and to improve the manufacturing yield of a DRAM and its reliability and performance.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0026]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention has a memory cell array region in which DRAM memory cells each including a selection MISFET and a capacitor are arranged in an array on the main surface of a semiconductor substrate, and a memory cell array region in the periphery of the memory cell array region. And a peripheral circuit region in which the MISFET of the peripheral circuit is formed.
A polycrystalline silicon plug electrically connected to the drain region, a bit line connected to the upper surface of the polycrystalline silicon plug through the first connection hole, and a MIS of the peripheral circuit.
A semiconductor integrated circuit device having a first layer wiring connected to any one of a source / drain region of a FET or a main surface of a semiconductor substrate via a second connection hole, wherein a bit line and a polycrystalline silicon plug are connected to each other. A titanium silicide film containing nitrogen or oxygen, a tungsten silicide film containing nitrogen or oxygen at an interface or an interface between the first layer wiring and the source / drain region of any of the MISFETs of the peripheral circuit or the main surface of the semiconductor substrate , A cobalt silicide film containing nitrogen or oxygen, or a cobalt silicide film is formed. The substance (impurity) contained in the silicide film may be carbon or germanium in addition to nitrogen and oxygen.

According to such a semiconductor integrated circuit device,
At the interface between the bit line and the polycrystalline silicon plug, a silicide film of titanium, tungsten or cobalt containing nitrogen, oxygen, carbon or germanium, or a cobalt silicide film containing no impurities is formed.
Even if the bit lines are formed in an opening structure, that is, even if the contact metal such as a titanium silicide film containing nitrogen or the like is exposed to an etching atmosphere, these contact metals act as an etching stopper. Also, the polycrystalline silicon plug is not scraped by etching. As a result, unevenness due to the dug-in of the polycrystalline silicon plug is not formed, and adverse effects due to the unevenness in subsequent steps such as photolithography or etching can be prevented, and the process margin can be increased.

Further, since the contact metal is not etched, no conduction failure occurs between the bit line and the polycrystalline silicon plug, and the yield and reliability of the semiconductor integrated circuit device can be improved.

The contact metal acts as an etching stopper as described above because the titanium silicide film, the tungsten silicide film or the cobalt silicide film contains nitrogen, oxygen, carbon or germanium, or the cobalt silicide film contains nitrogen. And the like, based on the knowledge obtained through experimental studies by the present inventors that they have etching resistance regardless of the presence or absence of the above.

According to such a semiconductor integrated circuit device, nitrogen, oxygen, carbon, or carbon is formed at the interface between the first layer wiring and one of the source / drain regions of the MISFET of the peripheral circuit or the main surface of the semiconductor substrate. Germanium containing titanium, tungsten or cobalt silicide film,
Alternatively, since a cobalt silicide film containing no impurity is formed, heat resistance can be improved. As a result, the heat process after the formation of the first layer wiring can be performed stably, and the leak current in the peripheral circuit region can be reduced, thereby improving the yield and reliability of the semiconductor integrated circuit device. That is, it is based on the knowledge of the results of the experimental studies by the present inventors that the leak current at the connection portion does not increase even if heat treatment is performed later in the connection hole in which the contact metal such as the titanium silicide film is formed. The increase in leakage current is considered to be caused by aggregation of the titanium silicide film due to the thermal process or diffusion of titanium into the impurity diffusion region.
It is considered that such aggregation or diffusion of titanium is suppressed in the titanium silicide film containing nitrogen, oxygen, carbon, or germanium as described above.

The content of nitrogen or oxygen can be in the range of 1 atomic% to 13 atomic%.
If the content of nitrogen or oxygen is small, the etching resistance is inferior, and the heat resistance is inferior. Conversely, if the content of nitrogen or oxygen is large, the contact resistance increases and the metal cannot function as a contact metal. . Therefore, there is a practically appropriate range for the content of nitrogen or oxygen, and such a range is determined by experimental studies by the present inventors.
It has been found that 1 atomic% to 13 atomic% is suitable. More preferably, when the content (impurity) is nitrogen, the effect is great when the concentration is in the range of 1 to 3 atomic%. Such findings are also based on experiments and studies by the inventors.

(2) In the semiconductor integrated circuit device of the present invention, the selected MISFE arranged in an array on the main surface of the semiconductor substrate is provided.
T, a polycrystalline silicon plug formed in the first insulating film on one of the source / drain regions of the selection MISFET;
A semiconductor integrated circuit device having a bit line formed on a second insulating film on the first insulating film, wherein a first connection hole is opened in the second insulating film on the polycrystalline silicon plug; And the polycrystalline silicon plug are connected via a metal plug formed in the first connection hole.

According to such a semiconductor integrated circuit device,
Since the metal plug is formed in the first connection hole of the second insulating film, the connection between the bit line and the polycrystalline silicon plug is performed via the metal plug. For this reason, even when the bit line is formed in an opening structure with respect to the first connection hole, the metal plug functions as a stopper against the etching when patterning the bit line, and the contact metal or the metal plug is used. The crystalline silicon plug is not exposed to the etching atmosphere. As a result, it is possible to prevent the formation of irregularities due to the dugout of the polycrystalline silicon plug and the occurrence of conduction failure due to the lateral etching of the contact metal,
As in the case of (1), the process margin can be increased, and the yield and reliability of the semiconductor integrated circuit device can be improved.

When the first connection hole is buried with a metal plug, the thickness of the bit line can be reduced to half or less of the diameter of the first connection hole. As described above, since the bit line thickness can be reduced, the bit line capacity can be reduced and the DRA can be reduced.
The storage capacitance of M can be reduced or the detection accuracy of the stored charge can be improved, and the response speed of the DRAM can be improved.

That is, the bit lines are formed close to each other in the memory cell region of the DRAM, and are formed long over the memory cell array region between the direct peripheral circuits where the sense amplifiers are arranged. Therefore, if the bit line thickness is large, the facing area between the bit lines increases, and the line capacitance increases. The increase in the line capacitance causes a decrease in the detection sensitivity of the sense amplifier, and causes a decrease in the performance of the DRAM. However, if the present invention is applied,
Since the thickness of the bit line can be reduced, the facing area between the bit lines can be reduced, and the capacitance between the bit lines can be reduced. As a result, the accuracy of detecting the accumulated charges can be improved. Further, since the response speed is inversely proportional to the product of the stray capacitance and the resistance value, the reduction of the line capacitance can contribute to the improvement of the response speed.

The bit line can be made of tungsten or molybdenum, and the metal plug can be made of titanium nitride or tungsten nitride. In this case, while the bit line can be etched using a fluorine-based etching gas, titanium nitride or tungsten nitride has a low etching rate with a fluorine-based etching gas. Almost no etching. As a result, sufficient overetching can be performed at the time of patterning the bit line, and the process margin can be increased.

In other words, in the case of the above (1) or (2), the bit line is made of a material which can be selectively etched with respect to a base material in the first connection hole. can do. That is, the base material in the first connection hole may be a titanium silicide film containing nitrogen or the like, a metal plug such as titanium nitride, or any other material having etching resistance to the bit line.
By having such a base material, even if patterning is performed on the bit line having the aperture structure, it is possible to prevent unevenness due to shaving of the polycrystalline silicon plug or poor conduction due to lateral etching of the contact metal.

It is also possible to apply a laminated film of titanium nitride and tungsten as the material of the metal plug and apply a single-layered film of tungsten as the bit line material.
In this case, since the base material in the metal plug, that is, the first connection hole includes tungsten, this corresponds to the case where the etching selectivity with the base cannot be obtained when the tungsten film as the bit line material is etched. However, since the thickness of the tungsten film serving as the bit line can be reduced, even if over-etching is performed, the over-etching time is about 50% of the bit line thickness, and during this time, the underlayer, that is, the metal plug The amount of tungsten etched is small. That is, even if the bit line is formed of the same material as the material forming the metal plug, it is hardly etched to the bottom of the plug by over-etching, and a problem such as side etching of the silicide film at the bottom of the plug does not occur. Absent.

(3) The semiconductor integrated circuit device according to the present invention provides a selective MISFE arranged in an array on the main surface of a semiconductor substrate.
T, a polycrystalline silicon plug formed in the first insulating film on one of the source / drain regions of the selection MISFET;
Semiconductor having a second insulating film deposited on a first insulating film and a bit line connected to the polycrystalline silicon plug via a first connection hole opened in the second insulating film on the polycrystalline silicon plug An integrated circuit device, comprising: a bit line having a thickness L ₁ ,
Distance L and the thickness L ₁ of the bit lines in addition to the thickness of the second insulating film
₂ and the diameter D of the first connection hole, L ₁ ×
(1 + OVE) <L ₂ , and L ₁ > D / 2 (provided that OVE is an over-etch amount when patterning a bit line).

According to such a semiconductor integrated circuit device,
By satisfying the condition of L ₁ > D / 2, the first connection hole is completely buried with a film to be a bit line, and at the same time, L ₁ × (1
+ OVE) <L ₂ , that is, the bit line thickness in the first connection hole, which can be approximated by the distance L _{2 obtained} by adding the bit line thickness L ₁ to the thickness of the second insulating film, is L ₁ × ( 1 + OV
Since the condition equal to or more than the etching amount shown in E) is satisfied, when the patterning of the bit line is completed, the film remains in the first connection hole. With the film remaining in this manner, the contact metal and the polycrystalline silicon plug are not etched,
There is no occurrence of the above-mentioned unevenness or poor conduction.
As a result, similarly to the above (1) and (2), the process margin can be increased, and the yield and reliability of the semiconductor integrated circuit device can be improved.

In the above (1) to (3), the width of the bit line is smaller than the diameter of the first connection hole, that is, the bit line has an aperture structure with respect to the first connection hole. Can be. Here, the opening structure is a positive opening structure in mask design, and naturally refers to the expected opening structure. However, the opening structure is not limited to this, and may be accidentally opened due to mask misalignment in the manufacturing process. Needless to say, the present invention can also be applied to cases where the above is true.

(4) The semiconductor integrated circuit device according to the present invention has a memory cell array region in which DRAM memory cells each including a selected MISFET and a capacitor are arranged in an array on the main surface of a semiconductor substrate, and a memory cell array region in the periphery of the memory cell array region. Including a formed direct peripheral circuit region and an indirect peripheral circuit region formed around the direct peripheral circuit region, connecting the main surface of the semiconductor substrate in the direct peripheral circuit region or the indirect peripheral circuit region to the first layer wiring A semiconductor integrated circuit device having a connection hole, wherein the diameter of the connection hole is the same in the direct peripheral circuit region and the indirect peripheral circuit region.

According to such a semiconductor integrated circuit device,
Since the diameter of the connection hole is the same in the direct peripheral circuit region and the indirect peripheral circuit region, the heat resistance of the connection portion between the first layer wiring and the semiconductor substrate at the bottom of the connection hole is improved, and the connection of the semiconductor integrated circuit device is improved. Resistance can be reduced and leakage current can be reduced. As a result, it is possible to improve the production yield, reliability and performance of the semiconductor integrated circuit device.

That is, since the diameters of the connection holes are the same, the thickness of each of the layers constituting the wiring formed including the bottom of the connection holes, ie, the titanium layer, the titanium nitride layer, and the tungsten layer is reduced by the thickness of each connection hole. Will be formed uniformly at the bottom of the. Since the thickness of each layer is formed uniformly at the bottom of the connection hole, the heat resistance of each connection hole does not vary, and the heat resistance of the wiring at the bottom of the connection hole can be improved. In particular, by making the thickness of the titanium layer uniform at the bottom of each connection hole, the formation of the titanium silicide film can be performed uniformly.
In the formation of the titanium silicide film, a titanium film that has not undergone a silicidation reaction does not remain. If such an unreacted titanium layer remains, the unreacted titanium is silicided in a subsequent heat treatment step, causing unexpected stress in the titanium silicide film or forming voids in the semiconductor substrate, resulting in heat resistance. There is a fear that the property may be reduced, but in the case of the present invention, such a fear does not occur.

It is apparent from experiments conducted by the present inventors that a residual titanium film is generated due to such a variation in the titanium film thickness in the connection hole, and this causes a reduction in heat resistance. It has become.

The aspect ratio of the connection hole can be the same in the memory cell array region, the direct peripheral circuit region, and the indirect peripheral circuit region. Even when the diameters of the connection holes are different, the film thickness at the bottom of the connection hole can be made uniform by keeping the aspect ratio constant. As a result, a decrease in heat resistance due to the difference in titanium film thickness can be prevented.

(5) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: (a) arranging select MISFETs in a memory cell array region on the main surface of a semiconductor substrate in an array form; Forming and selecting MISF
Depositing a first insulating film covering the MISFET of the ET and the peripheral circuit, and (b) forming a first connection hole exposing at least one source / drain region of the selected MISFET.
Forming an opening in the insulating film and forming a polycrystalline silicon plug in the first connection hole; (c) depositing a second insulating film on the first insulating film and the polycrystalline silicon plug; A step of opening an exposed second connection hole in the second insulating film; (d) etching the second insulating film and the first insulating film in the peripheral circuit region to form a source / drain region or a peripheral circuit region of a MISFET in the peripheral circuit (E) depositing a conductive film on the second insulating film, patterning the conductive film to form a bit line in the memory cell array region, and forming a peripheral circuit region. Forming a first layer wiring in the semiconductor integrated circuit device, wherein before the step (e), the inside or bottom of the second connection hole or the inside or bottom of the third connection hole is provided. One of Both, and has a step of forming a member having a lower etching rate than the etching rate of the conductive film in the etching process using the patterning of the conductive film.

According to such a method of manufacturing a semiconductor integrated circuit device, before the step (e), one or both of the inside and the bottom of the second connection hole or the inside and the bottom of the third connection hole are performed. In order to form a member having an etching rate lower than the etching rate of the conductive film in the etching method used for patterning the conductive film, the member is used as an etching stopper when etching the conductive film, that is, when patterning the bit line. be able to. Therefore, the contact metal is not etched when the contact plug is formed on the polysilicon plug or the upper surface of the polysilicon plug. As a result, no digging is formed in the polycrystalline silicon plug, and the contact metal is not etched in the lateral direction, so that the formation of unevenness or the poor conduction of the bit line does not occur.

In this case, the member is used as an etching stopper for etching the bit line in the step (e),
A bit line having a width smaller than the diameter of the second connection hole can be processed. That is, the bit line can have an opening structure with respect to the second connection hole, and it is possible to cope with higher integration of the semiconductor integrated circuit device and lower capacity of the bit line.

Further, the member may be made of nitrogen, oxygen, carbon or germanium formed on the second insulating film in an amount of 1 atomic% to 13 atomic%.
A cobalt film, a titanium film, a tungsten film, or a cobalt film containing in the range of atomic% can be heat-treated to form a polycrystalline silicon plug or a silicide film formed by a silicide reaction with a main surface of a semiconductor substrate. The silicide film formed by such a method contains nitrogen, oxygen, carbon or germanium in a range of 1 atomic% to 13 atomic%, and as described above, such a silicide film has etching resistance. is there. In addition,
When nitrogen is contained, as described above, a more favorable effect can be obtained by setting the content in the range of 1 to 3 atomic%.

The member can be a plug formed of tungsten, titanium nitride or tungsten nitride formed in the second connection hole or the third connection hole. Even when the plug of the connection hole is formed in this way, the plug functions as an etching stopper.

Further, in the above manufacturing method, the diameter of the third connection hole, that is, the connection hole of the peripheral circuit can be uniformly opened. According to such a manufacturing method, the heat resistance of the connection portion between the first layer wiring and the semiconductor substrate at the bottom of the third connection hole can be improved.

(6) In the semiconductor integrated circuit device of the present invention, the thickness of the silicide film of titanium, tungsten or cobalt is set to 15 to 30 nm. By setting the thickness of the silicide film to 15 to 30 nm, the connection resistance at that portion can be reduced. Such an effect of reducing the connection resistance is a result of experiments and studies by the present inventors.

The outline of the present invention will be described below in sections.

(1) The semiconductor integrated circuit device of the present invention
First memory cell selecting first formed on the main surface of the semiconductor substrate
A MISFET and a second MISFET for peripheral circuits;
A polycrystalline silicon plug formed in a first insulating film on one of the source / drain regions of the first MISFET, and a polycrystalline silicon plug formed through a first connection hole opened in a second insulating film on the first insulating film; A second insulating film electrically connected to a source / drain region of the second MISFET via a bit line on the second insulating film electrically connected to the second MISFET via a second connection hole of the first and second insulating films; A semiconductor integrated circuit device having an upper first layer wiring, a connection region between a bit line and a polycrystalline silicon plug, or a first layer wiring and a second MISF.
The source / drain region of the ET or the gate electrode or the connection region with the main surface of the semiconductor substrate is formed of a silicide film of an element selected from titanium, tungsten or cobalt and containing an impurity, or a cobalt containing no impurity. A silicide film is formed, and impurities are
Any one or more elements selected from nitrogen, oxygen, carbon and germanium.

(2) In the above item (1), the content of impurities is in the range of 1 atomic% to 13 atomic%.

(3) In the above item (2), the impurity is nitrogen, and the content of nitrogen is 1 atomic% to 3 atomic%.
Range.

(4) In the above item (1), the line width of the bit line is equal to or smaller than the diameter of the first connection hole.

(5) The semiconductor integrated circuit device of the present invention
First memory cell selecting first formed on the main surface of the semiconductor substrate
A semiconductor integrated circuit having a MISFET, a polycrystalline silicon plug formed on a first insulating film on one source / drain region of the first MISFET, and a bit line formed on a second insulating film on the first insulating film A circuit device, wherein a first connection hole is opened in a second insulating film, and a bit line and a polycrystalline silicon plug are connected via a first plug formed in the first connection hole. It is.

(6) In the above item (5), the surfaces of the first and second insulating films are flattened at least over a region where the first MISFET is formed, and the surface of the first plug and the surface of the second insulating film are formed. Are formed on the same plane.

(7) In the above item (5), the thickness of the bit line is not more than half the diameter of the first connection hole.

(8) In the above item (5), the line width of the bit line is smaller than the diameter of the first connection hole.

(9) In the above item (5), the bit line is made of a material which can be selectively etched with respect to the first plug.

(10) In the above item (5), the bit line is made of a single-layer film of tungsten or molybdenum, and the first plug is made of a stacked film containing titanium nitride and tungsten, or made of titanium nitride or tungsten nitride. Things.

(11) In the above item (5), furthermore, the second MI of the peripheral circuit formed on the main surface of the semiconductor substrate is formed.
SFET and the first of peripheral circuits formed on the second insulating film.
A second connection hole is opened in the first and second insulating films, and the first layer wiring and the source / drain region or the gate electrode of the second MISFET or the main surface of the semiconductor substrate are connected to each other. The two plugs are connected via a second plug formed in the connection hole. The second plug is made of the same material as the first plug, and the first layer wiring is made of the same material as the bit line.

(12) In the above item (11), the first
And the surface of the second insulating film is planarized over the entire surface of the semiconductor substrate, and the surfaces of the first and second plugs and the second
The surface of the insulating film is formed on the same plane.

(13) In the above item (11), the bit line and the first-layer wiring are made of a single-layer film of tungsten or molybdenum, and the first and second plugs are a stacked film including a titanium nitride film and a tungsten film. Or titanium nitride or tungsten nitride.

(14) In the above item (11), the first
The connection area between the plug and the polycrystalline silicon plug, or
The connection region between the second plug and the source / drain region or gate electrode of the second MISFET or the main surface of the semiconductor substrate is a silicide film of an element selected from titanium, tungsten or cobalt and containing an impurity, or A cobalt silicide film containing no impurity is formed, and the impurity is one or more elements selected from nitrogen, oxygen, carbon, and germanium, and the content of the impurity is 1 atomic% to 13 atomic%. Range.

(15) In the above item (14), the impurity is nitrogen, and the content of nitrogen is in a range of 1 atomic% to 3 atomic%.

(16) In the above item (11), the first
In the connection region between the plug and the polycrystalline silicon plug, the connection region between the second plug and the source / drain region or gate electrode of the second MISFET or the main surface of the semiconductor substrate, or the source / drain surface region of the second MISFET, A silicide film of an element selected from titanium, tungsten or cobalt is formed, and the thickness of the silicide film in any connection region or surface region is 15 to 3
0 nm.

(17) In the above item (16), the second
The MISFET includes a p-channel MISFET, and the source / drain surface region of the p-channel MISFET or the bottom of the second plug and the p-channel MISFET
The thickness of the silicide film formed in the connection region with the source / drain region of the ISFET is 15 to 30 nm.

(18) The semiconductor integrated circuit device of the present invention is formed on the first MISFET for memory cell selection formed on the main surface of the semiconductor substrate and on the first insulating film on one of the source / drain regions of the first MISFET. The polycrystalline silicon plug, the second insulating film formed on the first insulating film, and the bit line connected to the polycrystalline silicon plug via the first connection hole opened in the second insulating film. a semiconductor integrated circuit device having a thickness L ₁ of the bit line, and the distance L ₂ plus the thickness L ₁ of the bit lines to a thickness of the second insulating film,
L ₁ × (1 + OVE) between the diameter D of the first connection hole and
<L ₂ and L ₁ > D / 2 (provided that OVE is an over-etch amount when patterning a bit line).

(19) In the above item (18), the line width of the bit line is equal to or smaller than the diameter of the first connection hole.

(20) In the semiconductor integrated circuit device of the present invention, a first MISFET for selecting a memory cell is formed in a memory cell region arranged in an array on the main surface of a semiconductor substrate, and is formed around the memory cell region. Direct peripheral circuit area,
A semiconductor integrated circuit device having a second connection hole for connecting a main surface of the semiconductor substrate in the direct or indirect peripheral circuit region to the first-layer wiring, including an indirect peripheral circuit region formed around the direct peripheral circuit region; In addition, the diameter of the second connection hole is the same in the direct and indirect peripheral circuit regions.

(21) In the above item (20), the second
The aspect ratio of the connection hole is the same in the memory cell region, the direct peripheral circuit region, and the indirect peripheral circuit region.

(22) The semiconductor integrated circuit device according to the present invention comprises a first MISFET for selecting a memory cell and a second MISFET for a peripheral circuit formed on a main surface of a semiconductor substrate.
A polycrystalline silicon plug formed in a first insulating film on one of the source / drain regions of the first MISFET, and a polycrystalline silicon via a first connection hole opened in a second insulating film on the first insulating film. A bit line on the second insulating film electrically connected to the silicon plug; and a second line electrically connected to the source / drain region of the second MISFET via the second connection holes of the first and second insulating films. A semiconductor integrated circuit device having a first layer wiring on an insulating film, wherein a connection region between a bit line and a polycrystalline silicon plug, a first layer wiring and a second MISFET are provided.
Connection region with the source / drain region or gate electrode or the main surface of the semiconductor substrate, or the second MISFET
In the source / drain surface region, a silicide film of an element selected from titanium, tungsten or cobalt is formed, and the thickness of the silicide film in any connection region or surface region is 15 to 30 nm. .

(23) In the above item (22), the second
The MISFET includes a p-channel MISFET, and the source / drain surface region of the p-channel MISFET or the first layer wiring and the p-channel MISFET
The thickness of the silicide film formed in the connection region with the source / drain region of the FET is 15 to 30 nm.

(24) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first MISFET for selecting a memory cell is formed on a main surface of a semiconductor substrate, and a first insulating film covering the first MISFET is formed. After that, the first insulating film is replaced with the first MI.
Etching in the presence of a photoresist film having an opening on at least one source / drain region of the SFET; (b) polycrystalline silicon filling the opening of the first insulating film formed by etching over the entire surface of the semiconductor substrate Depositing a film, removing the polycrystalline silicon film on the first insulating film, and forming a polycrystalline silicon plug electrically connected to the source / drain regions of the first MISFET;
(C) forming a second insulating film on the first insulating film, and etching the second insulating film in the presence of a photoresist film having an opening on the polycrystalline silicon plug to make a first connection with the second insulating film; Forming a hole, (d) the bottom of the first connection hole and the second
A metal film containing one or more impurities selected from nitrogen, oxygen, carbon, and germanium on an insulating film, the one containing titanium, tungsten, or cobalt as a main component, or an impurity Depositing a cobalt film that does not contain any of the above and performing a heat treatment; (e)
Depositing a first conductive film on a metal film or a cobalt film to form a first conductive film;
(F) forming a photoresist film patterned into a bit line pattern on the first conductive film, and etching the metal film or the cobalt film and the first conductive film in the presence of the photoresist film; Forming a bit line.

(25) In the above item (24), the silicide film formed in the connection region between the metal film or the cobalt film and the polycrystalline silicon plug by the heat treatment functions as an etching stopper in the etching step.

(26) In the item (24), the pattern width of the bit line pattern is equal to or smaller than the diameter of the first connection hole.

(27) In the item (24), the content of the impurity in the metal film is in a range of 1 atomic% to 13 atomic%.

(28) In the above item (27), the impurity is nitrogen, and the content of the impurity in the metal film is 1 atomic%.
-3 atomic%.

(29) In the above item (24), the first
The conductive film is a stacked film of titanium nitride and tungsten.

(30) In the above item (24), the first
Second MISF for peripheral circuit in the same process as MISFET
The ET is formed, and in the same step as the formation of the first connection hole, or before or after the formation of the first connection hole, electric power is applied to the source / drain region or gate electrode of the second MISFET or the semiconductor region on the main surface of the semiconductor substrate. A second connection hole for forming a first connection is formed in the same step as the formation of the bit line.

(31) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, (a) a first MISFET for selecting a memory cell is formed on a main surface of a semiconductor substrate, and a first insulating film covering the first MISFET is formed. After that, the first insulating film is replaced with the first MI.
Etching in the presence of a photoresist film having an opening on at least one source / drain region of the SFET; (b) polycrystalline silicon filling the opening of the first insulating film formed by etching over the entire surface of the semiconductor substrate Depositing a film, removing the polycrystalline silicon film on the first insulating film, and forming a polycrystalline silicon plug electrically connected to the source / drain regions of the first MISFET;
(C) forming a second insulating film on the first insulating film, and etching the second insulating film in the presence of a photoresist film having an opening on the polycrystalline silicon plug to make a first connection with the second insulating film; Forming a hole, (d) depositing a first conductive film filling the first connection hole, removing the first conductive film on the second insulating film,
Forming a first plug made of a first conductive film in the first connection hole; (e) forming a second plug on the first plug and the second insulating film;
And (f) forming a bit line by patterning the second conductive film.

(32) In the above item (31), the first
Before the step of etching the insulating film, the first insulating film is planarized by the CMP method, and the first plug is formed by polishing the first conductive film by the CMP method.

(33) In the above item (31), the second
The thickness of the conductive film is equal to or less than half the diameter of the first connection hole.

(34) In the item (31), the width of the bit line is equal to or smaller than the diameter of the first connection hole.

(35) In the above item (31), the second
The conductive film is a material having an etching selectivity with respect to the first plug.

(36) In the above item (31), the first
The conductive film is a stacked film including a titanium nitride film and a tungsten film, or a single-layer film made of titanium nitride or tungsten nitride, and the second conductive film is a single-layer film made of tungsten or molybdenum.

(37) In the above item (31), the first
In the same step as the MISFET, the second MIS in the peripheral circuit region
Forming a second connection hole for connecting to the source / drain region of the second MISFET in the same step as the formation of the first connection hole or before or after the formation of the first connection hole; At the same time as the formation of one plug, the first plug is inserted into the second connection hole.
A second plug made of a conductive film is formed, and simultaneously with formation of a bit line, a first layer wiring of a peripheral circuit made of the second conductive film is formed.

(38) In the above item (37), the first
And before the formation of the second plug, the concentration of one or more impurities selected from nitrogen, oxygen, carbon and germanium on the bottoms of the first and second connection holes and on the second insulating film. Depositing a metal film containing 1 atomic% to 13 atomic% and containing titanium, tungsten or cobalt as a main component, or a cobalt film containing neither impurity and heat treatment It has.

(39) In the above item (37), the first
Before the formation of the second plug, a metal film containing titanium, tungsten or cobalt as a main component is formed on the bottoms of the first and second connection holes and on the second insulating film. A step of depositing in a range of 20 nm and performing a heat treatment, or a step of depositing a silicide film of titanium, tungsten or cobalt with a thickness in a range of 15 to 30 nm, or a step of mainly depositing any of titanium, tungsten or cobalt. Depositing a metal film as a component, further depositing a silicon film with a thickness smaller than that of the metal film and performing a heat treatment, or depositing a metal film containing titanium, tungsten or cobalt as a main component. And annealing the metal film in an atmosphere of silicon hydride gas.

(40) In the above item (39), after the heat treatment step of the metal film, unreacted titanium, tungsten or cobalt is selectively removed by etching.

(41) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of (a) forming a MISFET on a main surface of a semiconductor substrate and forming an insulating film covering the MISFET;
(B) etching the insulating film in the presence of a photoresist film having an opening on the source / drain region of the MISFET to form a connection hole in the insulating film; and (c) depositing a conductive film filling the connection hole. Forming a photoresist film patterned into a wiring pattern on the conductive film, and forming a wiring by etching the conductive film in the presence of the photoresist film. Before forming the conductive film, a metal film containing titanium, tungsten or cobalt as a main component is formed on the bottom of the connection hole and on the insulating film so as to have a thickness of 10 to 20 n.
m, a step of performing a heat treatment, or a titanium, tungsten or cobalt silicide film,
Depositing a film having a thickness of 15 to 30 nm, or depositing a metal film containing titanium, tungsten or cobalt as a main component, and further depositing a silicon film with a thickness smaller than the metal film. , A step of performing a heat treatment, or a step of depositing a metal film containing any of titanium, tungsten, and cobalt as a main component and heat-treating the metal film in an atmosphere of silicon hydride gas. It is.

(42) In the above item (41), after the heat treatment step of the metal film, unreacted titanium, tungsten or cobalt is selectively removed by etching.

(43) In the above item (41), the conductive film is any one of a laminated film of titanium nitride and tungsten or a three-layer laminated film of titanium, titanium nitride and tungsten.

(44) The method of manufacturing a semiconductor integrated circuit device according to the present invention comprises: (a) a step of forming a MISFET on a main surface of a semiconductor substrate; and (b) titanium, tungsten at least in a region covering a source / drain of the MISFET. Alternatively, a step of depositing a metal film containing any of cobalt as a main component in a thickness range of 10 to 20 nm, and (c) a step of heat-treating the metal film to form a silicide film at a contact portion with silicon. , (D) a heat treatment step), a step of selectively removing unreacted titanium, tungsten or cobalt by etching, (e) a step of forming an insulating film covering the MISFET, and (f) on a source / drain region of the MISFET. Forming a connection hole in the insulating film by etching the insulating film in the presence of a photoresist film having an opening in the opening; Depositing a conductive film that embeds therein, forming a photoresist film patterned into a wiring pattern on the conductive film, and etching the conductive film in the presence of the photoresist film to form a wiring. .

(45) In the above item (44), the conductive film is any of a laminated film of titanium nitride and tungsten, or a three-layered film of titanium, titanium nitride and tungsten.

[0101]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a plan view showing an example of an entire semiconductor chip on which a DRAM according to an embodiment of the present invention is formed. As shown, a large number of memory arrays MARY are provided along the X direction (long side direction of the semiconductor chip 1A) and the Y direction (long side direction of the semiconductor chip 1A) on the main surface of the semiconductor chip 1A made of single crystal silicon.
Are arranged in a matrix. A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. In the center of the main surface of the semiconductor chip 1A, control circuits such as a word driver WD and a data line selection circuit, input / output circuits, and bonding pads are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM of the first embodiment. As shown, the memory array (MARY) of the DRAM includes a plurality of word lines WL (WL _n−1 , WL _n , WL _{n + 1} ...) And a plurality of bit lines BL arranged in a matrix. It is composed of a plurality of memory cells (MC) arranged at intersections. One memory cell for storing one bit of information is composed of one capacitor C and one selection MISFET Q connected in series with this.
s. One of the source and the drain of the selection MISFET Qs is electrically connected to the capacitor C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to a word driver WD,
One end of the bit line BL is connected to the sense amplifier SA.

FIG. 3 is an enlarged plan view of a part of FIG. In FIG. 3, bit lines B
L, the bit line connection hole BLCT and the first layer wiring M1 are indicated by solid lines, and the other members are indicated by broken lines or dotted lines. 3 shows a part of the memory array MARY, and the right side shows an n-channel MISF of a direct peripheral circuit.
ETQn and a p-channel MISFET Qp forming a part of the sense amplifier SA are shown. n channel M
ISFET Qn functions as a shared MISFET.

The memory array MARY has an active area L ₁
Are arranged, word lines WL are formed in the Y direction, and bit lines BL are formed in the X direction. Word line WL and active region L ₁
And the word line WL is connected to the selected MISFE
It functions as a gate electrode of TQs. Region of the active region L ₁ sandwiched in a region that functions as a gate electrode of the word line WL, and that is, the central portion of the active region L ₁ is formed with the bit line contact hole BLCT, a central portion of the active region L ₁ The bit line is connected via a bit line connection hole BLCT. Across the region of the active region L ₁ is a capacitor contact hole SN
Connected to capacitor C via CT.

An active region L ₂ and an active region L ₃ are formed in the peripheral circuit region, and the active region L ₂ and the gate wiring FG are formed.
An n-channel MISFET Qn functioning as a shared MISFET is formed in a portion overlapping with the MISFET Qn. n
One source / drain region of the channel MISFET Qn is connected to the bit line BL via the connection hole CT. The other source / drain region of the n-channel MISFET Qn is connected to the first layer wiring M1 via the connection hole CT. P-channel M which constitutes a part of the sense amplifier SA to the overlapping portion of the active region L ₃ and the gate wiring FG2
ISFET Qp is formed.

In the present embodiment, the bit line connection hole BLCT has an opening structure with respect to the bit line BL. That is, the bit line BL is connected to the bit line connection hole BL.
The width is shorter than the opening diameter of the CT, and the CT has a linear shape. Since such a bit line BL has a simple shape, interference of exposure light hardly occurs during photolithography, and the resolution is easily increased. Further, the adjacent bit line BL
Since the interval between them becomes longer, the capacitance of the bit line BL can be reduced. These characteristics facilitate the fine processing of the DRAM and contribute to the improvement of the sensitivity of the sense amplifier SA against the reduction of the accumulated charge due to the miniaturization, which is particularly advantageous for the future miniaturization and high integration of the DRAM. is there.

FIG. 4 is a sectional view taken along the line IV-IV in FIG. In FIG. 4, an area A is a memory array MARY.
And a region B shows a part of a peripheral circuit.

On the main surface of semiconductor substrate 1 made of p-type single crystal silicon, p-type well 2 in region A, p-type well 3 and n-type well 4 in region B are formed. Also, p
An n-type deep well 6 is formed so as to surround shape well 2. Note that a threshold voltage adjustment layer may be formed in each well.

On the main surface of each well, an isolation region 7 is formed. The isolation region 7 is made of a silicon oxide film and is formed in a shallow groove 8 formed on the main surface of the semiconductor substrate 1 via a thermally oxidized silicon oxide film 9.

The main surface of the p-type well 2 has a DRAM selection M
ISFET Qs is formed. Also, p-type well 3
And n-channel MISF on the main surface of n-type well 4 respectively.
ETQn and p-channel MISFETQp are formed.

The selection MISFET Qs has a gate electrode 11 formed on the main surface of the p-type well 2 via the gate insulating film 10 and an impurity semiconductor formed on the main surface of the p-type well 2 on both sides of the gate electrode 11. And an area 12. Gate insulating film 10 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation. Gate electrode 11 is, for example, polycrystalline silicon film 1 having a thickness of 70 nm.
1a, a 50 nm-thick titanium nitride film 11b and a thickness 1
It can be a stacked film of a 00 nm tungsten film 11c. In addition, an n-type impurity, for example, arsenic or phosphorus is introduced into impurity semiconductor region 12.

A cap insulating film 13 made of a silicon nitride film is formed on the upper layer of the gate electrode 11 of the selection MISFET Qs, and the upper layer is covered with a silicon nitride film 14. The silicon nitride film 14 is also formed on the side wall of the gate electrode 11, and is used for a self-alignment process when forming a connection hole described later. The gate electrode 11 of the selection MISFET Qs functions as a word line of the DRAM, and a word line WL is formed on the upper surface of the isolation region 7.

On the other hand, n-channel MISFET Qn and p-channel MISFET Qp are formed on the main surfaces of p-type well 3 and n-type well 4, respectively.
A gate electrode 11 formed through the gate electrode 11
And impurity semiconductor regions 15 formed on the main surface of each well on both sides of the semiconductor device. The gate insulating film 10 and the gate electrode 11 are the same as described above. The impurity semiconductor region 15 includes a low-concentration impurity region 15a and a high-concentration impurity region 15b, and forms a so-called LDD (Lightly Doped Drain) structure. As the impurity introduced into the impurity semiconductor region 15, an n-type or p-type impurity is introduced depending on the conductivity type of the MISFET.

A cap insulating film 13 made of a silicon nitride film is formed on the gate electrode 11 of the n-channel MISFET Qn and the p-channel MISFET Qp, and a sidewall spacer 16 made of, for example, a silicon nitride film is formed on the side surface. .

Select MISFET Qs, n-channel MIS
The FET Qn and the p-channel MISFET Qp are covered with an interlayer insulating film 17. The interlayer insulating film 17 is made of, for example, a SOG (Spin On Glass) film 17a and a silicon oxide film (hereinafter referred to as a TEOS oxide film) formed by a plasma CVD method using TEOS (tetramethoxysilane) as a source gas by CMP (Chemical Mechanical Polishing). TEOS oxide film 17b and TEO planarized by
It can be a stacked film of the S oxide films 17c and 17d.

The bit line BL and the first layer wiring 18 are formed on the interlayer insulating film 17. The bit line BL and the first layer wiring 18 can be, for example, a laminated film of a titanium film 18a, a titanium nitride film 18b, and a tungsten film 18c. As a result, the resistance of the bit line BL and the first layer wiring 18 can be reduced, and the performance of the DRAM can be improved. The bit line BL and the first layer wiring 18 are
They are formed at the same time as described later. Thereby, the process can be simplified.

The bit line BL is connected via the plug 19 to the impurity semiconductor region 1 shared by the pair of select MISFETs Qs.
2 is connected. Plug 19 can be, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. Further, a titanium silicide film 20 is formed at a connection between the plug 19 and the bit line BL. Thereby, the connection resistance between the bit line BL and the plug 19 can be reduced, and the connection reliability can be improved.

In the titanium silicide film 20 of the present embodiment, nitrogen is in the range of 1 to 13 atomic%, for example, 1 to 13 atomic%.
3 atomic% is contained. As described above, the bit line connection hole BLCT has an aperture structure with respect to the bit line BL. However, in the present embodiment, as described later, nitrogen is contained in the titanium silicide film 20 by 1 to 3 times. Atomic%, the titanium silicide film 20 functions as an etching stopper when patterning the bit line BL, and the plug 19 is not excessively etched.
For this reason, a problem does not occur in the exposure focusing in the subsequent process, the process margin can be increased, and the reliability and yield of the DRAM can be improved. Also, since the titanium silicide film 20 is not etched, the lateral etching of the titanium silicide film 20 does not progress, and the bit line BL
And the plug 19 can be reliably maintained.
That is, in the conventional titanium silicide film containing no nitrogen, the titanium silicide film is excessively etched during the patterning of the bit line BL, and is also etched in the lateral direction to form a gap between the bit line BL and the plug 19. ,
Although this gap reduces the connection reliability between the bit line BL and the plug 19, such a case does not occur in the present embodiment. Thereby, the reliability of the DRAM can be improved while maintaining the connection reliability.

Although the titanium silicide film to which nitrogen is added is illustrated here, oxygen, carbon, or germanium may be added in a range of 1 to 13 atomic%. Also, instead of titanium silicide, a tungsten silicide film may be used. In this case, it is necessary that nitrogen, oxygen, carbon or germanium is added in a range of 1 atomic% to 13 atomic%. Further, it may be a cobalt silicide film. In this case, the addition of nitrogen, oxygen, carbon or germanium in the range of 1 to 13 atomic% is not essential. That is, nitrogen, oxygen,
Even a cobalt silicide film to which carbon or germanium is not added can function as an etching stopper when patterning the bit line BL. However, if nitrogen, oxygen, carbon or germanium in the range of 1 atomic% to 13 atomic% is added to the cobalt silicide film, the etching resistance is further improved. Nitrogen, oxygen, carbon or germanium is added to these titanium or tungsten silicide films, or cobalt, silicide films, or nitrogen, oxygen,
The fact that the etching resistance is improved by adding carbon or germanium is based on experimental studies by the present inventors. According to the results of the experimental study, the addition of nitrogen, oxygen, carbon, or germanium can increase the etching rate by 3%.
It is reduced to about two-thirds.

As will be described later, oxygen or carbon may be naturally mixed in during the formation of the silicide film. That is, when an organic gas containing oxygen or carbon is used as a source gas, or when oxygen in an oxide film (silicon oxide film) formed on a silicon surface is reduced by titanium or the like during silicide annealing and taken into the silicide film. Etc. In the silicide film of the present embodiment, 1 atomic% to 13 atomic% of impurities may be mixed by using such a process in which oxygen or carbon is mixed naturally.

The first layer wiring 18 is connected to the n
Channel MISFET Qn and p channel MISFE
It is connected to impurity semiconductor region 15 of TQp. Further, a titanium silicide film 20 is formed at a connection portion between the first-layer wiring 18 and the impurity semiconductor region 15. Thereby, the connection resistance between the first layer wiring 18 and the impurity semiconductor region 15 can be reduced, and the connection reliability can be improved.

Similarly to the above, the titanium silicide film 20 formed at the connection between the first layer wiring 18 and the impurity semiconductor region 15 also contains 1 to 13 atomic%, for example, 1 to 3 atomic% of nitrogen. It is a thing. By using the titanium silicide film 20 containing nitrogen as described above, the heat resistance at the connection portion can be improved. Also in this case, the content of nitrogen is preferably 1 to 3 atomic%. The deterioration of the heat resistance is observed as an increase in the contact resistance at the connection portion or an increase in the leakage current. However, if the titanium silicide film 20 containing nitrogen of the present embodiment is used, such an increase in the contact resistance or No increase in leakage current occurs. This is also based on the knowledge obtained as a result of the inventors' experimental study.

Note that the titanium silicide film 20 at the connection between the first layer wiring 18 and the impurity semiconductor region 15 also contains oxygen, carbon or germanium in the range of 1 to 13 atomic% as described above. Good. Also, instead of titanium silicide, a tungsten silicide film may be used. In this case, nitrogen, oxygen, carbon or germanium
It must be added in the range of atomic% to 13 atomic%. Further, it may be a cobalt silicide film.
In this case, the addition of nitrogen, oxygen, carbon or germanium in the range of 1 to 13 atomic% is not essential. That is, even with a cobalt silicide film to which nitrogen, oxygen, carbon, or germanium is not added, the heat resistance at the connection portion is improved. However, 1 atomic% in the cobalt silicide film
If nitrogen, oxygen, carbon or germanium in the range of １３13 atomic% is added, the heat resistance is further improved.

As will be described later, such an improvement in heat resistance can be achieved by preventing the connection portion from deteriorating in the heat treatment for forming the capacitor insulating film of the capacitor C, and by limiting the heat treatment to the formation of the capacitor insulating film. It is significant in that it is no longer applied.
Therefore, while realizing the capacitor C having a high storage capacity,
An increase in contact resistance and an increase in leak current at the connection portion can be suppressed.

The bit line BL and the first layer wiring 18 (M
1) is covered with a cap insulating film 22a made of a silicon nitride film and a sidewall spacer 22b, and further covered with an interlayer insulating film 23. The interlayer insulating film 23 is made of, for example, an SOG film 23a, a TE planarized by a CMP method.
It can be a laminated film of the OS oxide film 23b and the TEOS oxide film 23c.

A capacitor C for storing information is formed in the region A in the upper layer of the interlayer insulating film 23. An insulating film 24 is formed on the interlayer insulating film 23 in the region B in the same layer as the capacitor C. The insulating film 24 can be, for example, a silicon oxide film. When the insulating film 24 is formed in the same layer as the capacitor C, the region A and the region B
It is possible to prevent the occurrence of a step with the region. As a result, a sufficient depth of focus can be provided for photolithography, and the process can be stabilized to cope with fine processing.

The capacitor C includes a lower electrode 27 connected via a plug 26 to a plug 25 connected to the impurity semiconductor region 12 opposite to the impurity semiconductor region 12 connected to the bit line BL of the selection MISFET Qs; A capacitance insulating film 28 made of, for example, a silicon nitride film and tantalum oxide, and a plate electrode 29 made of, for example, titanium nitride
It is composed of

In the upper layer of capacitor C, for example, TEO
Second layer wiring 31 via insulating film 30 made of S oxide film
(M2) is formed. The second layer wiring 31 can be a laminated film of, for example, a titanium film 31a, an aluminum film 31b, and a titanium nitride film 31c.

The second layer wiring 31 is connected to the first layer wiring 18 via the plug 32. The plug 32 has an adhesive layer 32a made of a laminated film of, for example, a titanium film and titanium nitride.
And a tungsten film 32b formed by a CVD method.

The second layer wiring 31 is covered with an interlayer insulating film 33, and a third layer wiring 34 (M 3) similar to the second layer wiring 31 is formed above the interlayer insulating film 33. The interlayer insulating film 33 includes, for example, a TEOS oxide film 33a and an SOG film 33.
b and a laminated film of the TEOS oxide film 33c. The third-layer wiring 34 and the second-layer wiring 31 are connected by a plug 35 similar to the plug 32.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS. 5 to 1
FIG. 8 is a sectional view showing an example of a method of manufacturing a DRAM according to an embodiment of the present invention in the order of steps.

First, a p-type semiconductor substrate 1 is prepared, and a shallow groove 8 is formed in the main surface of the semiconductor substrate 1. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 9.
Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 8, thereby forming the isolation region 7.

Next, impurities are ion-implanted using the photoresist as a mask to form p-type wells 2 and 3, n-type well 4 and deep well 6 (FIG. 5).

Next, the gate insulating film 10 is formed in the active region where the p-type wells 2 and 3 and the n-type well 4 are formed by thermal oxidation.
Is formed, and a polycrystalline silicon film doped with impurities, a titanium nitride film, a tungsten film, and a silicon nitride film are sequentially deposited on the entire surface of the semiconductor substrate 1. Thereafter, the silicon nitride film, the tungsten film, the titanium nitride film, and the polycrystalline silicon film are patterned by using a photolithography technique and an etching technique, so that a gate electrode 11 (word line WL) and a cap insulating film 13 are formed. Further, impurities are ion-implanted using the cap insulating film 13, the gate electrode 11, and the photoresist as a mask to form an impurity semiconductor region 12 and a low-concentration impurity region 15a (FIG. 6).

Next, a silicon nitride film (not shown) is deposited on the entire surface of the semiconductor substrate 1, and a photoresist film (not shown) is formed only in a region (A region) where a memory cell is to be formed. Then, using the photoresist film as a mask,
The silicon nitride film is anisotropically etched to form a silicon nitride film 14 only on the semiconductor substrate 1 in the region A and, at the same time, a sidewall spacer 16 on the side wall of the gate electrode 11 in the region B. Further, impurities are ion-implanted in a self-aligned manner using the sidewall spacers 16 as a mask to form the high-concentration impurity regions 15b (FIG. 7).

Next, the SOG film 17 is formed on the entire surface of the semiconductor substrate 1.
After a is applied and cured, a TEOS oxide film 17b is deposited by a plasma CVD method. This TEOS oxide film is polished by the CMP method to flatten the surface. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, a TEOS oxide film 17c is further deposited to form an interlayer insulating film 17. This TEOS oxide film 17c is made of TEOS generated by CMP.
This is for repairing damage due to scratches on the oxide film 17b.

Next, connection holes are opened in the TEOS oxide films 17c and 17b and the SOG film 17a, plug-in implantation is performed, and then a polycrystalline silicon film doped with impurities is deposited, and this polycrystalline silicon film is subjected to CMP. To form plugs 19 and 25 (FIG. 8). This connection hole is opened by two-stage etching to open the semiconductor substrate 1.
Over-etching can be prevented.

Next, after forming the TEOS oxide film 17d, an opening is formed in the TEOS oxide film 17d so that the plug 19 to which the bit line BL is connected is exposed, and the impurity semiconductor regions of the n-channel MISFET Qn and the p-channel MISFET Qp are formed. 15 so that the interlayer insulating film 17 is exposed.
A connection hole 21 is formed (FIG. 9).

Next, a titanium film 18 is formed on the entire surface of the semiconductor substrate 1.
a is deposited. This deposited state is shown in a partially enlarged view of FIG. 10 (FIG. 10). 10 to 13, the left side shows the bit line connection hole BLCT, and the right side shows the connection hole CT between the first layer wiring M1 and the main surface of the semiconductor substrate 1.

The titanium film 18a is formed so as to contain 1 to 3 atomic% of nitrogen. Such a titanium film to which nitrogen is added can be deposited by a reactive sputtering method or a CVD method. The deposition conditions by the reactive sputtering method are as follows, for example. That is, titanium (Ti) is used as a sputtering target, and nitrogen (N ₂ ) gas and argon (Ar) gas are used as atmospheric gases. The sputtering pressure can be 1 mTorr to 10 mTorr, preferably 3 mTorr. The input power can be 1 kW to 20 kW, preferably 4 kW. The conditions for deposition by the CVD method are as follows. That is, TDMA is used as the CVD gas.
T (tetradimethylaminotitanium; Ti (N (CH ₃ )
_{2) 4)} or TDEAT; can be (tetra diethylamino titanium Ti (N (C ₂ H _{5) 2) 4)} organic source and ammonia, such as (NH _3). Also,
Titanium tetrachloride (TiCl ₄ ) and ammonia can also be used. As a forming method, IMP (Ion Metal Plas
ma) method can be used.

Next, the semiconductor substrate 1 is kept in a reduced pressure atmosphere and subjected to a heat treatment at 650 ° C. for one minute to cause a silicidation reaction between the titanium film 18 a containing nitrogen, the plug 19 and the semiconductor substrate 1, and to form a titanium silicide film 20. Is formed (FIG. 11). The thus formed titanium silicide film 20 contains about 1 to 3 atomic% of nitrogen.

Although the unreacted titanium film is left in the figure, it can be removed. The unreacted titanium film can be selectively removed using, for example, a solution obtained by mixing aqueous ammonia and aqueous hydrogen peroxide at a volume ratio of 1: 5.

Next, a titanium nitride film 18b is deposited (FIG. 12). The titanium nitride film 18b can be formed by a sputtering method.

Next, a tungsten film 18c is deposited by a blanket CVD method (FIG. 13). Blanket C
Since the VD method is used, the tungsten film can be satisfactorily embedded even in the fine connection hole 21.

Next, a silicon nitride film to be the cap insulating film 22a is deposited, and the silicon nitride film, the tungsten film 18c, the titanium nitride film 18b, and the titanium film 18a are patterned. FIG. 14 shows XIV-X in FIG.
An enlarged view of a section taken along the line IV is shown. (A) shows a cross-sectional view at the stage of FIG. 13, and (b) shows a state after patterning to form a bit line BL. In (b), the bit line connection hole BLCT has a completely open structure with respect to the bit line BL. However, in this embodiment, since the titanium silicide film 20 contains 1 to 3 atomic% of nitrogen, the titanium silicide film 20 has etching resistance when patterning the tungsten film 18c, the titanium nitride film 18b, and the titanium film 18a. The plug 19 is not etched excessively, and the titanium silicide film 20 is not etched in the lateral direction. Note that sulfur hexafluoride (SF ₆ ) gas can be used for etching the tungsten film 18c, and chlorine (Cl ₂ ) gas can be used for etching the titanium nitride film 18b.

The bit line BL is formed by such etching.
At the same time, a first layer wiring M1 (18) is also formed.

Further, a silicon nitride film is deposited and anisotropically etched to form a sidewall spacer 22b (FIG. 15).

Next, the SOG film 23 on the entire surface of the semiconductor substrate 1
After a is applied and cured, a TEOS oxide film 23b is deposited by a plasma CVD method. This TEOS oxide film 23b is polished by the CMP method, and its surface is flattened. As a result, the focus margin in the subsequent photolithography process can be improved, and a fine connection hole can be formed. After cleaning the surface, add TEO
An S oxide film 23c is deposited, and an interlayer insulating film 23 is formed.
This TEOS oxide film 23c is for covering a scratch on the TEOS oxide film 23b formed by CMP.

Next, a connection hole is opened in the interlayer insulating film 23,
A polycrystalline silicon film doped with impurities is deposited, and this polycrystalline silicon film is polished by a CMP method to form a plug 26.
Is formed (FIG. 16).

Next, a silicon nitride film 23d is formed only in the memory cell array region A, an insulating film 24 is deposited, a groove is formed in a region where the capacitor C is formed, and a plug 26 is formed.
And depositing a polycrystalline silicon film covering this groove,
The lower electrode 27 of the capacitor C is formed by removing the polycrystalline silicon film other than the groove. After that, the insulating film formed in the insulating film 24 and the lower electrode 27 in the memory cell array region A is removed by wet etching.
7 is exposed in a cylindrical shape. At this time, the silicon nitride film 23d can be used as a mask for wet etching. Thereafter, the surface of the lower electrode 27 is nitrided or oxynitrided, and then a tantalum oxide film is deposited. Here, a heat treatment is performed on the tantalum oxide film to crystallize the tantalum oxide film to make a stronger dielectric, thereby forming the capacitor insulating film 28. In addition,
In the heat treatment for baking the tantalum oxide film, the heat resistance at the bottom of the connection hole 21 is mainly a problem. However, in the first embodiment, since the measures already described are taken, even if such a heat treatment is performed, generation of a leak current,
Problems such as an increase in contact resistance do not occur. Further, a titanium nitride film is deposited and patterned, and a plate electrode 2
9 (FIG. 17).

Next, a TEOS oxide film is deposited on the entire surface of the semiconductor substrate 1 to form an insulating film 30, and a connection item connected to the first layer wiring 18 is opened in the direct peripheral circuit region B and the indirect peripheral circuit region C. , Plug 32 is formed. The plug 32
It can be formed by depositing a stacked film of titanium and titanium nitride over the entire surface of the semiconductor substrate, further depositing a tungsten film by a blanket CVD method, and then etching back the tungsten film, the titanium nitride film, and the titanium film. Note that titanium and titanium nitride can be formed by a sputtering method, but can also be formed by a CVD method. Further, a titanium film 31a, an aluminum film 31b, and a titanium nitride film 31c are deposited on the entire surface of the semiconductor substrate 1 by a sputtering method, and are patterned to form the second layer wiring 31 (FIG. 18).

Finally, a TEOS oxide film 33a, an SOG film 33b and a TEOS oxide film 33c are deposited to form an interlayer insulating film 33, a plug 35 is formed in the same manner as the second layer wiring 31, and a third layer wiring is formed. 34 is formed, and the DRAM shown in FIG. 2 is almost completed.

According to the DRAM of the first embodiment, since the titanium silicide film 20 contains nitrogen, when the bit line BL is patterned, the titanium silicide film 20 contains titanium silicide even if the bit line connection hole BLCT has an opening structure. The film 20 functions as an etching stopper, so that excessive etching of the plug 19 and lateral etching of the titanium silicide film 20 do not occur. Therefore, the following possible steps are facilitated, the connection reliability between the bit line BL and the plug 19 is improved, and the DRA
The reliability and yield of M can be improved.

Since the titanium silicide film 20 below the connection hole 21 (CT) contains nitrogen, the heat resistance at the bottom of the connection hole is improved, and a high temperature is applied when forming the capacitor insulating film 28. However, an increase in the connection resistance and an increase in the leak current at the connection portion between the first layer wiring M1 and the semiconductor substrate 1 do not occur. This situation will be described using data. FIGS. 19 and 20 are graphs showing experimental results examined by the present inventors. FIG. 19 shows changes in contact resistance (contact resistance) with respect to nitrogen content, and FIG. 20 shows leakage with respect to nitrogen content. The change in current is shown. 19A and 20A show the case of an n-type substrate, and FIG. 19B shows the case of a p-type substrate.

As is clear from the figure, in the case of a titanium silicide film containing no nitrogen (when the nitrogen content is 0%)
The contact resistance and the leak current increase, and the contact resistance and the leak current decrease as the nitrogen content increases. However, the contact resistance and the leak current both increased from about the nitrogen content exceeding 13%, and it can be seen that the effect was not obtained with an excessively large nitrogen content. Therefore, there is an optimum value for the nitrogen content, and it can be said that the range is 1 atomic% to 13 atomic%, preferably 1 atomic% to 3 atomic%.

In the present embodiment, the case where the material of the bit line BL and the first layer wiring 18 (M1) is titanium nitride and tungsten is illustrated, but a single layer film of a titanium nitride film may be used. In this case, the titanium silicide film 2
Numeral 0 is exposed to a fluorine-based gas which is an etching gas for a titanium nitride film. However, since the titanium silicide film 20 contains nitrogen, it has etching resistance, and there is no problem. However, cobalt silicide or tungsten silicide is more effective.

The bit line BL and the first layer wiring 18
Is titanium nitride and tungsten, it is preferable to use cobalt silicide or cobalt silicide containing nitrogen, oxygen, carbon or germanium because of its excellent etching resistance.

(Embodiment 2) FIGS. 21 to 23 are enlarged sectional views showing an example of a method of manufacturing a DRAM according to another embodiment of the present invention. 21 to 23, the left side shows the portion of the bit line connection hole BLCT, and the right side shows the portion of the connection hole CT between the first layer wiring M1 and the main surface of the semiconductor substrate 1.

The DRAM of the present embodiment is similar to the DRAM of the first embodiment.
The DRAM is different from the DRAM in that the structure of the bit line BL and the first layer wiring, the bit line connection hole BLCT and the plug formed in the connection hole 21 are provided, but other configurations and manufacturing methods are the same. Therefore, only the differences will be described below.

The method of manufacturing the DRAM of the present embodiment is almost the same as the method of manufacturing the DRAM of the first embodiment shown in FIG. However, the titanium silicide film 20 in the present embodiment does not need to contain nitrogen, oxygen, carbon, or germanium. Needless to say, nitrogen, oxygen, carbon, or germanium may be contained as in Embodiment 1, and cobalt silicide or tungsten silicide may be used.

After the tungsten film 18c is deposited as shown in FIG.
c, the titanium nitride film 18b and the titanium film 18a are etched back, and the bit line connection hole BLCT and the connection hole 21 are etched.
Other than the above-mentioned laminated film is removed. Thus, the bit line plug BP is formed in the bit line connection hole BLCT and the wiring plug CTP is formed in the connection hole 21 (FIG. 21). For the etch back, an etch back method or a CMP method can be used.

When the bit line plug BP and the wiring plug CTP are formed by using the CMP method, the TE in which the bit line connection hole BLCT and the connection hole 21 are formed is formed.
The surface of the OS oxide film 17d needs to be flattened. Further, it is preferable that the surface of the TEOS oxide film 17c on which the plugs 19 and 25 are formed is also flattened. Since the underlying layer or the layer on which the bit line plug BP and the wiring plug CTP are formed is planarized, the thickness of each conductive film for forming the bit line plug BP and the wiring plug CTP is reduced, In addition, the polishing load can be reduced by reducing the polishing film thickness.

Next, a metal film M is deposited on the entire surface of the semiconductor substrate 1 (FIG. 22), and thereafter, the metal film M is patterned to form a bit line BL and a first layer wiring M1 (FIG. 2).
3). As the metal film M, for example, a single-layer film of tungsten or molybdenum can be used.

The subsequent steps are the same as in the first embodiment.

According to the DRAM of this embodiment, since the bit line plug BP is formed, the bit line plug BP functions as a kind of mask when patterning the metal film M, and the titanium silicide film 20 is formed. And the plug 19 is not etched. Thus, even if the bit line BL has an aperture structure, excessive etching of the plug 19 and lateral etching of the titanium silicide film 20 can be prevented. That is, when the bit line BL is a single-layer film made of a tungsten film, the tungsten portion of the bit line plug BP is etched when the bit line plug BP contains tungsten. However, as described later, since the thickness of the bit line BL can be reduced, the bit line B
The overetching at the time of etching the metal film M to be L may be performed by an amount corresponding to the film thickness. That is, since the film thickness is small, the amount of overetching of the metal film M may be small. For this reason, even when the bit line plug BP serving as the base contains tungsten when etching the metal film M, the etching amount of the tungsten is small and the etching does not reach the plug bottom. As a result, excessive etching of the silicide layer is prevented.

When the bit line BL is made of molybdenum, the metal film M serving as the bit line BL is etched under a condition that the etching rate of molybdenum is higher than that of tungsten. The metal film M can be selectively etched with respect to the bit line plug BP. That is, the bit line plug BP can function as an etching stopper for the metal film M. Thereby, even if the bit line BL has an opening structure with respect to the bit line plug BP, the etching of the silicide film can be prevented without etching the bit line plug BP.

In addition, since the bit line BL is formed of a tungsten single layer film, the resistance of the bit line BL can be reduced. In other words, in the past, a titanium nitride film had to be used due to the embedding property in the connection hole. However, in this embodiment, the bit line BL is compared with the titanium nitride film because the connection hole is filled with a plug. Thus, only a low-resistance tungsten film can be obtained. Since the titanium nitride film has difficulty in processing, it is effective from the viewpoint of workability to form the bit line BL only with the tungsten film which is easy to process.

Since the bit line plug BP is formed in the bit line connection hole BLCT in advance, it is not necessary to bury the bit line connection hole BLCT with the metal film M. Therefore, the thickness of the metal film M is reduced. be able to. As a result, the capacitance between the bit lines BL can be reduced, and the detection sensitivity of the stored charge can be improved. For example, if the diameter of the connection hole is 300 nm, conventionally, the thickness of the metal film M is 1
50 nm or more was required. However, in this embodiment mode, the thickness can be reduced to 150 nm or less and a tungsten film having high conductivity can be used, so that the thickness can be further reduced.

The shape of the bit line BL is as shown in FIG.
It has a linear shape and is arranged close to. This close proximity is because the memory cell region is patterned with the minimum processing size, and the pattern width is also formed with the minimum processing size. Since the bit line BL has a linear shape, the resolution of photolithography is improved, and the effect of reducing the width of the bit line BL and reducing the capacitance between the bit lines BL is as described in the first embodiment. There is naturally a limit imposed by the resolution of photolithography in an attempt to reduce the resolution. For this reason, it is difficult to reduce the line capacitance between the bit lines BL by increasing the interval between the bit lines BL. On the other hand, in the present embodiment, the capacitance is reduced by reducing the thickness of the bit line BL, and the effect of the capacitance reduction of the first embodiment or more can be expected.

As shown in FIG. 24, a titanium nitride film 50 can be used for the bit line plug BP instead of the above-described laminated film of titanium nitride and tungsten. In this case, since the titanium nitride film 50 has a large etching selectivity with respect to the tungsten film constituting the bit line BL, the bit line plug BP made of the titanium nitride film 50 is used as an etching stopper when patterning the bit line BL. Can be used. Such etching is performed by SF ₆
Is used as an etching gas. In such a case, the processing margin of the bit line BL can be increased. Further, the titanium nitride film 50 may be replaced with a tungsten nitride film. Also in this case, the tungsten nitride film can be used as an etching stopper when etching the tungsten constituting the bit line BL.

When the bit line plug BP is made of a laminated film of titanium nitride and tungsten, or a titanium nitride film or a tungsten nitride film, and when the bit line BL is made of molybdenum, the bit line plug BP is etched. Of course, it can function as an etching stopper.

(Embodiment 3) FIGS. 25 to 28 are enlarged sectional views showing an example of a method of manufacturing a DRAM according to still another embodiment of the present invention.

The manufacturing method of the present embodiment is similar to that of the first embodiment.
Are substantially the same as those shown in FIG. However, TE
The OS oxide film 17d is formed slightly thicker (FIG. 25).

Next, a titanium film 18a is deposited, heat-treated in the same manner as in the first embodiment to form a titanium silicide film 20, and a titanium nitride film 18b is deposited (FIG. 26). Here, it is not necessary to add nitrogen or oxygen to the titanium silicide film 20, but it goes without saying that it may be added.

Next, a tungsten film 18c is deposited by a blanket CVD method (FIG. 27). At this time, the tungsten film 18c, the titanium nitride film 18b and the titanium film 1
8a thickness plus, that is, if the thickness of the bit line BL and L _1, the distance L ₂ plus the thickness L ₁ of the TEOS oxide film 17d, and, between the diameter D of the bit line contact hole BLCT Include L ₁ × (1 + OVE) <L ₂ and L ₁ > D
/ 2 are set so as to satisfy the relationship of / 2. Note that OVE is an overetch amount when patterning the bit line BL. It is appropriate that the overetch amount is 0.5.

As long as such a relationship is satisfied, a tungsten film 18c, a titanium nitride film 18b, and a titanium film 18a are formed using a photoresist film 40 as shown in FIG.
Does not progress to the bottom of the bit line connection hole BLCT. As a result, even if the bit line BL has an aperture structure, the titanium silicide film 20 and the plug 19 are not etched.

The method for etching the tungsten film 18c, the titanium nitride film 18b, and the titanium film 18a is as described in the first embodiment.

According to the present embodiment, etching of titanium silicide film 20 and plug 19 is prevented, and the same effect as in the first and second embodiments can be obtained.

(Embodiment 4) FIG. 29 is a sectional view showing an example of a DRAM according to another embodiment of the present invention. FIGS. 30 and 31 show the DR of the present embodiment.
It is sectional drawing which showed an example of the manufacturing method of AM.

The DRAM of the present embodiment is substantially the same as the first embodiment in the region A and the region B in FIG. In FIG. 29, particularly, the indirect peripheral circuit area C
In the DRAM of the present embodiment, the diameter of the connection hole 21 in the region C is the same as the diameter of the connection hole 21 in the region B.

The manufacturing method of the DRAM of the present embodiment is almost the same as the manufacturing method of the first embodiment. However, FIG.
As shown in FIG. 0, when the connection hole 21 is opened, the connection hole 21 in the region B as the direct peripheral circuit and the connection hole C in the indirect peripheral circuit
The connection hole 21 in the region is opened with the same diameter.

Next, FIGS. 10 to 1 in the first embodiment.
3 will be described. Here, FIG. 10 to FIG. 13 show a region B which is a direct peripheral circuit and a region C which is an indirect peripheral circuit in common.

A titanium film 18a is deposited on the entire surface of the semiconductor substrate 1. This deposited state is shown in a partially enlarged view of FIG. 11 (FIG. 10). When the thickness of the titanium film 18a on the interlayer insulating film 17 is compared with the thickness at the bottom of the connection hole 21, the thickness at the bottom of the connection hole 21 is smaller. This is because the titanium film 18a is formed by using a sputtering method.
This is because the thickness at the bottom becomes thinner depending on the viewing angle of the connection hole 21 from the bottom, that is, the larger the opening, the thicker the bottom. However, in the present embodiment, the opening of the connection hole 21 is uniform in both the direct peripheral circuit region B and the indirect peripheral circuit region C. Therefore, the thickness of the titanium film 18a at the bottom of the connection hole 21 in both regions is the same.

Next, the semiconductor substrate 1 is annealed to cause a silicide reaction between the semiconductor substrate 1 and the titanium film 18a (FIG. 11). Thus, a titanium silicide layer 20 is formed at the bottom of the connection hole 21. At this time, the titanium film 18a
Is uniform irrespective of whether it is the direct peripheral circuit region B or the indirect peripheral circuit region C, the entire titanium film 18a at the bottom of the connection hole 21 can be reacted,
No unreacted titanium remains. This allows
Due to a thermal process that occurs in a later process, an unexpected silicide reaction does not occur, and the connection reliability in the connection hole 21, that is, the heat resistance can be improved.

Next, a titanium nitride film 18b is deposited (FIG. 12). The titanium nitride film 18b can also be formed by a CVD method or a sputtering method.
Similarly, a uniform film thickness can be realized at the bottom of the connection hole 21. Accordingly, a decrease in heat resistance due to a variation in the thickness of the titanium nitride film 18b can be suppressed, and connection reliability at the connection hole 21 can be improved.

Next, a tungsten film 18c is deposited by a blanket CVD method (FIG. 13). Blanket C
Since the VD method is used, the tungsten film can be satisfactorily embedded even in the fine connection hole 21.

After that, a silicon nitride film is deposited and patterned to form a bit line BL and a first layer wiring M1,
A cap insulating film 22a is formed, and a sidewall spacer 22b is formed (FIG. 31).

The subsequent steps are the same as in the first embodiment.

In such a DRAM, since the diameter of the connection hole 21 is the same over the entire surface of the semiconductor substrate 1, the titanium silicide film 20 having excellent heat resistance can be formed.
That is, since the titanium film 18a is formed by the sputtering method, the titanium film 1a at the bottom of the connection hole depends on the opening diameter of the connection hole.
8a is different. In the case where the titanium silicide film 20 is formed by performing a heat treatment on the titanium films 18a having different thicknesses, unreacted titanium is left partially. Such unreacted titanium tends to remain in the connection hole having a large opening diameter. This is because the larger the opening diameter, the thicker the titanium film at the bottom of the connection hole. The present inventors have recognized that the residual titanium reacts in a subsequent thermal process and causes erosion of the cavity and the semiconductor substrate 1, which is related to an increase in leak current and an increase in contact resistance.

That is, in the DRAM of this embodiment, the thickness of the titanium film 18a at the bottom of the connection hole 21 is made uniform by making the diameters of all the connection holes 21 uniform. Thus, unreacted titanium after the silicide reaction is eliminated, and the heat resistance (resistance to increase in leakage current and resistance to increase in contact resistance) at the connection hole is improved.

Incidentally, the thickness of the titanium film 18a of the DRAM of the present embodiment is shown as an example. When the titanium film 18a having a thickness of 50 nm is deposited by the collimation sputtering method,
At the bottom of the connection hole 21, the thickness of each connection hole 21 was 10 nm. 650 is applied to the titanium film 18a.
As a result of heat treatment at ℃ for 1 minute, no residual titanium was detected. Also, when forming the capacitor C later, 8
Although heat treatment was performed at 00 ° C. for 11 minutes, no increase in contact resistance or increase in leak current at the portion of the connection hole 21 was particularly observed.

In the present embodiment, an example has been described in which the diameter of the connection hole 21 is made uniform. However, when the depths of the connection holes 21 are different, the diameter may be determined so that the aspect ratios match. it can. Thereby, the titanium film thickness at the bottom of the connection hole can be made uniform, and the heat resistance at the connection hole can be improved.

In this embodiment, the bit line plug BP and the wiring plug CTP are different from those of the second embodiment.
May be created by the CMP method.

(Embodiment 5) FIG. 32A is a plan view showing a part of an indirect peripheral circuit of a semiconductor integrated circuit device according to still another embodiment of the present invention, and FIG. )
Is an equivalent circuit diagram thereof.

In this embodiment, an output buffer is shown as an example. The output buffer of this embodiment is an n-channel M
Four ISFETs, four p-channel MISFETs are connected in parallel, and an n-channel MISFET and a p-channel MISFET are connected in series to form a CMOS inverter.

The n-channel MISFET is formed in an n-diffusion region 101 in which an n-type impurity is diffused, and the p-channel MISFET is formed in a p-diffusion region 102 in which a p-type impurity is diffused.

N diffusion region 101 and p diffusion region 102
A gate electrode 103 is formed on each gate electrode 103.
Are connected to each other to form an input unit 104.

Source / drain regions are formed on both sides of the gate electrode 103, and one source / drain region of each MISFET is connected to a wiring 10 connected via a connection hole 105.
6 to a power terminal 107 or to a ground terminal 109 by a wiring 108 connected through a connection hole 105. The other source / drain region is connected to the contact hole 1.
The output unit 111 is connected by a wiring 110 connected via the input / output unit 05. Note that the p-channel MISFET has a larger gate width because its current driving capability is lower than that of the n-channel MISFET.

Here, the connection hole 105 is formed so as to have the same diameter in both the direct peripheral area and the indirect peripheral area, as described in the fourth embodiment. As described above in Embodiment 4, the heat resistance of the connection hole can be improved.

However, when a drive current capacity is required as in the present embodiment, the contact area at the bottom of the connection hole is reduced, and the contact resistance is increased, which may obstruct current driving. .

Therefore, in the present embodiment, connection hole 105
Are arranged in two rows in the width direction of the gate electrode to suppress an increase in contact resistance. As a result, the current capacity of the buffer can be increased, and sufficient operation can be ensured even at a large current.

In the present embodiment, the portion where the connection holes 105 are arranged in two rows is the wiring 106 or the wiring 1 connected to the power supply terminal 107 or the ground terminal 109.
08 is limited to the portion where the wiring is connected to the output unit 111, and the connection holes 105 are arranged in one line in the portion where the wiring 110 connected to the output unit 111 is laid out. This is because the connection hole 105
Are arranged in two rows, although the contact resistance is reduced, the contact area between the wiring and the semiconductor substrate is increased, and the substrate capacitance is added to the wiring, and the response performance of the output signal is reduced.

As described above, according to the present embodiment, when a large current capacity is required, the contact holes are arranged in two rows to reduce the contact resistance, while the contact holes are required in a portion where the signal response performance is required. By arranging 105 in one row, it is possible to improve both the current capacity and the response performance. Needless to say, such an effect can be obtained together with the improvement of the heat resistance in the connection hole 105.

Although the example in which the connection holes 105 are arranged in two rows is shown here, the connection holes 105 may be arranged in two or more rows. In addition, since the layout is relatively large in the indirect peripheral circuit region, it is relatively easy to dispose a plurality of rows of connection holes 105 as in the second embodiment, which is a major obstacle to an increase in layout area. No.

(Embodiment 6) FIGS. 33 to 36 are enlarged sectional views showing an example of a method of manufacturing a DRAM according to another embodiment of the present invention. 33 to 36,
Only the peripheral circuit is shown.

The DRAM of the present embodiment is similar to that of the first embodiment.
DRAM of the first embodiment is different from the DRAM of the first embodiment except that the structure and the forming method of the titanium silicide film are different.
Is the same as the structure and manufacturing method. Therefore, only the differences will be described below. The method of manufacturing the DRAM of the present embodiment is the same as that of the DRAM of the first embodiment.
9 is substantially the same up to the manufacturing method in FIG.

After forming the connection holes 21, a titanium film 18a is deposited (FIG. 33). The titanium film 18a can be deposited by, for example, a collimation sputtering method. In addition, titanium film 1
8a has a thickness of 10 to 2 at the bottom of the connection hole 21;
Deposit to a thickness of 0 nm.

Next, a heat treatment is performed in the same manner as in the first embodiment to cause the titanium film 18a to react with the silicon of the semiconductor substrate 1 to form a titanium silicide film 20 (FIG. 34). In the formation of the titanium silicide film 20, heat treatment is performed so that all the titanium at the bottom reacts so that residual titanium does not occur at the bottom of the connection hole 21.

If the thickness of the titanium film 18a at the bottom of the connection hole 21 is set to 10 to 20 nm and all of them are reacted, the thickness of the titanium silicide film 20 is in the range of 15 to 30 nm. By such a silicidation reaction, the entire titanium film 18a at the bottom of the connection hole 21 is silicided,
No residual titanium is present. Thus, the heat resistance of the contact portion can be improved by the absence of the residual titanium. If residual titanium is present, the residual titanium is silicidized by a subsequent thermal process, and the thickness of the titanium silicide film 20 is increased. In the present embodiment, however, the thickness of the titanium silicide film 20 is reduced by a subsequent thermal process. Does not increase. The fact that the thickness of the titanium silicide film 20 does not increase suppresses an increase in the connection resistance of the contact portion as described below.

The thickness of the titanium silicide film 20 is set to 15 to 3
By setting the range to 0 nm, the contact resistance at the bottom of the connection hole 21 can be reduced. The change in the value of the contact resistance depending on the thickness of the titanium silicide film 20 is as follows.
Based on the findings of the present inventors through experimental studies. This finding will be described with reference to FIG. FIG. 37 is a graph showing the relationship between the contact resistance and the thickness of the titanium silicide film 20 at the bottom of the connection hole 21. FIG.
(B) shows the case of p-type. Regardless of the n-type or p-type case, when the thickness of the titanium silicide film 20 is 15 nm or less, the contact resistance increases. This indicates that a film thickness of about 15 nm is necessary to secure a low connection resistance, and that if there is no certain thickness, the function as a silicide film cannot be exhibited and the resistance cannot be reduced.
On the other hand, in the case of the p-type, the contact resistance increases as the thickness of the titanium silicide film 20 increases. This is considered to reflect the impurity concentration profile of the high concentration impurity region 15b. That is, in the p-type high-concentration impurity region 15b, the impurity concentration is high in the surface region, and decreases as the depth increases. In such an impurity concentration profile, if a thick titanium silicide layer is formed, the titanium silicide layer is formed in a region having a low impurity concentration, that is, a deep region of the high concentration impurity region 15b, and a region having a high impurity concentration and a low resistance is formed. It is considered that the phenomenon of being taken into the silicide layer occurs. In such a case, the phenomenon that the resistance of the high-concentration impurity region 15b is not sufficiently reduced and the connection resistance eventually increases appears.

On the other hand, in the case of the n-type, even if the thickness of the titanium silicide film 20 is increased, no remarkable increase in the contact resistance is observed. This is because the n-type high concentration impurity region 1
In 5b, the impurity profile does not depend on the depth,
It is considered to reflect that it is kept almost constant. Therefore, in the case of the n-type, even if the thickness of the titanium silicide film 20 is slightly increased, it does not affect the increase in the contact resistance. This is because the titanium silicide film 2 on the upper surface of the plug 19 connected to the bit line BL in the memory cell region
0 is convenient. That is, the depth of the opening formed on the plug 19 is shallow, and the aspect thereof is lower than that of the connection hole 21. Therefore, the thickness of the titanium film 18a at the bottom of the opening is larger than that at the bottom of the connection hole 21. Therefore, the thickness of the titanium silicide film 20 formed on the upper surface of the plug 19 is increased. However, the selection MISFET Qs for selecting a memory cell is an n-channel type,
The impurity introduced into 9 is an impurity showing n-type conductivity. Therefore, the titanium silicide film 2 on the upper surface of the plug 19
Even if the film thickness of "0" becomes somewhat thick, it is convenient without increasing the connection resistance.

The titanium silicide film 20 does not need to contain nitrogen, oxygen, carbon or germanium, but may contain nitrogen, oxygen, carbon or germanium as in the first embodiment. In addition, titanium film 1
Instead of 8a, a tungsten film or a cobalt film may be used to form cobalt silicide or tungsten silicide.

Next, a titanium nitride film 18b is deposited as in the first embodiment (FIG. 35), and a tungsten film 18c is deposited as in the first embodiment (FIG. 36).

The subsequent steps are the same as in the first embodiment.

According to the present embodiment, the contact resistance at the bottom of connection hole 21 can be reduced, and the heat resistance of the contact portion can be improved.

Note that, as in the first embodiment, the titanium nitride film 18b and the tungsten film 18c may be replaced with a single-layer film of a titanium nitride film or a single-layer film of a tungsten nitride film. Further, the titanium silicide film 20 of the present embodiment can be applied to the second embodiment.

(Embodiment 7) FIGS. 38 to 41 are enlarged sectional views showing an example of a method of manufacturing a DRAM according to still another embodiment of the present invention. 38 to 41, only the peripheral circuit portion is shown.

The DRAM of the present embodiment is similar to that of the sixth embodiment.
The structure and manufacturing method of the DRAM of the sixth embodiment are the same as those of the DRAM except that the method of forming the titanium silicide film is different from that of the DRAM. Therefore, only the differences will be described below. DR of this embodiment
The method of manufacturing the AM is almost the same as that of the DRAM of the sixth embodiment up to the method of FIG. However, in the present embodiment, the thickness of the titanium film 18a is 10 nm or more, that is, the thickness of the titanium silicide film after the heat treatment is 15 nm.
nm or more, and is not particularly limited. Therefore, the thickness of the titanium film 18a may be 20 nm or more (FIG. 38).

Next, a heat treatment is performed in the same manner as in the sixth embodiment to form a titanium silicide film 20 (FIG. 39). However, all of the titanium film 18a at the bottom of the contact hole 21 is not silicided, and the thickness of the titanium silicide film 20 is 15 to
The heat treatment time and temperature are controlled so as to be 30 nm. Thus, the thickness of the titanium silicide film 20 is set to 15 to
By setting the thickness to 30 nm, an effect of suppressing an increase in connection resistance can be obtained as described in the sixth embodiment.

In the case of the present embodiment, unreacted titanium remains at the bottom of connection hole 21 as shown in FIG. As described above, such unreacted titanium residue lowers the connection reliability due to the subsequent heat treatment step. Therefore, in this embodiment, unreacted titanium is selectively etched and removed by, for example, a wet etching method (FIG. 40). By removing the unreacted titanium by etching as described above, it is possible to prevent the titanium from remaining and prevent the reliability of the connection portion from being lowered by the subsequent heat process, that is, the heat resistance.

Next, as in the sixth embodiment, a titanium nitride film 18b and a tungsten 18c are deposited (FIG. 4).
1). Subsequent steps are the same as in the sixth embodiment.

According to the present embodiment, the connection resistance at the bottom of the connection hole 21 can be reduced and the connection reliability (heat resistance) can be improved.

The titanium silicide film 20 does not need to contain nitrogen, oxygen, carbon or germanium, but may contain nitrogen, oxygen, carbon or germanium as in the first embodiment. In addition, titanium film 1
As in the first embodiment, cobalt silicide or tungsten silicide may be formed using a tungsten film or a cobalt film instead of 8a.

Further, as in the second embodiment, the titanium nitride film 18b and the tungsten film 18c may be replaced with a single layer of a titanium nitride film or a single layer of a tungsten nitride film. Further, the titanium silicide film 20 of the present embodiment can be applied to the second embodiment.

(Embodiment 8) FIG. 42 is an enlarged sectional view showing an example of a method of manufacturing a DRAM according to another embodiment of the present invention. FIG. 42 shows only the peripheral circuit portion.

The DRAM of the present embodiment is similar to that of the first embodiment.
This is different from the DRAM in the structure of the bit line BL and the first layer wiring M1. In the present embodiment, titanium silicide layer 20 is not formed on the main surface of semiconductor substrate 1. Therefore, only the differences will be described below.

In the present embodiment, the bit line BL and the first layer wiring M1 are made of titanium silicide film 51, titanium nitride film 1
8b and a tungsten film 18c. The titanium silicide film 51 replaces the titanium silicide layer 20 in the first to seventh embodiments, and has a function of reducing the connection resistance between the bit line BL and the first layer wiring M1 and the plug 19 or the semiconductor substrate 1.

Titanium silicide film 51 of the present embodiment
Can be formed by the sputtering method or the CVD method after forming the connection hole 21 as in the first embodiment. Further, the thickness of the titanium silicide film 51 can be in a range of 15 to 30 nm.

According to the DRAM of the present embodiment, the connection resistance at the bottom of connection hole 21 can be reduced by titanium silicide film 51, and since there is no excess titanium remaining, the connection at the bottom of connection hole 21 is reduced. Reliability (heat resistance) is improved.

The titanium silicide film 51 does not need to contain nitrogen, oxygen, carbon or germanium, but may contain nitrogen, oxygen, carbon or germanium as in the first embodiment. In addition, titanium film 1
As in the first embodiment, cobalt silicide or tungsten silicide may be formed using a tungsten film or a cobalt film instead of 8a.

As in the second embodiment, the titanium nitride film 18b and the tungsten film 18c may be replaced with a single layer of a titanium nitride film or a single layer of a tungsten nitride film. Needless to say, the bit line plug BP and the wiring plug CTP may be formed after the step of FIG. 42 as in the second embodiment.

(Embodiment 9) FIGS. 43 and 44 show
FIG. 11 is an enlarged sectional view showing an example of a method for manufacturing a DRAM according to still another embodiment of the present invention. FIG. 43 and FIG.
In FIG. 4, only the peripheral circuit portion is shown.

The DRAM of the present embodiment is similar to that of the first embodiment.
This is different from the DRAM in the structure of the bit line BL and the first layer wiring M1. In the present embodiment, the method of forming titanium silicide layer 20 is different. Therefore, only the differences will be described below.

The method of manufacturing the DRAM of the present embodiment is almost the same as the method of manufacturing the DRAM of the sixth embodiment shown in FIG. However, in the present embodiment, the thickness of the titanium film 18a is 10 nm or more, that is, the thickness of the titanium silicide film after the heat treatment is 15 nm or more, and is not particularly limited. Therefore, the thickness of the titanium film 18a may be 20 nm or more.

Next, a polycrystalline silicon film 52 is deposited (FIG. 43). The polycrystalline silicon film 52 has a function of not reacting with an excess titanium film to generate residual titanium during the heat treatment described below.

Next, heat treatment is performed in the same manner as in Embodiment 6 (FIG. 44). As a result of this heat treatment, a part (bottom side) of the titanium film 18a at the bottom of the contact hole 21 reacts with silicon of the semiconductor substrate 1 to form a titanium silicide film 20, and another part of the titanium film 18a (top side) ) Is a polycrystalline silicon film 52
And a titanium silicide film 52a is formed. As a result, the titanium film 18a reacts with the polycrystalline silicon film 52.
Is consumed, and the bottom surface of the remaining titanium film 18a is consumed for reaction with silicon of the semiconductor substrate 1. Therefore, the silicide layer is not formed up to the deep region of the high-concentration impurity region 15b of the semiconductor substrate 1, and the connection resistance does not increase. On the other hand, even if the thickness of the titanium film 18a is large, no residual titanium is formed, and the heat resistance (connection reliability) of the connection portion is kept high.

A part of the titanium film 18a that has not reacted with the polycrystalline silicon film 52 remains on the side wall of the connection hole 21 and the upper surface of the TEOS oxide film 17d. There is no fear that connection reliability is impaired. That is, as long as there is no residual titanium at the bottom of the connection hole 21, there is no decrease in reliability due to the subsequent heating step. That is, in the present embodiment, the connection holes 21
So that there is no residual titanium at the bottom of the
The titanium film 18a and the polycrystalline silicon film 52 are formed so that the formed silicide layer is not formed deep in the semiconductor substrate 1.
May be selected. The thickness of the polycrystalline silicon film 52 can be formed, for example, smaller than the thickness of the titanium film 18a.

Subsequent steps are the same as in the sixth embodiment.

According to the present embodiment, the connection resistance at the bottom of connection hole 21 can be reduced, and the reduction in connection reliability (heat resistance) due to the subsequent heating step can be suppressed.

The titanium silicide film 20 does not need to contain nitrogen, oxygen, carbon or germanium, but may contain nitrogen, oxygen, carbon or germanium as in the first embodiment. In addition, titanium film 1
As in the first embodiment, cobalt silicide or tungsten silicide may be formed using a tungsten film or a cobalt film instead of 8a.

As in Embodiment 2, the titanium nitride film 18b and the tungsten film 18c may be replaced with a single-layer film of a titanium nitride film or a single-layer film of a tungsten nitride film. Further, the titanium silicide film 20 of the present embodiment can be applied to the second embodiment.

It should be noted that, as shown in FIG.
Even if a is formed thicker than 20 nm, for example, silane gas (S
Heat treatment can be performed in the atmosphere of iH ₄ ).
In such a case as well, excess titanium can be silicided by reaction with silane gas to suppress the generation of unreacted titanium.

(Embodiment 10) FIGS. 46 and 47 show
FIG. 14 is a cross-sectional view illustrating an example of a method for manufacturing a DRAM according to another embodiment of the present invention.

In the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the silicidation
This is performed before the formation of the OG film 17a.

After the step of FIG. 7 in the first embodiment, a titanium film 53 is deposited on the entire surface of semiconductor substrate 1. Thereafter, heat treatment is performed on semiconductor substrate 1 in the same manner as in the first embodiment to form titanium silicide film 54 (FIG. 46).

Thereafter, the unreacted titanium film is selectively removed by, for example, wet etching (FIG. 47). Subsequent steps are almost the same as in the first embodiment. However,
After the formation of the connection hole 21, the bit line BL and the first layer wiring M
No layer for silicidizing titanium or the like is necessary for the metal film M to be 1.

According to the present embodiment, since the silicide layer is formed in all regions of the semiconductor substrate 1 where silicon is exposed, the connection resistance can be reduced more reliably. Further, since the unreacted titanium is selectively removed, heat resistance can be increased.

The bit line BL after the formation of the connection hole 21
Alternatively, the metal film M to be the first layer wiring M1 may include a layer for silicidation such as titanium. In this case, since excess titanium or the like is present at the bottom of the connection hole 21, the heat resistance at this portion, that is, the bottom of the connection hole 21 decreases, and the connection resistance increases. However, in the present embodiment,
Since the titanium silicide film 54 is also formed in the semiconductor region other than the bottom of the connection hole 21, that is, in the high-concentration impurity region 15 b, low resistance of the semiconductor region is guaranteed by the titanium silicide film 54 other than the bottom of the connection hole 21. You.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in Embodiments 1 to 10,
Although the case where the bit line BL intentionally has an aperture structure with respect to the bit line connection hole BLCT is shown,
And the bit line connection hole BLCT is not intended to have an aperture structure, as shown in FIG.
An aperture structure may be formed due to a mask shift or the like. Needless to say, the present invention can be applied to such a case.

In the above embodiment, the first layer wiring M
The connection between the first layer and the lower layer is described between the high concentration impurity region 15b, which is the source / drain region of the MISFET, and the first layer wiring M1, but is not limited to the source / drain region of the MISFET. For example, the present invention may be applied to connection between the other surface of the semiconductor substrate 1 and the gate electrode of the MISFET.

[0253]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Unevenness of the polycrystalline silicon plug in the bit line connection hole can be prevented. Further, by preventing the unevenness, it is possible to remove an adverse effect in a subsequent process, for example, a photolithography process or an etching process, and to increase a process margin.

(2) The lateral etching of the silicide film at the connection between the bit line and the polycrystalline silicon plug can be prevented. Further, by preventing the lateral etching of the silicide film, the conduction between the bit line and the polycrystalline silicon plug is stably ensured, and the yield and reliability of the semiconductor integrated circuit device can be improved.

(3) DRAM with reduced bit line capacity
In this case, it is possible to reduce the storage capacity required for storing the information or to improve the operation speed of the DRAM.

(4) When the bit line of the DRAM and the first layer wiring in the peripheral circuit area are shared, the heat resistance of the connection portion between the first layer wiring and the semiconductor substrate is improved, and the connection in the subsequent heat process is performed. The increase in leakage current at the
The production yield of AM and its reliability and performance can be improved.

(5) The connection resistance between the first layer wiring and a lower layer member such as a semiconductor substrate can be reduced, and the performance of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view showing an example of an entire semiconductor chip on which a DRAM according to a first embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM of the first embodiment.

FIG. 3 is an enlarged plan view of a part of FIG. 1;

FIG. 4 is a sectional view taken along line IV-IV in FIG. 3;

FIG. 5 is a sectional view illustrating an example of a method of manufacturing the DRAM of the first embodiment in the order of steps.

FIG. 6 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 7 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 8 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 9 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 10 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 11 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 12 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 13 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 14 is an enlarged cross-sectional view showing one example of a method of manufacturing the DRAM of the first embodiment in the order of steps, and FIG.
FIG. 1 is a sectional view taken along line XIV-XIV of FIG.
4 (b) shows X after patterning to form a bit line.
FIG. 14 is a sectional view taken along line IV-XIV.

FIG. 15 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 16 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 17 is a cross-sectional view showing one example of the method for manufacturing the DRAM of the first embodiment in the order of steps;

FIG. 18 is a cross-sectional view showing one example of the method of manufacturing the DRAM of the first embodiment in the order of steps;

19A and 19B are graphs showing experimental results examined by the present inventors. FIG. 19A shows a change in contact resistance (contact resistance) with respect to a nitrogen content, and FIG. ) Shows the case of a p-type substrate.

FIGS. 20A and 20B are graphs showing experimental results examined by the present inventors. FIG. 20A shows a change in leakage current with respect to a nitrogen content, FIG. 20A shows a case of an n-type substrate, and FIG.
The case of a shaped substrate will be described.

FIG. 21 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the second embodiment.

FIG. 22 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the second embodiment.

FIG. 23 is an enlarged sectional view showing an example of the method for manufacturing the DRAM of the second embodiment.

FIG. 24 is an enlarged cross-sectional view showing another example of the method for manufacturing the DRAM of the second embodiment.

FIG. 25 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the third embodiment.

FIG. 26 is an enlarged cross-sectional view showing one example of the method for manufacturing the DRAM of the third embodiment.

FIG. 27 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the third embodiment.

FIG. 28 is an enlarged sectional view illustrating an example of a method for manufacturing a DRAM of the third embodiment.

FIG. 29 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the fourth embodiment.

FIG. 30 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the fourth embodiment.

FIG. 31 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the fourth embodiment.

32 shows an example of a semiconductor integrated circuit device according to the fifth embodiment, FIG. 32a is a plan view showing a part of an indirect peripheral circuit, and FIG. 32b is an equivalent circuit diagram thereof.

FIG. 33 is an enlarged sectional view showing an example of the method for manufacturing a DRAM of the sixth embodiment.

FIG. 34 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the sixth embodiment.

FIG. 35 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the sixth embodiment.

FIG. 36 is an enlarged sectional view showing an example of a method for manufacturing a DRAM of the sixth embodiment.

FIG. 37 is a graph showing the relationship between the contact resistance and the thickness of the titanium silicide film at the bottom of the connection hole;
7A shows the case of n-type, and FIG. 37B shows the case of p-type.

FIG. 38 is an enlarged sectional view showing an example of the method for manufacturing a DRAM of the seventh embodiment.

FIG. 39 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the seventh embodiment.

FIG. 40 is an enlarged sectional view showing an example of the method for manufacturing a DRAM of the seventh embodiment.

FIG. 41 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the seventh embodiment.

FIG. 42 is an enlarged sectional view showing an example of a method for manufacturing a DRAM of the eighth embodiment.

FIG. 43 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the ninth embodiment.

FIG. 44 is an enlarged cross-sectional view showing one example of a method for manufacturing a DRAM of the ninth embodiment.

FIG. 45 is an enlarged cross-sectional view showing another example of the method for manufacturing the DRAM of the ninth embodiment.

FIG. 46 is a sectional view showing an example of a method for manufacturing a DRAM of the tenth embodiment.

FIG. 47 is a cross-sectional view showing an example of the method for manufacturing the DRAM of the tenth embodiment.

FIG. 48 is a plan view showing an example of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 1A semiconductor chip 2, 3 p-type well 4 n-type well 6 deep well 7 isolation region 8 shallow groove 9 silicon oxide film 10 gate insulating film 11 gate electrode 11a polycrystalline silicon film 11b titanium nitride film 11c tungsten film 12 impurity Semiconductor region 13 Cap insulating film 14 Silicon nitride film 15 Impurity semiconductor region 15a Low-concentration impurity region 15b High-concentration impurity region 16 Sidewall spacer 17 Interlayer insulating film 17a SOG film 17b TEOS oxide film 17c TEOS oxide film 17d TEOS oxide film 18 (M1 First layer wiring 18a Titanium film 18b Titanium nitride film 18c Tungsten film 19 Plug 20 Titanium silicide film 21 Connection hole 22a Cap insulating film 22b Sidewall spacer 23 Interlayer insulating film 23a SOG 23b TEOS oxide film 23c TEOS oxide film 23d Silicon nitride film 24 Insulating film 25 Plug 26 Plug 27 Lower electrode 28 Capacitive insulating film 29 Plate electrode 30 Insulating film 31 (M2) Second layer wiring 31a Titanium film 31b Aluminum film 31c Titanium nitride film 32 Plug 32a Adhesive layer 32b Tungsten film 33 Interlayer insulating film 33a TEOS oxide film 33b SOG film 33c TEOS oxide film 34 (M3) Third layer wiring 35 Plug 40 Photoresist film 50 Titanium nitride film 51, 52a, 54 Titanium silicide film 52 Polycrystalline silicon film 53 Titanium film A Memory cell array area B Direct peripheral circuit area BL Bit line BLCT Bit line connection hole BP Bit line plug C Capacitor C Indirect peripheral circuit area CT connection hole CTP wiring plug D port FG1 gate wiring FG2 gate wiring L ₁ active region L ₂ active region L ₃ active region M metal film MARY memory array OVE overetching amount Qn n-channel MISFET Qp p-channel MISFET Qs select MISFET SA a sense amplifier SNCT capacitor connection hole WD word driver WL Word line

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hidekazu Goshima 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Isamu 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside Hitachi, Ltd. Device Development Center (72) Inventor Keizo Kawakita 6-16, Shinmachi, Ome-shi, Tokyo 3 Inside Hitachi Ltd. Device Development Center (72) Inventor Satoru Yamada 6-chome, Shinmachi, Ome-shi, Tokyo No. 16 at Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Tsuyoshi Tamaru 6-chome, Shinmachi, Ome-shi, Tokyo No. 16 Within Hitachi Device Co., Ltd. Device Development Center (72) Inventor Nobuyoshi Kobayashi Ome-shi, Tokyo 6--16 Shinmachi 3 Device Development Center, Hitachi, Ltd. (72) Akita Yumeshi Umezawa 6-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Yoshikazu Ohira 3-16-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd.

Claims (45)

[Claims] 1. A first MISFET for selecting a memory cell and a second M for peripheral circuits formed on a main surface of a semiconductor substrate.
An ISFET and one source of the first MISFET;
A polysilicon plug formed in the first insulating film on the drain region, and an electrical connection to the polysilicon plug through a first connection hole opened in the second insulating film on the first insulating film; The bit line on the second insulating film thus formed and the second MI via the second connection hole of the first and second insulating films.
A semiconductor integrated circuit device having a first layer wiring on the second insulating film electrically connected to a source / drain region of an SFET, a connection region between the bit line and the polycrystalline silicon plug, or A connection region between the first layer wiring and a source / drain region or a gate electrode of the second MISFET or a main surface of the semiconductor substrate is a silicide film of an element selected from titanium, tungsten or cobalt, And a cobalt silicide film containing no impurity is formed, wherein the impurity is any one or a plurality of elements selected from nitrogen, oxygen, carbon, and germanium. Circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the content of said impurity is in a range of 1 atomic% to 13 atomic%. 3. The semiconductor integrated circuit device according to claim 2, wherein said impurity is nitrogen, and the nitrogen content is in a range of 1 at% to 3 at%. Circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein a line width of said bit line is smaller than a diameter of said first connection hole. 5. A first MISFET for selecting a memory cell formed on a main surface of a semiconductor substrate, and said first MISFET.
A polycrystalline silicon plug formed on the first insulating film on one of the source / drain regions;
A semiconductor integrated circuit device having a bit line formed on an insulating film, wherein a first connection hole is opened in the second insulating film, and the bit line and the polycrystalline silicon plug are connected to each other by the first plug. A semiconductor integrated circuit device connected via a first plug formed in a connection hole. 6. The semiconductor integrated circuit device according to claim 5, wherein a surface of said first and second insulating films is at least said first insulating film.
A semiconductor integrated circuit device, wherein the surface is planarized over a region where a MISFET is formed, and a surface of the first plug and a surface of the second insulating film are formed on the same plane. 7. The semiconductor integrated circuit device according to claim 5, wherein the thickness of the bit line is equal to or less than half the diameter of the first connection hole. . 8. The semiconductor integrated circuit device according to claim 5, wherein a line width of the bit line is smaller than a diameter of the first connection hole. 9. The semiconductor integrated circuit device according to claim 5, wherein said bit line is made of a material which can be selectively etched with respect to said first plug. Circuit device. 10. The semiconductor integrated circuit device according to claim 5, wherein said bit line is made of a single-layer film of tungsten or molybdenum, and said first plug is a stacked film containing titanium nitride and tungsten, or A semiconductor integrated circuit device comprising titanium nitride or tungsten nitride. 11. The semiconductor integrated circuit device according to claim 5, further comprising a second MI of a peripheral circuit formed on a main surface of said semiconductor substrate.
An SFET and a first layer wiring of a peripheral circuit formed on the second insulating film; a second connection hole is opened in the first and second insulating films;
The first layer wiring is connected to a source / drain region or a gate electrode of the second MISFET or a main surface of the semiconductor substrate via a second plug formed in the second connection hole; A semiconductor integrated circuit device, wherein the plug is made of the same material as the first plug, and the first layer wiring is made of the same material as the bit line. 12. The semiconductor integrated circuit device according to claim 11, wherein surfaces of said first and second insulating films are flattened over the entire surface of said semiconductor substrate, and surfaces of said first and second plugs. And a surface of the second insulating film is formed on the same plane. 13. The semiconductor integrated circuit device according to claim 11, wherein the bit line and the first layer wiring are formed of a single layer film of tungsten or molybdenum, and the first and second plugs are formed of a titanium nitride film. And a stacked film including a tungsten film and a titanium film or a tungsten nitride film. 14. The semiconductor integrated circuit device according to claim 11, wherein a connection region between the first plug and the polycrystalline silicon plug, or a source / drain region or a gate of the second plug and the second MISFET. In the connection region with the electrode or the main surface of the semiconductor substrate, a silicide film of an element selected from titanium, tungsten, or cobalt and containing an impurity, or a cobalt silicide film containing no impurity is formed. The semiconductor is characterized in that the impurity is one or more elements selected from nitrogen, oxygen, carbon and germanium, and the content of the impurity is in a range of 1 atomic% to 13 atomic%. Circuit device. 15. The semiconductor integrated circuit device according to claim 14, wherein the impurity is nitrogen, and the content of nitrogen is in a range of 1 atomic% to 3 atomic%. Circuit device. 16. The semiconductor integrated circuit device according to claim 11, wherein a connection region between the first plug and the polycrystalline silicon plug, a source of the second plug and a source of the second MISFET.
A silicide film of an element selected from titanium, tungsten or cobalt is formed in a drain region or a connection region with a gate electrode or a main surface of a semiconductor substrate, or in a source / drain surface region of the second MISFET. A semiconductor integrated circuit device, wherein the thickness of the silicide film in any one of the connection region and the surface region is 15 to 30 nm. 17. The semiconductor integrated circuit device according to claim 16, wherein said second MISFET includes a p-channel MISFET, and a source / drain surface region of said p-channel MISFET or said second MISFET. 2 The thickness of the silicide film formed in the connection region between the bottom of the plug and the source / drain region of the p-channel type MISFET is 15 to 30 nm.
A semiconductor integrated circuit device. 18. A first MISFET for selecting a memory cell formed on a main surface of a semiconductor substrate, and said first MISFET.
A polycrystalline silicon plug formed on the first insulating film on one of the source / drain regions of T; a second insulating film formed on the first insulating film; and a second opening formed in the second insulating film. 1. A semiconductor integrated circuit device comprising: a bit line connected to the polycrystalline silicon plug through one connection hole; wherein the bit line has a thickness L ₁ and a thickness of the second insulating film. L ₁ × (1 + OVE) <between a distance L _{2 obtained} by adding the thickness L ₁ of the first connection hole and the diameter D of the first connection hole.
A semiconductor integrated circuit device having a relationship of L ₂ and L ₁ > D / 2 (where OVE is an over-etch amount when patterning a bit line). 19. The semiconductor integrated circuit device according to claim 18, wherein a line width of said bit line is smaller than a diameter of said first connection hole. 20. A first MISFET for selecting a memory cell
Are arranged in an array on the main surface of the semiconductor substrate, a direct peripheral circuit region formed around the memory cell region, and an indirect peripheral circuit region formed around the direct peripheral circuit region A semiconductor integrated circuit device having a second connection hole for connecting a main surface of the semiconductor substrate in the direct or indirect peripheral circuit region and a first layer wiring, wherein a diameter of the second connection hole is: A semiconductor integrated circuit device which is the same in the direct and indirect peripheral circuit regions. 21. The semiconductor integrated circuit device according to claim 20, wherein the aspect ratio of the second connection hole is the same in the memory cell region, the direct peripheral circuit region, and the indirect peripheral circuit region. Semiconductor integrated circuit device. 22. A first MISFET for selecting a memory cell and a second MISFET for a peripheral circuit formed on a main surface of a semiconductor substrate.
A MISFET, a polycrystalline silicon plug formed in a first insulating film on one of the source / drain regions of the first MISFET, and a first connection hole opened in a second insulating film on the first insulating film. And a bit line on the second insulating film electrically connected to the polycrystalline silicon plug through the second connection hole of the first and second insulating films.
A semiconductor integrated circuit device having a first layer wiring on the second insulating film electrically connected to a source / drain region of an ISFET, wherein a connection region between the bit line and the polycrystalline silicon plug; A first layer wiring and a source of the second MISFET;
A silicide film of an element selected from titanium, tungsten or cobalt is formed in a drain region, a gate electrode, a connection region with a main surface of the semiconductor substrate, or a source / drain surface region of the second MISFET. A semiconductor integrated circuit device, wherein the thickness of the silicide film in any one of the connection region and the surface region is 15 to 30 nm. 23. The semiconductor integrated circuit device according to claim 22, wherein the second MISFET includes a p-channel MISFET, and a source / drain surface region of the p-channel MISFET or the second MISFET. Single-layer wiring and the p-channel type M
A semiconductor integrated circuit device, wherein a thickness of the silicide film formed in a connection region between the source and drain regions of the ISFET is 15 to 30 nm. 24. (a) forming a first MISFET for selecting a memory cell on a main surface of a semiconductor substrate;
After forming a first insulating film covering the FET, the first insulating film is replaced with at least one of a source and a source of the first MISFET.
Etching in the presence of a photoresist film having an opening on the drain region; (b) depositing a polycrystalline silicon film filling the opening of the first insulating film formed by the etching on the entire surface of the semiconductor substrate; Removing the polycrystalline silicon film on the first insulating film to form a polycrystalline silicon plug electrically connected to a source / drain region of the first MISFET; (c) forming a polycrystalline silicon plug on the first insulating film Forming a second insulating film, and etching the second insulating film in the presence of a photoresist film having an opening on the polycrystalline silicon plug;
Forming a first connection hole in the insulating film; and (d) one or more impurities selected from nitrogen, oxygen, carbon, and germanium on the bottom of the first connection hole and on the second insulating film. Depositing a metal film containing any of titanium, tungsten or cobalt as a main component, or a cobalt film containing none of the impurities, and performing a heat treatment; Depositing a first conductive film on a cobalt film to fill the first connection hole; (f) forming a photoresist film patterned in a bit line pattern on the first conductive film; Forming a bit line by etching the metal film or the cobalt film and the first conductive film in the presence of the semiconductor integrated circuit device. 25. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the heat treatment forms a silicide film in a connection region between the metal film or the cobalt film and the polycrystalline silicon plug. A method for manufacturing a semiconductor integrated circuit device, which functions as an etching stopper in an etching step. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein a pattern width of the bit line pattern is smaller than a diameter of the first connection hole. Production method. 27. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the content of the impurity in the metal film is in a range of 1 atomic% to 13 atomic%. A method for manufacturing a circuit device. 28. The method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the impurity is nitrogen, and a content of the impurity in the metal film is in a range of 1 atomic% to 3 atomic%. A method for manufacturing a semiconductor integrated circuit device. 29. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the first conductive film is a stacked film of titanium nitride and tungsten. 30. The method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein the second process for the peripheral circuit is performed in the same step as the first MISFET.
Forming a MISFET, in the same step as forming the first connection hole, or before or after the formation of the first connection hole, forming a source / drain region or a gate electrode of the second MISFET or a main surface of the semiconductor substrate; A second for electrically connecting to the semiconductor region;
A method for manufacturing a semiconductor integrated circuit device, comprising: forming a connection hole; and forming a first layer wiring of a peripheral circuit in the same step as forming the bit line. 31. (a) forming a first MISFET for selecting a memory cell on a main surface of a semiconductor substrate;
After forming a first insulating film covering the FET, the first insulating film is replaced with at least one of a source and a source of the first MISFET.
Etching in the presence of a photoresist film having an opening on the drain region; (b) depositing a polycrystalline silicon film filling the opening of the first insulating film formed by the etching on the entire surface of the semiconductor substrate; Removing the polycrystalline silicon film on the first insulating film to form a polycrystalline silicon plug electrically connected to a source / drain region of the first MISFET; (c) forming a polycrystalline silicon plug on the first insulating film Forming a second insulating film, and etching the second insulating film in the presence of a photoresist film having an opening on the polycrystalline silicon plug;
Forming a first connection hole in the insulating film; (d) depositing a first conductive film filling the first connection hole;
Removing the first conductive film on the second insulating film to form a first plug made of the first conductive film in the first connection hole; (e) the first plug and the second insulating film Depositing a second conductive film on the film; and (f) patterning the second conductive film to form a bit line. 32. The method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the first insulating film is planarized by a CMP method before the step of etching the first insulating film, and the first plug is A method of manufacturing a semiconductor integrated circuit device, wherein the first conductive film is formed by polishing by a CMP method. 33. The method for manufacturing a semiconductor integrated circuit device according to claim 31, wherein the thickness of the second conductive film is not more than half the diameter of the first connection hole. Of manufacturing a semiconductor integrated circuit device. 34. The method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the line width of the bit line is equal to or smaller than the diameter of the first connection hole. Method. 35. The method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the second conductive film is a material having an etching selectivity with respect to the first plug. A method for manufacturing a circuit device. 36. The method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein the first conductive film is a stacked film including a titanium nitride film and a tungsten film, or a single layer made of titanium nitride or tungsten nitride. A method of manufacturing a semiconductor integrated circuit device, wherein the second conductive film is a single-layer film made of tungsten or molybdenum. 37. The method of manufacturing a semiconductor integrated circuit device according to claim 31, wherein a second MISFET in a peripheral circuit region is formed in the same step as the first MISFET, and the same step as the formation of the first connection hole is performed. Or the first
Before and after the formation of the connection hole, a second connection hole for connecting to the source / drain region of the second MISFET is formed. At the same time as the formation of the first plug, the first conductive hole is formed in the second connection hole. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a second plug made of a film; and forming a first layer wiring of a peripheral circuit made of the second conductive film simultaneously with the formation of the bit line. 38. The method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein before forming the first and second plugs, bottoms of the first and second connection holes and the second insulating film. Further, one or more impurities selected from nitrogen, oxygen, carbon, and germanium are added at a concentration of 1 atomic% to 1 atomic%.
A metal film containing in the range of 3 atomic% and containing any of titanium, tungsten and cobalt as a main component;
Alternatively, a method of manufacturing a semiconductor integrated circuit device, comprising: depositing a cobalt film containing neither of the impurities and performing a heat treatment. 39. The method of manufacturing a semiconductor integrated circuit device according to claim 37, wherein before forming the first and second plugs, bottoms of the first and second connection holes and the second insulating film. A step of depositing a metal film containing titanium, tungsten or cobalt as a main component in a thickness range of 10 to 20 nm and performing a heat treatment thereon, or a titanium, tungsten or cobalt silicide film, Depositing the film in a thickness range of 15 to 30 nm;
Or a step of depositing a metal film containing any of titanium, tungsten or cobalt as a main component and further depositing a silicon film with a thickness smaller than the metal film and performing a heat treatment; or Depositing a metal film containing any one of the above as a main component and annealing the metal film in an atmosphere of silicon hydride gas. A method of manufacturing a semiconductor integrated circuit device, comprising: 40. The method of manufacturing a semiconductor integrated circuit device according to claim 39, wherein after the heat treatment step of the metal film, unreacted titanium, tungsten or cobalt is selectively removed by etching. Of manufacturing a semiconductor integrated circuit device. 41. (a) MISFE is formed on a main surface of a semiconductor substrate.
Forming T and forming an insulating film covering the MISFET; (b) etching the insulating film in the presence of a photoresist film having openings on source / drain regions of the MISFET; Forming a connection hole; (c) depositing a conductive film filling the connection hole, forming a photoresist film patterned in a wiring pattern on the conductive film, and forming the conductive film in the presence of the photoresist film. Forming a wiring by etching a film, wherein before forming the conductive film, titanium, tungsten or cobalt is formed on the bottom of the connection hole and on the insulating film. A step of depositing a metal film containing any one of the above as a main component in a thickness range of 10 to 20 nm and subjecting it to a heat treatment; Ku the step a silicide film of cobalt, in which the film thickness is deposited in the range of 15 to 30 nm,
Or a step of depositing a metal film containing any of titanium, tungsten or cobalt as a main component and further depositing a silicon film with a thickness smaller than the metal film and performing a heat treatment; or Depositing a metal film containing any one of the above as a main component, and subjecting the metal film to a heat treatment in an atmosphere of a silicon hydride gas. 42. The method of manufacturing a semiconductor integrated circuit device according to claim 41, wherein after the heat treatment of the metal film, unreacted titanium, tungsten or cobalt is selectively removed by etching. Of manufacturing a semiconductor integrated circuit device. 43. The method for manufacturing a semiconductor integrated circuit device according to claim 41, wherein the conductive film is any one of a stacked film of titanium nitride and tungsten, or a three-layer stacked film of titanium, titanium nitride and tungsten. A method of manufacturing a semiconductor integrated circuit device. 44. (a) MISFE is formed on a main surface of a semiconductor substrate.
(B) forming a metal film containing titanium, tungsten or cobalt as a main component at least in a region covering the source / drain of the MISFET;
(C) heat-treating the metal film to form a silicide film at a contact portion with silicon; and (d) etching unreacted titanium, tungsten or cobalt in the heat-treating process. (E) forming an insulating film covering the MISFET; and (f) etching the insulating film in the presence of a photoresist film having openings on source / drain regions of the MISFET. Forming a connection hole in the insulating film; and (g) depositing a conductive film filling the connection hole, forming a photoresist film patterned in a wiring pattern on the conductive film, Forming a wiring by etching the conductive film in the presence of a semiconductor integrated circuit device. 45. The method for manufacturing a semiconductor integrated circuit device according to claim 44, wherein the conductive film is any one of a stacked film of titanium nitride and tungsten, or a three-layered film of titanium, titanium nitride and tungsten. A method of manufacturing a semiconductor integrated circuit device.