JPH11233738A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a ferroelectric memory device with improved reliability by relaxing stress applied to a semiconductor element with a ferroelectric material from a sealing resin and suppressing the occurrence of faulty bits caused by the stress. SOLUTION: In a memory device, a semiconductor element 9 where a circuit 3 with a ferroelectric thin film is formed at least on one surface and a metal lead frame 4 are connected via an adhesive layer 2, a metal small-gauge wire 5, the circuit 3, and the lead frame 4 are electrically connected, sealing is made by a sealing resin 10, and a stress relaxation layer 6 is formed between the sealing resin 10 and the semiconductor element 9. When a compact filler creeps between the large filler in the sealing resin and the semiconductor element 9, a high stress concentration field is generated at the semiconductor element 9, which is relaxed by the stress relaxation layer 6, thus suppressing the generation of faulty bits when manufacturing the semiconductor device and achieving a reliable ferroelectric body memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element and a metal lead frame are sealed with a sealing resin, and more particularly to a semiconductor device using a ferroelectric material as a storage capacitor capacitance insulating film.

[0002]

2. Description of the Related Art A schematic sectional view of a semiconductor device is shown in FIG. In FIG. 12, a circuit 3 is formed on an upper surface of a silicon substrate 1, and a semiconductor element 9 is configured by the silicon substrate 1 and the circuit 3. Silicon substrate 1 has adhesive layer 2
To the metal lead frame (die pad) 4. The metal lead frame 4 is connected to the circuit 3 by a thin metal wire 5.

Then, the semiconductor element 9, the metal lead frame 4, and the thin metal wire 5 are sealed with a sealing resin 10. However, the outer lead portion of the metal lead frame 4 is exposed from the sealing resin 10.

[0004]

By the way, 80% or more of the packages on which the semiconductor elements are mounted are of the resin-sealed type described above, that is, the semiconductor elements are resin-encapsulated together with a metal lead frame. Resin sealing is generally performed at a temperature of about 180 ° C., and is cooled from the temperature of about 180 ° C. to room temperature.

For this reason, in the above-mentioned resin sealing,
In the process of cooling from a temperature of about 180 ° C. to room temperature, residual stress is generated in the semiconductor element according to a difference in thermal expansion coefficient between the semiconductor element and a metal lead frame or a sealing resin.

[0006] With the advance of high integration of semiconductor devices, the technology for thin film processing in the manufacture of semiconductor devices has been miniaturized. However, the miniaturization cannot keep up with the demand for improvement in the degree of integration of semiconductor devices. Therefore, the dimensions of highly integrated semiconductor elements tend to be large.

On the other hand, since the external dimensions of the package of the semiconductor element are determined by the standard, when the element is increased in size with high integration, the ratio of the external dimension of the semiconductor element to the external dimension of the package becomes large. This increases the cooling stress generated in the semiconductor element.

When the stress generated in the semiconductor element increases,
In the worst case, it leads to a defect that the semiconductor element is broken. Even when the semiconductor element does not crack, the circuit characteristics of the semiconductor element, such as the resistance value of the resistor, the capacitance of the capacitor, and the amplification characteristic of the transistor, fluctuate depending on the mechanical stress (strain). Would.

[0009] In particular, in a ferroelectric memory device, which is attracting attention as a nonvolatile memory element, there is a concern that element characteristics may be degraded due to stress. In a ferroelectric material, which is a main material of a ferroelectric memory device, a crystal is distorted by application of an electric field for reading / writing data. The non-volatility of data in a ferroelectric memory device is realized by the fact that the polarization caused by the crystal strain remains after the electric field is removed.

Therefore, if an unnecessary stress (strain) is applied from the outside, the above-mentioned polarization state, that is, stored data may be changed, which significantly affects the reliability of the product. There is a problem that a defective bit which may not be provided and does not exhibit the operation as designed is generated.

An object of the present invention is to reduce the stress applied to a semiconductor element having a ferroelectric substance from a sealing resin, suppress the occurrence of defective bits caused by the stress, and improve the reliability of the ferroelectric memory. The realization of the device.

[0012]

Means for Solving the Problems The present inventors have observed the cross-sectional structure of a defective bit generated in a ferroelectric memory device due to the above-mentioned stress, and this portion was observed as shown in the schematic diagram of FIG. Small filler (filler) in the sealing resin 10
It was confirmed that 12 was pressed against the semiconductor element 9 by the large filler 11. These fillers 11 and 12 are large and small ones contained in the resin 13 in order to strengthen the mechanical strength of the resin 13. The large filler 11 has a diameter of about 10 to 100 μm and a small filler. Reference numeral 12 has a diameter of about several μm.

As described above, during packaging with the sealing resin 10, stress is generated in the element due to the difference in thermal expansion coefficient between the sealing resin 10 and the semiconductor element 9. In general, the resin material has a larger thermal expansion coefficient between the resin material and the semiconductor substrate, so that a compressive stress is generated in the semiconductor element 9.

As a result of analyzing the stress immediately below the structure in which the small filler 12 enters just below the large filler 11,
The present inventor has clarified that stress concentration occurs immediately below the small filler 12, and a compressive stress of about 20 times the average compressive stress due to the sealing resin 10 is generated in the normal direction of the substrate surface.

The inventors of the present application measured the relationship between the stress applied to the ferroelectric thin film and the polarization characteristics of the ferroelectric, and as a result, the polarization characteristics of the ferroelectric showed stress dependence. It revealed that.

FIGS. 3 and 4 show the relationship between the stress of the ferroelectric (lead zirconate titanate: Pb (Ti, Zr) O ₃ ) and the remanent polarization (normalized by the initial value: 2Pr / 2Pr ₀ ). . The remanent polarization represents the amount of charge that can be stored in the storage capacitor. FIG. 3 shows the stress in the direction perpendicular to the electrode surface, and FIG. 4 shows the stress in the direction horizontal to the electrode surface.

In both the direction perpendicular to the electrode surface (FIG. 3) and the direction horizontal to the electrode surface (FIG. 4), the remanent polarization changes with respect to the stress. In particular, for a compressive stress in the electrode surface pressure direction, 100
Degradation of as much as 7 to 8% per MPa occurs.

FIG. 5 shows a sectional structure of a general ferroelectric memory element at present. In FIG. 5, 31 is an element isolation film,
32 is a gate oxide film, 33 is a source, 34 is a drain,
35 is a gate electrode, 36 and 38 are interlayer insulating films, 37 is a bit line, 39 is a contact plug, 40 is a lower electrode,
Reference numeral 1 denotes a capacitor insulating film, 42 denotes an upper electrode, and is electrically connected to the MOS transistor. A storage capacitor using a ferroelectric material for the capacitor insulating film 41 is disposed parallel to the silicon substrate 1.

For this reason, the stress generated by the filler at the time of resin sealing is applied in the direction of the electrode surface pressure of the storage capacitor where the ferroelectric material is most susceptible to the stress, deteriorating the polarization characteristics of the ferroelectric material. The present inventor has clarified that the formation of a defective bit results.

Based on the present inventor's elucidation of the cause of the occurrence of a defective bit, the present invention is configured as follows.

(1) In a ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with a resin, the unit of the film thickness is set to microns, and the unit of the Young's modulus is set. Is defined as gigapascal, the ratio of the Young's modulus to the film thickness between the surface of the semiconductor element having the ferroelectric thin film and the sealing resin is 2.
An insulating stress relaxation layer having a value of 0 or less is formed.

(2) In a ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with resin, the unit of the film thickness is set to microns and the Young's modulus When a unit of gigapascal is used, an insulating stress relaxation layer having a Young's modulus ratio of 2.0 or less with respect to the film thickness is formed on the surface of the semiconductor element having the ferroelectric thin film.

(3) Preferably, (1) or (2) above
In the above, the Young's modulus of the stress relaxation layer is at least one digit lower than the Young's modulus of the sealing resin.

(4) Preferably, in the above (1) or (2), the stress relaxation layer is a polyimide film. (5) Preferably, in the above (1) or (2), the stress relaxation layer is a gel coat film.

(6) In a ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with a resin, a plurality of fillers are contained in the resin. The density of the filler in the vicinity of the semiconductor element of the resin is lower than the density of the filler in the vicinity of at least the surface of the resin.

(7) Preferably, in the above (1) or (2), the thickness of the stress relaxation layer is 1 μm or more.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of a ferroelectric memory device according to a first embodiment of the present invention, and FIG. 2 shows a positional relationship between a die pad and outer leads of a ferroelectric memory device applicable to the present invention. FIG. 2A shows a half of the entire structure, and FIG. 2B shows a quarter of the whole structure. FIGS. 3 and 4 are diagrams showing the stress dependence of the remanent polarization of the ferroelectric material, and show the vertical direction of the electrode surface and the horizontal direction of the electrode surface, respectively.

FIG. 5 is a schematic cross-sectional view of a general ferroelectric memory device, and FIG. 6 is a diagram illustrating a filler, a semiconductor device, and a stress relaxation film for explaining the operation and effect of the first embodiment of the present invention. FIG. 7 is a diagram showing the dependency of the stress generated by the filler on the film thickness of the stress relaxation film, and FIG. 8 is obtained by the film thickness and the Young's modulus of the stress relaxation film.
FIG. 9 is a contour graph of the stress relaxation rate, and FIG. 9 is a graph showing the dependency of the product yield on the stress relaxation rate.

The ferroelectric memory device according to the first embodiment has
As shown in FIG. 1, a semiconductor element 9 in which a circuit 3 having a ferroelectric thin film is formed on a silicon substrate 1 is connected to a metal lead frame (die pad) 4 via an adhesive layer 2, and a thin metal wire 5 (for example, Circuit 3 with ferroelectric thin film with gold wire)
And a metal lead frame (outer lead) 4 arranged in two directions is electrically connected, a stress relaxation layer 6 is applied to the element surface, and the element is sealed with a sealing resin 10.

As the sealing resin, for example, a thermosetting epoxy resin having a Young's modulus of 10 to 20 GPa is used, but is not necessarily limited to the epoxy resin. Further, the sealing resin has a Young's modulus of about 70, for example.
A filler made of GPa silicon oxide is included.

As the metal lead frame 4, for example, an iron-nickel alloy such as 42-Ni-Fe or a copper alloy is used. Note that the metal lead frame 4 may be made of a material other than an iron-nickel alloy or a copper alloy.

The stress relaxation layer 6 is a low elasticity insulating film.
The ratio of the Young's modulus (unit: gigapascal) to the film thickness (unit: micron) is smaller than 2.0. For example, a polyimide film or a gel-like film is preferable, but other values may be used. The ratio of the Young's modulus to the film thickness is preferably calculated using a value within the range of the operation compensation environment of the apparatus.

As shown in FIG. 5, a part of the cross-sectional structure of a general ferroelectric memory element is a transistor (source 33, drain 34, gate electrode 35) separated by an element isolation film 31 on a silicon substrate 1. The storage capacitors (electrodes 40, 42, capacitance insulating film 41) electrically connected to the gate oxide film 32) by the plaque 39
7, formed on the interlayer insulating films 36 and 38;

As the capacitor insulating film 41, for example, a ferroelectric film such as lead zirconate titanate (Pb (Zr, Ti) O ₃ ) or a bismuth layer compound is used, but other materials may be used. . For the electrodes 40 and 42, for example, platinum, iridium oxide, ruthenium oxide, or the like is used.

The present invention relates to a semiconductor element in which a filler in a sealing resin and a ferroelectric thin film are formed, and the method for electrically connecting the semiconductor device to the outside is limited to this embodiment. Not something. For example, as shown in FIG. 2B, the lead frame 4 may be provided in four directions, or may be connected to the outside by solder balls.

The structure of the ferroelectric memory element is not limited to the structure of the first embodiment as long as a ferroelectric thin film is formed.

The operation and effect of the ferroelectric memory device according to the first embodiment will be described below. The inventors performed a stress analysis in the semiconductor element 9 immediately below the small filler 12 due to resin sealing, and revealed that a stress concentration field was formed immediately below the filler 12. The analysis model conformed to FIG.

As a result of the analysis, on average, a compressive stress of about 4 MPa is generated in the semiconductor element by the resin sealing, and when only the large filler 11 is present, the stress immediately below it is amplified to about 7 MPa. It just does. However, in the structure in which the small filler 12 enters under the large filler 11, the stress directly below the filler 12 is amplified by about 20 times, resulting in a compressive stress of 75 MPa.

The inventors measured the stress dependence of the characteristics of the ferroelectric (FIGS. 3 and 4), and found that the occurrence of defective bits was due to the deterioration of the ferroelectric characteristics due to the stress generated by the filler. Revealed. Further, as shown in FIG. 5, in general, since the storage capacitor is arranged in parallel to the substrate 1, the stress caused by the filler applied to the semiconductor element vertically is as follows.
It has been clarified that the stress in the direction perpendicular to the electrode surface causes a large deterioration in the characteristics of the ferroelectric.

As a result, it has become clear that in order to prevent the occurrence of defective bits, it is necessary to relax the stress caused by the filler applied to the ferroelectric thin film. Therefore, the inventors of the present application have analyzed and found that it is effective to provide the stress relaxation layer 6 between the sealing resin 10 and the semiconductor element 9 as shown in FIG.

FIG. 7 shows the result of analyzing the stress generated in the semiconductor element 9 immediately below the filler 12 in the model shown in FIG. A polyimide film (PIQ) was assumed for the stress relaxation layer 6. As a result, it was found that the stress of the semiconductor element 9 was relaxed, and when a film having a Young's modulus of 2 GPa was applied, the stress was relaxed by about 50% with 3 μm coating and about 60% with 5 μm coating.

It was also found that when a material having a lower elastic modulus such as gel coat was used for the stress relaxation film 6, the stress value could be reduced to 1/10 or less. Therefore, for example, the Young's modulus of the sealing resin 10 is about 10 to 2
In the case of 0 GPa, the Young's modulus of the stress relaxation layer 6 is desirably at least one digit lower than the Young's modulus of the sealing resin 10 such as 2 GPa.

FIG. 8 shows the stress relaxation rates (20%, 30%, 4%) using the thickness of the stress relaxation film 6 and the Young's modulus as parameters.
0%, 50%, 60%). The smaller the Young's modulus and the thicker the film thickness, the more effective the stress relaxation.

FIG. 9 shows the dependency of the product yield on the stress relaxation rate. In FIG. 9, the stress relaxation rate is 20 to 30.
% Or more, a product yield of 90% or more can be secured. Therefore, in FIG. 8, if the material is selected such that the ratio α of the Young's modulus (unit: gigapascal) to the film thickness (unit: micron) becomes 2.0 or less, the stress relaxation rate becomes 20 to 30.
It is clear that an effect of at least% is expected. According to the first embodiment of the present invention, the yield is about 30% in the related art, but the yield is 92%.
% Or more.

As described above, according to the first embodiment of the present invention, since the insulating stress relaxation layer is formed between the surface of the semiconductor element having the ferroelectric thin film and the sealing resin, the sealing is achieved. Even when the small filler is positioned between the large filler in the resin and the semiconductor element, the stress is alleviated by the stress relieving layer, suppressing the stress generated in the semiconductor element,
The characteristic deterioration of the ferroelectric can be prevented.

Since the structure in which the small filler enters directly below the large filler occurs at a certain probability, according to the present invention, the occurrence of defective bits can be prevented, and the reliability and yield of the product can be improved. Can contribute. That is, according to the first embodiment of the present invention, a ferroelectric memory device with improved reliability can be realized.

The stress relaxation layer 6 does not need to be formed only on the surface of the semiconductor element 9 having the circuit 3 having the ferroelectric thin film, and the filler (11, 12) in the sealing resin 10 is not required. ) And the semiconductor element 9, the layer need not necessarily be formed directly on the semiconductor element 9.

The desirable thickness of each component in the ferroelectric memory device of the first embodiment is about 0.1 to 1.0 mm (more preferably 0.2 to 0.4 mm) for the semiconductor substrate 1. About), about 0.1 to 2.0 mm (more preferably 0.3 to 2.0 mm) for the sealing resin 10.
About 0.8 mm), and about 0.1 to 0.5 mm (more preferably 0.2 to 0.5 mm) for the metal lead frame 4.
About 0.3 mm) and about 0.1 μm to 1 for the adhesive layer 2.
About 00 μm (more preferably several tens μm),
The stress relaxation layer 6 has a thickness of about 0.1 to 100 μm (more preferably about 1.0 to 10 μm). In addition,
The dimensions of each component are not limited to the above, and may be other values according to the conditions.

Next, a description will be given using a second embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of a ferroelectric memory device according to a second embodiment of the present invention, and FIG.
FIG. 4 is a schematic diagram showing a positional relationship between a filler in a sealing resin and a semiconductor element in the embodiment.

In the ferroelectric memory device according to the second embodiment of the present invention, as shown in FIG. 10, a semiconductor element 9 having a circuit 3 having a ferroelectric thin film formed on a silicon substrate 1 is replaced with a metal lead. A metal lead frame (outer lead) 4 is connected to a frame (die pad) 4 via an adhesive layer 2, and is electrically connected to a circuit 3 having a ferroelectric thin film by a thin metal wire 5 (for example, a gold wire). To the sealing resin 20
The structure is sealed with.

As the sealing resin 20, for example, a thermosetting epoxy resin having a Young's modulus of 10 to 20 GPa is used, but is not necessarily limited to the epoxy resin. For example, the sealing resin has a Young's modulus of about 70 GPa.
Of a silicon oxide.

As shown in FIG. 11, the fillers 11 and 12 in the sealing resin 20 have a low density near the semiconductor element 9, and more preferably, a resin layer containing no filler is near the semiconductor element 9. Exists.

The material described in the first embodiment may be used as the material of the metal lead frame 4.

As shown in FIG. 5, a part of the cross-sectional structure of a general ferroelectric memory element is a transistor (source 33, drain 34, gate electrode 35, Gate oxide film 3
A storage capacitor (electrodes 40 and 42, a capacitor insulating film 41) electrically connected to 2) by a plaque 39 is formed on the bit line 37 and the interlayer insulating films 36 and 38. Capacitive insulating film 4
1. The electrodes 40 and 42 may be the same as those described in the first embodiment.

The present invention relates to a semiconductor element on which a filler in a sealing resin and a ferroelectric thin film are formed. The method of electrically connecting the semiconductor device to the outside of the semiconductor device is limited to this embodiment. Not something. For example, as shown in FIG. 2 (b), it may be provided in four directions, or may be connected to the outside by solder balls.

The structure of the ferroelectric memory element is not limited to the structure of the second embodiment as long as a ferroelectric thin film is formed.

The operation and effect of the ferroelectric memory device according to the second embodiment will be described below. As described in the description of the first embodiment, in the conventional resin sealing structure, a stress concentration portion is generated in a semiconductor element by a small filler penetrating directly below a large filler in a sealing resin. . as a result,
The ferroelectric formed in the semiconductor element has a problem in that the characteristics are deteriorated by the stress, and a defective bit that does not operate as designed is generated.

This is because a large number of large and small fillers, which lead to the formation of defective bits, are uniformly present in the sealing resin. As a result, a structure as shown in FIG. It became clear that the probability of occurrence was high.

According to the second embodiment of the present invention, FIG.
13, the density of the filler (filler) in the vicinity of the semiconductor element 9 is made lower than the density of the filler (filler) in at least the vicinity of the surface of the sealing resin 20 to obtain the state shown in FIG. Probability can be reduced. As a result, the probability of occurrence of defective bits having deteriorated ferroelectric properties due to fillers is reduced, which can contribute to improvement in product reliability and yield.

The desired dimensions of each component in the semiconductor device of the second embodiment may be the dimensions described in the first embodiment. Various methods for reducing the filler density in the vicinity of the semiconductor element 9 in the sealing resin 20 are conceivable. For example, the sealing resin 20 is divided into a first layer and a second layer. The first layer contains a filler, but the second layer does not contain a filler. If the second layer is arranged on the semiconductor element 9 side, the filler exists in the vicinity of the semiconductor element 9. It is possible to adopt a configuration that does not.

Further, the second layer may contain only a large filler or only a small filler.
Similar effects can be obtained.

[0062]

Since the present invention is configured as described above, the following effects can be obtained. By providing the stress relaxation layer between the semiconductor element and the sealing resin, the stress caused by the filler generated in the semiconductor element can be alleviated, and the characteristic deterioration of the ferroelectric due to the stress can be prevented.

As a result, it is possible to prevent occurrence of defective bits at the time of resin encapsulation, and there is an effect that the reliability and the yield of the ferroelectric memory device can be improved.

By setting the density of the filler in the vicinity of the semiconductor element to be lower than the density of the filler in at least the vicinity of the surface of the sealing resin, the probability of occurrence of defective bits due to the filler and deteriorating the ferroelectric characteristics is reduced. Lower, which can contribute to improved product reliability and yield

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a positional relationship between a die pad and outer leads of a ferroelectric memory device applicable to the present invention.

FIG. 3 is a graph showing the dependence of the polarization characteristics of a ferroelectric on the stress in the direction perpendicular to the electrode surface.

FIG. 4 is a graph showing the dependence of the polarization characteristics of a ferroelectric on the stress in the horizontal direction of the electrode surface.

FIG. 5 is a schematic diagram of a cross-sectional structure of a general ferroelectric memory element.

FIG. 6 is a schematic diagram illustrating a positional relationship among a stress relaxation layer, a sealing resin, and a semiconductor element according to the first embodiment of the present invention.

FIG. 7 is a graph showing a result of analyzing a stress generated in a semiconductor element immediately below a filler.

FIG. 8 is a contour graph of the stress relaxation rate using the thickness of the stress relaxation film and the Young's modulus as parameters.

FIG. 9 is a graph showing the effect of improving product yield by stress relaxation.

FIG. 10 is a schematic sectional view of a ferroelectric memory device according to a second embodiment of the present invention.

FIG. 11 is a schematic view illustrating a positional relationship among a stress relaxation layer, a sealing resin, and a semiconductor element according to a second embodiment of the present invention.

FIG. 12 is a schematic sectional view of a conventional semiconductor device.

FIG. 13 is a schematic diagram for explaining occurrence of a defective bit in a ferroelectric memory device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 adhesive layer 3 circuit having ferroelectric thin film 4 metal lead frame 5 thin metal wire 6 stress relaxation layer 9 semiconductor element 10, 20 sealing resin 11 large filler 12 small filler 13 resin 31 element separation film 32 Gate oxide film 33 Source 34 Drain 35 Gate electrode 36, 38 Interlayer insulating film 37 Bit line 39 Contact plug 40 Lower electrode 41 Capacitive insulating film 42 Upper electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792 (72) Inventor Asao Nishimura 5--20-1, Josuihoncho, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd.

Claims (7)

[Claims] 1. A ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with a resin, wherein the unit of the film thickness is microns and the unit of the Young's modulus is An insulating stress-relief layer having a ratio of Young's modulus to the film thickness of 2.0 or less between the surface of the semiconductor element having the ferroelectric thin film and the encapsulating resin when the pressure is gigapascal; A ferroelectric memory device comprising: 2. A ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with a resin. When the gigapascal is used, an insulating stress relaxation layer having a Young's modulus ratio of 2.0 or less with respect to the film thickness is formed on the surface of the semiconductor device having the ferroelectric thin film. Ferroelectric memory device. 3. The ferroelectric memory device according to claim 1, wherein a Young's modulus of said stress relaxation layer is at least one order of magnitude lower than a Young's modulus of said sealing resin. apparatus. 4. The ferroelectric memory device according to claim 1, wherein said stress relaxation layer is a polyimide film. 5. The ferroelectric memory device according to claim 1, wherein said stress relaxation layer is a gel coat film. 6. A ferroelectric memory device in which a semiconductor element having a ferroelectric thin film on at least one side and a metal lead frame are sealed with a resin, wherein the resin contains a plurality of fillers, A ferroelectric memory device, wherein the density of the filler near the semiconductor element of the resin is lower than the density of the filler near at least the surface of the resin. 7. The ferroelectric memory device according to claim 1, wherein the thickness of the stress relaxation layer is 1 μm or more.