JPH11233558A - Flip-chip connection method and connection structure body - Google Patents
Flip-chip connection method and connection structure bodyInfo
- Publication number
- JPH11233558A JPH11233558A JP3142498A JP3142498A JPH11233558A JP H11233558 A JPH11233558 A JP H11233558A JP 3142498 A JP3142498 A JP 3142498A JP 3142498 A JP3142498 A JP 3142498A JP H11233558 A JPH11233558 A JP H11233558A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- circuit element
- electrode
- circuit board
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路素
子を回路基板に直接フェースダウンで電気的に接続する
フリップチップ接続方法およびその方法で接続された接
続構造体並びにそれによって構成された電子機器に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip connection method for electrically connecting a semiconductor integrated circuit element directly to a circuit board face-down, a connection structure connected by the method, and an electronic device constituted thereby. About.
【０００２】[0002]
【従来の技術】従来、半導体集積回路素子を回路基板に
直接フェースダウンで電気的に接続するフリップチップ
接続方法として、導電性接着剤を用いた方法がある。突
起電極を有する半導体集積回路素子と、該突起電極と電
気的に接続できるように配置した基板電極を有する回路
基板を用い、該突起電極と該基板電極との間に導電性接
着剤を介在させ、半導体集積回路素子と回路基板の間に
樹脂を介在させる構造である。その一例として例えば、
特開平９−１０７００３号公報に開示されているものが
ある。図３は上記公報に開示された従来技術を示したプ
ロセス図である。2. Description of the Related Art Conventionally, there is a method using a conductive adhesive as a flip-chip connection method for electrically connecting a semiconductor integrated circuit element directly to a circuit board face-down. A semiconductor integrated circuit element having a protruding electrode and a circuit board having a substrate electrode arranged so as to be electrically connectable to the protruding electrode are used, and a conductive adhesive is interposed between the protruding electrode and the substrate electrode. And a structure in which a resin is interposed between the semiconductor integrated circuit element and the circuit board. For example, for example,
There is one disclosed in JP-A-9-107003. FIG. 3 is a process diagram showing a conventional technique disclosed in the above publication.
【０００３】上記従来技術においては、半導体集積回路
素子１の端子電極に突起電極２を形成し、該突起電極２
の先端に転写方式で導電性接着剤９をつける。転写方式
とは容器１０に所定の厚さに収容された導電性接着剤９
に突起電極２を押し付けて、該突起電極２を上方に持ち
上げることで所定の厚さの導電性接着剤９を突起電極２
に転写する方法である。半導体集積回路素子１が搭載さ
れる部分に樹脂６を塗布し、樹脂６の上から半導体集積
回路素子１を回路基板３上に搭載し加熱硬化させる。特
に上記従来技術では導電性接着剤９に遅硬化タイプのも
のを用い、樹脂６に速硬化タイプのものを用いることで
突起電極２に転写した導電性接着剤９が樹脂６によって
流されることなく、確実に突起電極２と基板電極４の間
に介在させることができる。In the prior art, a protruding electrode 2 is formed on a terminal electrode of a semiconductor integrated circuit device 1 and the protruding electrode 2 is formed.
A conductive adhesive 9 is applied to the end of the substrate by a transfer method. The transfer method means that the conductive adhesive 9 contained in the container 10 at a predetermined thickness is used.
The protruding electrode 2 is pressed against the protruding electrode 2, and the protruding electrode 2 is lifted upward, so that the conductive adhesive 9 having a predetermined thickness is applied to the protruding electrode 2.
This is a method of transferring to The resin 6 is applied to a portion where the semiconductor integrated circuit element 1 is mounted, and the semiconductor integrated circuit element 1 is mounted on the circuit board 3 from above the resin 6 and cured by heating. In particular, in the above-mentioned prior art, the conductive adhesive 9 used is a slow-curing type and the resin 6 is a fast-curing type, so that the conductive adhesive 9 transferred to the protruding electrode 2 is prevented from flowing by the resin 6. Thus, it can be reliably interposed between the protruding electrode 2 and the substrate electrode 4.
【０００４】また、特開平８―１７２１１４号公報に
は、金バンプを備える半導体チップを用いた場合のフリ
ップチップ接続方法の一従来技術が開示されている。こ
の従来技術では、半導体チップに金バンプを形成し、該
半導体チップが実装される基板にはんだを供給すると共
に、両者が接合される基板上の一部分に絶縁性樹脂を予
め供給しておく。半導体チップの搭載時には、はんだ融
点以下の温度で加圧・加熱して半導体チップと基板との
接合部を仮接続し、絶縁性樹脂を硬化させる。その後、
リフロ炉を通すことではんだの融点以上の温度で加熱し
て、金―はんだ接合を形成する。Japanese Patent Application Laid-Open No. 8-172114 discloses a conventional flip-chip connection method using a semiconductor chip having gold bumps. In this conventional technique, a gold bump is formed on a semiconductor chip, solder is supplied to a substrate on which the semiconductor chip is mounted, and an insulating resin is supplied in advance to a part of the substrate to which the two are joined. When mounting the semiconductor chip, the joint between the semiconductor chip and the substrate is temporarily connected by applying pressure and heating at a temperature equal to or lower than the melting point of the solder, and the insulating resin is cured. afterwards,
It is heated at a temperature higher than the melting point of the solder by passing it through a reflow oven to form a gold-solder joint.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記に
記載した従来のフリップチップ接続には下記の問題点が
あった。However, the above-mentioned conventional flip-chip connection has the following problems.
【０００６】上記特開平９−１０７００３号公報の導電
性接着剤を用いたフリップチップ接続方法では、半導体
集積回路素子の突起電極の先端に導電性接着剤を付ける
転写方式を用いる必要がある。しかし、該転写方式はチ
ップボンダのタクトタイムが長くなるため、大量生産に
は適した工法ではなく組立コストを高価にする問題があ
る。In the flip-chip connection method using a conductive adhesive disclosed in Japanese Patent Application Laid-Open No. 9-107003, it is necessary to use a transfer method in which a conductive adhesive is applied to the tip of a protruding electrode of a semiconductor integrated circuit device. However, this transfer method has a problem in that the tact time of the chip bonder becomes long, so that it is not a method suitable for mass production, and the assembly cost is high.
【０００７】また、該転写方式は容器に所定の厚さの薄
い導電性接着層を形成させるため、導電性接着剤が短時
間で乾燥してしまう。そのため、時間経過とともに突起
電極に転写される導電性接着剤の転写量が減少してしま
い接続断線になる恐れがある。そこで、転写方式では導
電性接着剤の一定量を維持するために、常に導電性接着
剤を新しいものと交換する必要がある。しかし、常に導
電性接着剤を新しいものと交換するため、多量の導電性
接着剤を使用せざる得ない。Further, in the transfer method, since a thin conductive adhesive layer having a predetermined thickness is formed on a container, the conductive adhesive is dried in a short time. As a result, the amount of the conductive adhesive transferred to the protruding electrodes decreases with the passage of time, which may result in disconnection. Therefore, in the transfer method, it is necessary to always replace the conductive adhesive with a new one in order to maintain a certain amount of the conductive adhesive. However, since the conductive adhesive is always replaced with a new one, a large amount of the conductive adhesive must be used.
【０００８】また、取扱いでも導電性接着剤が乾燥しな
いように管理する必要である。Further, it is necessary to control the conductive adhesive so as not to dry even during handling.
【０００９】したがって、導電性接着剤を用いるとチッ
プボンダのタクトタイムが長くなり、多量の導電性接着
剤を使用することなどから生産コストが高価となる。Therefore, when the conductive adhesive is used, the tact time of the chip bonder becomes long, and the production cost becomes high because a large amount of the conductive adhesive is used.
【００１０】一方、上記特開平８―１７２１１４号公報
の従来技術では、最初はんだの融点以下で接合部の仮接
続を行い、同時に絶縁性樹脂の硬化を行った後、はんだ
の融点以上の温度を加え、接合部を接続させる。その結
果、はんだ内に含有されていたフラックスなどのガス
は、はんだ溶融時にはんだ外へ排出されるが、接合部周
辺の絶縁性樹脂が硬化しているため、外気へ排出される
ことなく、接合部と絶縁性樹脂の間に蓄積される。On the other hand, in the prior art disclosed in Japanese Patent Application Laid-Open No. 8-172114, temporary connection of a bonding portion is first performed at a temperature lower than the melting point of the solder, and at the same time, the insulating resin is cured. In addition, the joint is connected. As a result, gases such as flux contained in the solder are discharged out of the solder when the solder is melted, but since the insulating resin around the joint is hardened, it is not discharged to the outside air, Is accumulated between the part and the insulating resin.
【００１１】このように絶縁性樹脂内に蓄積されたガス
は、接合部の応力緩和機能を低下させ、接続部の信頼性
低下の一因となる場合がある。[0011] The gas accumulated in the insulating resin as described above may reduce the stress relaxation function of the joint and may contribute to the reduction of the reliability of the connection.
【００１２】本発明の目的は、上記したフリップチップ
接続の生産効率を向上させ、チップボンダのタクトタイ
ムを短くすることで生産コストを安価にでき、かつ接続
部の信頼性向上を図ることができるフリップチップ接続
方法および接続構造体を提供することにある。An object of the present invention is to improve the production efficiency of the above-mentioned flip-chip connection, shorten the tact time of the chip bonder, reduce the production cost, and improve the reliability of the connection portion. It is to provide a chip connection method and a connection structure.
【００１３】[0013]
【課題を解決するための手段】本発明は上記の目的を達
成するために、回路素子が搭載される部分に熱硬化性樹
脂を有し、基板電極上にはんだを有する回路基板に、突
起電極を有する回路素子を実装するフリップチップ接続
方法において、前記回路素子を前記回路基板上の目的と
する部位に位置決め搭載した後、加熱する加熱工程を含
み、前記加熱工程は、加熱温度を前記はんだの融点以上
まで上昇させて前記はんだを溶融させる第１の工程と、
該加熱温度を前記はんだの融点以下まで下降させて前記
熱硬化性樹脂の硬化反応を進める第２の工程とを含むこ
とを特徴とする。In order to achieve the above object, the present invention provides a circuit board having a thermosetting resin at a portion where a circuit element is to be mounted and a solder on a board electrode. In the flip-chip connection method of mounting a circuit element having a soldering step, after positioning and mounting the circuit element on a target portion on the circuit board, the method includes a heating step of heating, and the heating step includes setting a heating temperature of the solder. A first step of melting the solder by raising it to a melting point or higher;
A second step of lowering the heating temperature below the melting point of the solder to advance the curing reaction of the thermosetting resin.
【００１４】また、本発明は上記の目的を達成するため
に、突起電極を有する回路素子と基板電極上にはんだを
有する回路基板とからなり、該回路素子と回路基板との
間に熱硬化性樹脂を介在するフリップチップ接続構造体
において、前記突起電極と前記はんだとの金属接合を、
前記熱硬化性樹脂の硬化が完了する前に形成されたもの
とすることを特徴とする。In order to achieve the above object, the present invention comprises a circuit element having a protruding electrode and a circuit board having solder on a substrate electrode, wherein a thermosetting material is provided between the circuit element and the circuit board. In the flip-chip connection structure with a resin interposed, the metal joint between the bump electrode and the solder is
The thermosetting resin is formed before the curing of the thermosetting resin is completed.
【００１５】例えば、基板電極上にはんだプリコート法
ではんだを形成し、回路基板上の半導体集積回路素子が
搭載される部分に予め熱硬化性樹脂を塗布し、半導体集
積回路素子の突起電極と基板電極を位置合わせした後、
半導体集積回路素子を回路基板上に搭載し、半導体集積
回路素子を吸着したボンディングツールに備えられた第
１の加熱手段と回路基板を載せた基板ステージに備えら
れた第２の加熱手段とにより半導体集積回路素子と回路
基板を加熱する。For example, a solder is formed on a substrate electrode by a solder pre-coating method, and a thermosetting resin is applied in advance to a portion of the circuit board on which the semiconductor integrated circuit element is to be mounted. After aligning the electrodes,
A semiconductor integrated circuit element is mounted on a circuit board, and a semiconductor is formed by a first heating means provided on a bonding tool that has absorbed the semiconductor integrated circuit element and a second heating means provided on a substrate stage on which the circuit board is mounted. Heat the integrated circuit element and the circuit board.
【００１６】加熱する際には、最初、突起電極と基板電
極の間に介在するはんだの溶融を行い、次に半導体集積
回路素子と回路基板の間に介在している樹脂の硬化反応
を進める。At the time of heating, first, the solder interposed between the protruding electrode and the substrate electrode is melted, and then the curing reaction of the resin interposed between the semiconductor integrated circuit element and the circuit board is advanced.
【００１７】以上のプロセスにより、突起電極に金を用
いた場合、半導体集積回路素子の突起電極と基板電極と
の電気接続を実現する金―はんだ接続の形成が完了した
後に、熱硬化性樹脂の硬化が完了する。According to the above process, when gold is used for the protruding electrode, after the formation of the gold-solder connection for realizing the electrical connection between the protruding electrode of the semiconductor integrated circuit device and the substrate electrode is completed, the thermosetting resin is used. Curing is complete.
【００１８】[0018]
【発明の実施の形態】以下、図面を用いて本発明を詳述
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.
【００１９】図１に有機回路基板への搭載が完了した、
本発明の一実施形態におけるフリップチップ接続構造体
の断面図を示す。FIG. 1 shows that mounting on the organic circuit board is completed.
1 shows a cross-sectional view of a flip chip connection structure according to an embodiment of the present invention.
【００２０】図１において、１は半導体集積回路素子、
２は半導体集積回路素子の端子電極に設けた突起電極
（バンプ）、３は回路基板、４は基板電極、５は基板電
極上に設けたはんだ、６は熱硬化性樹脂である。なお、
突起電極２の材料は金またははんだが好ましい。はんだ
５は共晶はんだまたは錫、銀はんだが好ましい。樹脂６
はエポキシアクリレートまたはフェノールエポキシ、シ
アノアクリレートを主骨格とする材料が好ましい。In FIG. 1, 1 is a semiconductor integrated circuit device,
Reference numeral 2 denotes a protruding electrode (bump) provided on a terminal electrode of the semiconductor integrated circuit element, 3 denotes a circuit board, 4 denotes a substrate electrode, 5 denotes a solder provided on the substrate electrode, and 6 denotes a thermosetting resin. In addition,
The material of the protruding electrode 2 is preferably gold or solder. The solder 5 is preferably a eutectic solder or a tin or silver solder. Resin 6
Is preferably a material having a main skeleton of epoxy acrylate, phenol epoxy, or cyanoacrylate.
【００２１】図２を用いて下記に、突起電極２を設けた
半導体集積回路素子１を回路基板３に実装する方法につ
いて説明する。A method for mounting the semiconductor integrated circuit device 1 provided with the protruding electrodes 2 on the circuit board 3 will be described below with reference to FIG.
【００２２】まず、半導体集積回路素子１を回路基板３
上に搭載する前工程として、半導体集積回路素子１の端
子電極に突起電極２を形成し、基板電極４にはんだ５を
形成する。突起電極２の形成方法には、突起電極２の部
材に金を用いた場合、一般的に主流であるワイヤバンピ
ング法を用いる（ステップ１）。First, the semiconductor integrated circuit device 1 is mounted on the circuit board 3.
As a pre-mounting step, the protruding electrode 2 is formed on the terminal electrode of the semiconductor integrated circuit device 1 and the solder 5 is formed on the substrate electrode 4. When gold is used for the member of the projecting electrode 2, a wire bumping method, which is generally mainstream, is used for forming the projecting electrode 2 (step 1).
【００２３】基板電極４上のはんだ５形成には、はんだ
プリコート技術の１つであるスーパージャフィット法を
用いる（ステップ２）。The solder 5 is formed on the substrate electrode 4 by using a super jafit method which is one of the solder pre-coating techniques (step 2).
【００２４】次に、予め回路基板３の半導体集積回路素
子１が搭載される部分に、半導体集積回路素子１と回路
基板３の間を充分に介在させる量の樹脂６を塗布する
（ステップ３）。Next, an amount of resin 6 sufficient to intervene between the semiconductor integrated circuit element 1 and the circuit board 3 is applied to the portion of the circuit board 3 on which the semiconductor integrated circuit element 1 is mounted (step 3). .
【００２５】次に、この樹脂６を塗布した基板電極４上
のはんだ５に突起電極２が位置するように半導体集積回
路素子１を回路基板３に位置決め搭載する。この時、半
導体集積回路素子１を吸着したボンディングツール７に
備えられたヒーター等の加熱手段により、位置決め搭載
した半導体集積回路素子１を加熱すると同時に、回路基
板３を載せた基板ステージ８に備えられたヒーター等の
加熱手段でも加熱を行う（ステップ４）。この加熱工程
では、最初、はんだ融点以上の温度に加熱して突起電極
２とはんだ５との接合部を金属接合させた後、はんだ融
点以下に加熱温度を下げて樹脂６を硬化させる。Next, the semiconductor integrated circuit device 1 is positioned and mounted on the circuit board 3 such that the protruding electrodes 2 are located on the solder 5 on the substrate electrodes 4 coated with the resin 6. At this time, the semiconductor integrated circuit element 1 that is positioned and mounted is heated by a heating means such as a heater provided in the bonding tool 7 to which the semiconductor integrated circuit element 1 has been sucked, and is simultaneously provided on the substrate stage 8 on which the circuit board 3 is mounted. Heating is also performed by a heating means such as a heater (step 4). In this heating step, first, the joint between the protruding electrode 2 and the solder 5 is metal-joined by heating to a temperature equal to or higher than the solder melting point, and then the resin 6 is cured by lowering the heating temperature to the solder melting point or lower.
【００２６】例えば、図４に示すような温度プロファイ
ルにしたがってボンディングツール７の加熱温度を変化
させると良い。ここで、ボンディングツール７の初期加
熱温度Ｔ2は、はんだ５の溶融温度に４０°Ｃから６０
°Ｃ加えた温度付近が好ましい。例えば、樹脂６がエポ
キシアクリレートを主骨格に持つ樹脂で、はんだ５が共
晶はんだである場合、ボンディングツール７の初期加熱
温度Ｔ2は２４０°Ｃが好ましい。なお、初期加熱温度
Ｔ2での加熱時間は、樹脂６の硬化反応があまり進まな
いようにするために、数秒間あるいはそれ以下とするこ
とが好ましい。For example, it is preferable to change the heating temperature of the bonding tool 7 according to a temperature profile as shown in FIG. Here, the initial heating temperature T 2 of the bonding tool 7 is set to a melting temperature of the solder 5 from 40 ° C. to 60 ° C.
It is preferable that the temperature be around the temperature added by ° C. For example, when the resin 6 is a resin having an epoxy acrylate as a main skeleton and the solder 5 is a eutectic solder, the initial heating temperature T 2 of the bonding tool 7 is preferably 240 ° C. The heating time at the initial heating temperature T 2 is preferably several seconds or less in order to prevent the curing reaction of the resin 6 from proceeding so much.
【００２７】この時、基板ステージ８の加熱温度も樹脂
６の硬化反応が進まない温度が好ましい。例えば、エポ
キシアクリレートを主骨格に持つ樹脂６では、９０°Ｃ
に設定することが好ましい。At this time, the heating temperature of the substrate stage 8 is preferably a temperature at which the curing reaction of the resin 6 does not proceed. For example, in a resin 6 having epoxy acrylate as a main skeleton, 90 ° C.
It is preferable to set
【００２８】上記初期加熱が終了した後には、樹脂６の
硬化反応を進めるために、ボンディングツール７の加熱
温度をはんだ融点以下の温度Ｔ1まで下げる。ここで、
加熱温度Ｔ1は１５０〜１８０°Ｃに設定することが好
ましい。After the completion of the initial heating, the heating temperature of the bonding tool 7 is lowered to a temperature T 1 lower than the melting point of the solder in order to advance the curing reaction of the resin 6. here,
Heating temperatures T 1 is preferably set to 150 to 180 ° C.
【００２９】以上によって、図４のＢ点では接合部での
はんだ接続が完了し、Ａ点では樹脂６の硬化が完了す
る。As described above, at the point B in FIG. 4, the solder connection at the joint is completed, and at the point A, the curing of the resin 6 is completed.
【００３０】なお、図４の例では加熱温度をはんだの融
点以下に下げた後、一定に維持する構成となっている
が、本発明では樹脂６の硬化を完了させることができる
のであれば、厳密に温度を一定に維持する必要はない。
また、図４のようにボンディングツール７の加熱温度を
変化させる代わりに、ボンディングツール７によりハン
ダ融点以上に加熱した後、半導体チップ１が実装された
回路基板３を１５０〜１８０°Ｃの温度を維持する恒温
槽に入れ、樹脂６の硬化を完了させる方法を取ってもよ
い。In the example shown in FIG. 4, the heating temperature is lowered to a temperature lower than the melting point of the solder and is kept constant. However, in the present invention, if the curing of the resin 6 can be completed, It is not necessary to maintain a strictly constant temperature.
Also, instead of changing the heating temperature of the bonding tool 7 as shown in FIG. 4, after the soldering point is heated by the bonding tool 7 to a temperature equal to or higher than the melting point, the circuit board 3 on which the semiconductor chip 1 is mounted is heated to a temperature of 150 to 180 ° C. It is also possible to adopt a method in which the resin 6 is placed in a constant temperature bath and the curing of the resin 6 is completed.
【００３１】以上のプロセスにより、図１に示すフリッ
プチップ接続構造体が得られる。By the above process, the flip chip connection structure shown in FIG. 1 is obtained.
【００３２】本実施形態によれば、図１に示すフリップ
チップ接続構造体は、半導体集積回路素子１の端子電極
上に形成した突起電極２と基板電極４上に形成したはん
だ５とが金属接合することで電気的に接続され、更に半
導体集積回路素子１と回路基板３間に介在する樹脂６が
応力を緩和することで組立時の歩留まりを向上すること
ができる。According to the present embodiment, in the flip-chip connection structure shown in FIG. 1, the bump electrode 2 formed on the terminal electrode of the semiconductor integrated circuit element 1 and the solder 5 formed on the substrate electrode 4 are bonded to each other. By doing so, the resin 6 interposed between the semiconductor integrated circuit element 1 and the circuit board 3 relieves the stress, so that the yield at the time of assembly can be improved.
【００３３】さらに、突起電極２に金を用いた場合、突
起電極２とはんだ５は金―はんだの金属接合であるため
低接続抵抗を実現することができる。Further, when gold is used for the protruding electrode 2, a low connection resistance can be realized because the protruding electrode 2 and the solder 5 are a metal joint of gold and solder.
【００３４】さらに、本実施形態におけるフリップチッ
プ接続方法では、最初にはんだ融点以上の温度を加え接
合部を接続した後、樹脂６の硬化を行っているため、は
んだ溶融時には接続部周辺の樹脂６が硬化していない。
このため、はんだ溶融時にはんだ外へ排出される予めは
んだ内に含有されていたガスは、硬化していない樹脂６
を通過して外気へ排出される。Further, in the flip-chip connection method according to the present embodiment, the resin 6 is cured after the joint is connected by first applying a temperature equal to or higher than the melting point of the solder. Is not cured.
For this reason, the gas previously contained in the solder, which is discharged out of the solder when the solder is melted, is removed from the uncured resin 6.
And is discharged to the outside air.
【００３５】本実施形態によれば、フリップチップ接続
構造体の接合部にガスが蓄積されることがなく、その結
果、該構造体の信頼性の向上を図ることができる。According to this embodiment, no gas is accumulated at the joint of the flip-chip connection structure, and as a result, the reliability of the structure can be improved.
【００３６】本実施形態によるフリップチップ接続構造
体について信頼性試験を行った結果、耐はんだリフロ性
（２４０°Ｃ１０分を４回など）後においても接続抵抗
の変化は少なく１から３ミリオーム程度であり、―５５
°Ｃ〜１２５°Ｃ各３０分の熱衝撃試験３００回や高温
高湿試験（６５°Ｃ９５％ＲＨ）３００時間においても
大きな接続抵抗の変化は見られなかった。As a result of performing a reliability test on the flip-chip connection structure according to the present embodiment, the change in the connection resistance is small even after the solder reflow resistance (240 ° C., 10 minutes, etc., four times) and is about 1 to 3 milliohms. Yes, -55
No significant change in the connection resistance was observed even after 300 times of the thermal shock test for 30 minutes each in ° C to 125 ° C or 300 hours in the high-temperature and high-humidity test (65 ° C, 95% RH).
【００３７】[0037]
【発明の効果】本発明によれば、半導体集積回路素子を
回路基板に直接搭載するフリップチップ接続構造体の製
造において、管理が困難である導電性接着剤を使用せ
ず、更にはんだ融点以上の温度を加え接合部を接続した
後、樹脂の硬化を行うため、はんだ溶融時に予めはんだ
内に含有されていたガスは、硬化していない樹脂を通過
して外気に排出され、接合部に蓄積されることなく、接
続信頼性の向上を図ることができる。According to the present invention, in manufacturing a flip-chip connection structure in which a semiconductor integrated circuit element is directly mounted on a circuit board, a conductive adhesive which is difficult to control is not used, and furthermore, a solder melting point or higher is used. After applying the temperature and connecting the joints, the resin is cured, so that the gas previously contained in the solder at the time of melting the solder passes through the uncured resin, is discharged to the outside air, and is accumulated in the joints. Without this, the connection reliability can be improved.
【図１】本発明の一実施形態における接続構造体の断面
図である。FIG. 1 is a sectional view of a connection structure according to an embodiment of the present invention.
【図２】本発明の一実施形態におけるプロセス図であ
る。FIG. 2 is a process diagram in one embodiment of the present invention.
【図３】従来技術におけるプロセス図である。FIG. 3 is a process diagram according to the related art.
【図４】本発明の一実施形態における加熱工程での加熱
プロファイルの一例を示すグラフである。FIG. 4 is a graph showing an example of a heating profile in a heating step in one embodiment of the present invention.
１…半導体集積回路素子、 ２…突起電極（バンプ）、 ３…回路基板、 ４…基板電極、 ５…はんだ、 ６…樹脂、 ７…ボンディングツール、 ８…基板ステージ、 ９…導電性接着剤、 １０…容器（転写トレイ）。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit element, 2 ... Protruding electrode (bump), 3 ... Circuit board, 4 ... Board electrode, 5 ... Solder, 6 ... Resin, 7 ... Bonding tool, 8 ... Board stage, 9 ... Conductive adhesive, 10 ... Container (transfer tray).
Claims (3)
を有し、基板電極上にはんだを有する回路基板に、突起
電極を有する回路素子を実装するフリップチップ接続方
法において、 前記回路素子を前記回路基板上の目的とする部位に位置
決め搭載した後、加熱する加熱工程を含み、 前記加熱工程は、加熱温度を前記はんだの融点以上まで
上昇させて前記はんだを溶融させる第１の工程と、該加
熱温度を前記はんだの融点以下まで下降させて前記熱硬
化性樹脂の硬化反応を進める第２の工程とを含むことを
特徴とするフリップチップ接続方法。1. A flip-chip connection method for mounting a circuit element having a protruding electrode on a circuit board having a thermosetting resin in a portion where the circuit element is mounted and having solder on a substrate electrode, After positioning and mounting at a target portion on the circuit board, includes a heating step of heating, the heating step is a first step of melting the solder by raising the heating temperature to the melting point of the solder or more A second step of lowering the heating temperature to the melting point of the solder or lower to advance the curing reaction of the thermosetting resin.
り、 前記はんだは共晶はんだ及び錫、銀はんだのいずれかで
あり、 前記熱硬化性樹脂はエポキシアクリレート、フェノール
エポキシ及びシアノアクリレートのうちいずれかを主骨
格とする部材であることを特徴とする請求項１に記載の
フリップチップ接続方法。2. The circuit element is a semiconductor integrated circuit element, wherein the solder is one of eutectic solder and tin or silver solder, and the thermosetting resin is one of epoxy acrylate, phenol epoxy and cyano acrylate. The method of claim 1, wherein the member is a member having a main skeleton.
はんだを有する回路基板とからなり、該回路素子と回路
基板との間に熱硬化性樹脂を介在するフリップチップ接
続構造体において、 前記突起電極と前記はんだとの金属接合は、前記熱硬化
性樹脂の硬化が完了する前に形成されたものであること
を特徴とするフリップチップ接続構造体。3. A flip chip connection structure comprising a circuit element having a protruding electrode and a circuit board having solder on a substrate electrode, wherein a thermosetting resin is interposed between the circuit element and the circuit board. A flip-chip connection structure, wherein the metal joint between the protruding electrode and the solder is formed before the curing of the thermosetting resin is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3142498A JPH11233558A (en) | 1998-02-13 | 1998-02-13 | Flip-chip connection method and connection structure body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3142498A JPH11233558A (en) | 1998-02-13 | 1998-02-13 | Flip-chip connection method and connection structure body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11233558A true JPH11233558A (en) | 1999-08-27 |
Family
ID=12330872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3142498A Pending JPH11233558A (en) | 1998-02-13 | 1998-02-13 | Flip-chip connection method and connection structure body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11233558A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003289089A (en) * | 2002-03-28 | 2003-10-10 | Sumitomo Bakelite Co Ltd | Semiconductor device and its manufacturing method |
| US8581403B2 (en) | 2008-01-30 | 2013-11-12 | Nec Corporation | Electronic component mounting structure, electronic component mounting method, and electronic component mounting board |
| JP2020106584A (en) * | 2018-12-26 | 2020-07-09 | エルジー ディスプレイ カンパニー リミテッド | Display device and method for manufacturing display device |
-
1998
- 1998-02-13 JP JP3142498A patent/JPH11233558A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003289089A (en) * | 2002-03-28 | 2003-10-10 | Sumitomo Bakelite Co Ltd | Semiconductor device and its manufacturing method |
| US8581403B2 (en) | 2008-01-30 | 2013-11-12 | Nec Corporation | Electronic component mounting structure, electronic component mounting method, and electronic component mounting board |
| JP2020106584A (en) * | 2018-12-26 | 2020-07-09 | エルジー ディスプレイ カンパニー リミテッド | Display device and method for manufacturing display device |
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