JPH11232081A - Information processing system and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable an efficient processing by efficiently determining whether each processing module is to be executed by a software or by a hardware when executing series of processing composed of plural processing modules. SOLUTION: An application program 100 is composed of plural software modules SM describing processings in a program language (or hardware modules describing the processings in circuit information reconstituted in a programmable logic circuit 400). A hardware module (software module) to perform the same processing as the processing to be performed by the software module (or hardware module HM) in the program is acquired from a storage device 200 in a system or on a network. An execution module determining means 600 is provided for determining whether the processing module described in the program is to be executed by the software module or by the hardware module before the execution of the program or at the time of execution.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system and an information processing method capable of processing at least part of a process by a programmable logic circuit whose circuit configuration can be reconfigured. It relates to the effective use of circuits.

[0002]

2. Description of the Related Art In the field of digital circuit devices, in particular, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and programmable logic devices (PGAs) have been developed in order to shorten the development period of products.
2. Description of the Related Art Programmable logic circuits including LDs) are widely used.

[0003] These programmable logic circuits can freely configure internal logic circuits and connections between the logic circuits by reading circuit information describing the logic circuits. For this reason, the use of the programmable logic circuit device has an advantage that the time required to manufacture an integrated circuit, which conventionally required several weeks to several months after the completion of circuit design, becomes unnecessary. In particular, U.S. Pat.
An electrically reconfigurable programmable logic circuit device such as the invention of 187 has the advantage that a circuit once manufactured can be freely changed as many times as necessary, and the programmable logic circuit device becomes more and more widely used. It is being used.

[0004] Recently, logic circuits have increased in complexity, and the circuit scale has increased to a level that cannot be realized by a single programmable logic circuit device.

As one method for solving this problem, it has been proposed to reconfigure a programmable logic circuit during processing in order to realize different logic circuits at different times. By using this method, there is an advantage that various processes can be performed at a relatively high speed even when the size of a circuit that can be built in is limited because the device is small like a portable information terminal.

However, when the programmable logic circuit is reconfigured, the circuit information of the entire circuit is read again, so that there is a disadvantage that the reconfiguration takes time. Further, reconfiguring in the middle of the process means that the process is temporarily suspended, the data at that time is saved in a storage device outside the programmable logic circuit, new circuit information is read and reconfigured, and the data before reconfiguration is reconstructed. And extra processing of inputting new data for reconstruction is required.

In order to solve this problem, a programmable logic circuit described in a data book named “CONFIGURABLE LOGIC” by Atmel, USA, and “THE PROGR,” manufactured by Xilinx, USA.
A programmable logic circuit described in a data book named "AMMABLE LOGIC" has a data storage device for storing data, and reads part of circuit information from an external storage device during operation of the circuit to partially store the circuit information. By performing the reconfiguration, the time required for the reconfiguration is minimized.

The problem when using such a programmable logic circuit in an information processing system is that processing is performed by a programmable logic circuit and processing is performed by a fixed logic circuit device such as a microprocessor whose circuit configuration cannot be changed. Therefore, the technology for separation has not been established.

As one of the methods for solving this problem,
There is an example of a computer disclosed in JP-A-6-301522. This will be described as Conventional Example 1 with reference to FIG.

That is, in the conventional example 1 of FIG.
The source program 1000 executed by the computer includes a fixed unit whose circuit configuration cannot be changed and a variable unit whose circuit configuration can be changed like a programmable logic circuit. The library 1001 includes information on the configuration of the fixed unit,
Information on a circuit that can be configured by the variable unit is stored.

The compiler 1002 analyzes the source program 1000 and converts it into object code and hardware configuration data while referring to the library 1001. For example, the compiler 1002 analyzes the flow of the source program, detects the frequency of the function, determines a function having a large number of calls as a function to be processed by hardware based on the detected frequency, and generates hardware configuration data 1003. Create and output.

Next, the compiler 1002 generates a code indicating that a part determined to be processed by hardware is processed by a predetermined variable part. Then, this code is added to a portion to be processed by the remaining software to create and output an object code 1004. Computer 1005
Executes a process according to the object code by using a fixed unit and a variable unit configured by hardware configuration data.

As described above, in the first conventional example, the speed of the entire process is increased by implementing a function having a large number of calls at the time of compilation at the time of compiling.

Next, as a second conventional example which solves the above problem, a case of a computer device disclosed in Japanese Patent Laid-Open No. 5-150943 will be described. In the second conventional example, processing separated by a programmable logic circuit and processing performed by a fixed logic circuit device is executed by a computer as an information processing system as an application program.

The computer device of the second prior art is composed of a CP
U, a memory, a programmable logic circuit, an external storage device such as a hard disk, and other input / output interfaces.

The external storage device stores circuit data of the programmable logic circuit and an application program. The memory stores an initial loading program for loading an application program from an external storage device.

The CPU executes these programs and writes circuit data into the programmable logic circuit. The programmable logic circuit is connected to a bus line of the CPU, inputs a signal on the bus line, performs logic processing, and returns a signal to the bus line. FIG. 36 shows a processing procedure in the second conventional example.

First, a program file to be executed is specified (step S1). Next, it is determined whether or not the specified program file contains circuit data (step S2). If so, the circuit data writing program is loaded and executed (step S3), and then the circuit data is loaded. Then, the circuit data is written into the programmable logic circuit (step S5).
Thereafter, the application program is loaded (Step S6) and executed (Step S7).

If the specified program file does not contain circuit data, the process jumps from step S2 to step S6, where the application program is loaded and executed as it is.

As described above, in the case of the conventional example 2, the circuit performs a predetermined logic process when executing an instruction using a function on the programmable logic circuit. This makes it possible to increase the speed of processing by configuring a necessary logic circuit without providing special hardware for each application.

An information processing system for processing a part of the processing described above by a programmable logic circuit can be used by connecting to a network. As one example of such a case, an image reproducing apparatus disclosed in Japanese Patent Application Laid-Open No. 9-74556 will be described as Conventional Example 3 below.

As shown in FIG. 37, the image reproducing apparatus of the third conventional example has a moving image decoding unit 1100 capable of reconfiguring a processing system, and a program for reconfiguring the moving image decoding unit 1100. Receiving section 1200 for downloading encoded moving image data from network NT
A switching unit 1300 for switching a transmission destination depending on whether received data is a program or moving image data, a program converting unit 1400 for converting the program into a format changeable to the structure of the moving image decoding unit 1100, and a receiving unit 1200
Control unit 150 for controlling switching unit 1300, program conversion unit 1400, and video decoding unit 1100
It consists of 0.

The video decoding unit 1100 inversely quantizes the quantized image data and can change the content of the inverse quantization processing, and inversely transforms the converted image data. And an inverse conversion unit 1102 that can change the content of the inverse conversion process.

The program conversion unit 1400 converts the program into a format that can change the configuration of the moving image decoding unit 1100 (a hardware processing unit), and a second unit that is executed by the control unit 1500 when reproducing a moving image. A dividing unit 1401 for dividing the program into two program parts (software processing parts), a first converting unit (hardware compiler) 1402 for converting the first program part into a format capable of changing the configuration of the video decoding unit 1100, A second conversion unit (software compiler) 1403 for converting the second program portion into a format that can be decoded by the control unit 1500 and executed.

This image reproducing apparatus receives a moving image reproducing program and encoded moving image data from the network NT, and operates as follows.

First, the receiving unit 1200 receives a reproduction algorithm program described in a logical description language. The received data is transmitted to the program conversion unit 1400 through the transmission switching unit 1300, and divided by the division unit 1401 into a hardware processing part and a software processing part.

The hardware processing section includes a first conversion section 1
Passed to 402, programmable logic circuit (FPGA)
Is converted into a rewriteable format (bit stream), and the inverse quantization unit 1101 and the inverse transformation unit 1102 are rewritten under the control of the control unit 1500. Also,
The software processing part is passed to the second conversion unit 1403, converted into a format that can be processed by the processor, and then passed to the control unit 1500.

When moving image data is sent from the network NT to the image reproducing apparatus of FIG. 37 configured as described above, the moving image data is received by the receiving unit 1200, transmitted to the moving image decoding unit 1100 by the switching unit 1300, and decoded. Is output as Inverse quantization unit 1101 and inverse transformation unit 110
2 is composed of an element whose circuit configuration can be changed, so that it is possible to cope with image data reproduced by a different algorithm.

As described above, in the examples shown in the conventional examples 1 to 3, the part processed by the hardware by the programmable logic circuit and the part processed by the software by the microprocessor are fixedly determined. An example in which hardware processing is replaced by software processing will be described as Conventional Example 4.

[0030] Proceedings of the
IEEE Symposium on FPGAs f
or Custom Computing Machi
Nes (1996), pp. 195-203, "Supporting FPGA M
microprocessors through Re
targetable Software Tool
In “s”, a method of debugging a program used in a technology (DISC) of using a programmable logic circuit that can be rewritten during operation as a processor is described.

In the paper of the conventional example 4, it is shown that a routine for processing by hardware is performed by software at the time of debugging in order to debug the software in a short time. This is because a routine that is repeatedly executed when executing a program need only be processed once during debugging, so that a hardware module having a large circuit scale is reconfigured in a programmable logic circuit over a longer time than processing time. This is because it is more efficient to execute and debug by software than to execute by software. Which process is performed at the time of debugging is specified by a debugging program.

[0032]

However, the conventional examples 1 to 4 relating to the information processing system in which a part of the processing is processed by the programmable logic circuit described above have the following problems.

In the first conventional example, the processing to be executed by the programmable logic circuit is determined centrally in a single program such as a function having a large number of calls. Therefore, when the information processing system performs a plurality of processes as a series of processes at once using a plurality of programs, there is a disadvantage that the processes using the programmable logic circuit cannot be efficiently used.

For example, if the number of calls in one program is small, but there are a number of functions that are commonly called in the entire processing sequentially executed as a series of processing, the processing is executed by the programmable logic circuit. It is more efficient and better. However, in the first conventional example, it is not possible to determine that the processing of the function having a small number of calls in one program is executed by the programmable logic circuit.

Also, depending on the function, the size of the corresponding circuit information is large, so that it takes a long time to reconfigure the circuit information in the programmable logic circuit. Even if the number of calls is large, the processing time of the software processing is shorter. In some cases, in the first conventional example, such a function process is determined to be a process by the programmable logic circuit because of the large number of calls.

In the second conventional example, a portion to be processed by hardware is predetermined for each application, and the portion to be processed by the hardware is mounted on a programmable logic circuit before the start of a program. Therefore, there is a problem that software processing that does not require hardware processing is not started until the circuit configuration is completed.

In particular, when the writing time to the programmable logic circuit is long due to the large size of the circuit data, the entire processing time may be shorter if the processing is performed by software having a lower processing speed than the hardware processing.

That is, in the case of the conventional example 2, attention is paid only to the processing time of each hardware processing and software processing, and no consideration is given to shortening the entire processing time including the reconfiguration time of the programmable logic circuit. There is a problem.
In addition, since the programmable logic circuit is reconfigured for each program, a circuit commonly used when executing a plurality of programs is also redundantly configured.
There is also the problem of inefficiency.

In Conventional Example 3, a program described in a logical description language is downloaded from a network.
There is a problem that it takes time to convert the program into circuit information in the image reproducing apparatus.

That is, in the process of converting the logic description language into circuit information, the logic description language is converted into a netlist, and the netlist is subjected to technology mapping according to a device, layout and layout processing is performed, and the result is further converted. Must be converted to circuit information. In particular, it is known that the placement and routing process has a complicated algorithm and takes a long time.

That is, in the conventional example 3, in order to make the programs stored in the server on the network and shared by the client compatible, a description method with a high level of abstraction such as a logical description language is used. However, there is a problem in that the amount of pre-processing at the client becomes large, and the entire processing time becomes long enough to impair the reduction of the processing time by hardware processing.

Furthermore, in the third conventional example, the program is obtained from the network. However, in the transmission over the network, the communication may be interrupted on the way and the program may not be downloaded. is there.

In the conventional example 4, when the program is executed, if the number of repetition processings is one or more, the processing is performed by software rather than mounting the hardware module in a programmable logic circuit. Although processing time may be shorter, hardware processing is replaced with software processing only at the time of debugging. That is, there is a problem in that the reduction of the entire processing time including the reconfiguration time of the programmable logic circuit at the time of program execution is not considered.

As problems common to the above-mentioned conventional examples 1 to 4, the reconfiguration time of the programmable logic circuit including the time for acquiring the circuit information and the common time among a plurality of programs executed as a series of processing are common. The processing is unified into hardware processing and software processing without considering the processing to be used.

In view of the above, the present invention provides an information processing system that performs a plurality of processes as a series of processes at a time, and performs processing by the programmable logic circuit in consideration of the reconfiguration time of the programmable logic circuit. In order to perform efficient processing as a whole of the series of processing,
The purpose is to be able to utilize it.

[0046]

In order to solve the above-mentioned problems, an information processing system according to the first aspect of the present invention comprises a program constituted by a plurality of processing modules each comprising a software module in which processing is described in a program language. An information processing system that executes a series of processes to be described, and a part of the series of processes can be processed by a programmable logic circuit, and is the same as a process performed by a software module in the program. A storage unit for storing a hardware module in which processing is described by circuit information for reconfiguring the programmable logic circuit, and a hardware unit for obtaining the hardware module from the storage unit and reconfiguring the programmable logic circuit A software module acquisition means, and a processing module described in the program. Le, said software module, whether to run in either the hardware module, and execution module determination means for determining prior to execution of said program, characterized in that it comprises.

According to a second aspect of the present invention, a series of processes described by a program composed of a plurality of processing modules including software modules in which processes are described in a program language are executed, and An information processing system in which a part of the series of processes can be processed by a programmable logic circuit, wherein the same process as that performed by a software module in the program is described by circuit information reconfigured in the programmable logic circuit. A storage unit for storing the hardware module, a hardware module obtaining unit for obtaining the hardware module from the storage unit and reconfiguring the programmable logic circuit, and a processing module described in the program. , The software module;
Which of the hardware modules should be executed,
Execution module determining means for determining when the processing module of the program is executed.

According to a third aspect of the present invention, there is provided a plurality of processing modules comprising a hardware module in which a part of the processing can be processed by a programmable logic circuit and the processing is described by circuit information included in the programmable logic circuit. An information processing system that executes a series of processes described by a program configured by the same process as the process performed by the hardware module in the program,
A storage unit for storing a software module described in a programming language; a software module obtaining unit for obtaining the software module from the storage unit and storing the software module in a storage unit for an execution program; An execution module determining unit that determines whether the processing module is executed by the software module or the hardware module before the execution of the program.

According to a fourth aspect of the present invention, a plurality of processing modules, each of which can be partially processed by a programmable logic circuit, are composed of hardware modules in which the processing is described by circuit information included in the programmable logic circuit. An information processing system that executes a series of processes described by a program configured by the same process as the process performed by the hardware module in the program,
A storage unit for storing a software module described in a programming language; a software module obtaining unit for obtaining the software module from the storage unit and storing the software module in a storage unit for an execution program; An execution module determining unit that determines whether the processing module executed by the software module or the hardware module is to be executed when the processing module of the program is executed.

According to a fifth aspect of the present invention, a series of processes described by a program composed of a plurality of processing modules including software modules in which processes are described in a program language are executed, and An information processing system in which a part of the series of processes can be processed by a programmable logic circuit, wherein the same process as that performed by a software module in the program is described by circuit information reconfigured in the programmable logic circuit. A hardware module obtaining means for obtaining the hardware module through a network and reconfiguring the programmable logic circuit; and a processing module described in the program, the software module,
Which of the hardware modules should be executed,
Execution module determining means for determining before executing the program.

According to a sixth aspect of the present invention, a series of processes described by a program composed of a plurality of processing modules each including a software module in which processes are described in a program language are executed. Is an information processing system in which a part of the processing can be performed by a programmable logic circuit, wherein the same processing as that performed by a software module in the program is described by circuit information reconfigured in the programmable logic circuit. A hardware module obtaining means for obtaining a hardware module through a network and reconfiguring the programmable logic circuit; and executing the processing module described in the program by the software module or the hardware module. In the processing of the program. Characterized in that it comprises a execution module determination means for determining when the module execution.

According to a seventh aspect of the present invention, a plurality of processing modules each including a hardware module in which a part of the processing can be processed by a programmable logic circuit and the processing is described by circuit information included in the programmable logic circuit. An information processing system that executes a series of processes described by a program configured by the same process as the process performed by the hardware module in the program,
A software module obtaining means for obtaining a software module described in a programming language through a network and storing the software module in a storage unit for an execution program; a processing module described in the program as a software module; Execution module determining means for determining which of the two is to be executed before the execution of the program.

According to a further aspect of the present invention, a plurality of processing modules comprising a hardware module in which a part of the processing can be processed by a programmable logic circuit, and the processing is described by circuit information included in the programmable logic circuit. An information processing system that executes a series of processes described by a program configured by the same process as the process performed by the hardware module in the program,
A software module obtaining means for obtaining a software module described in a programming language through a network and storing the software module in a storage unit for an execution program; a processing module described in the program as a software module; Execution module determining means for determining which of the two is executed when the processing module of the program is executed.

According to a ninth aspect of the present invention, in the information processing system according to the first, second, fifth, or sixth aspect, the hardware module performs the same processing as the processing performed by the software module. Is described in a program, and the hardware module obtaining means obtains a hardware module corresponding to the identification code and reconfigures the programmable logic circuit.

According to a tenth aspect of the present invention, in the information processing system according to the third, fourth, seventh or eighth aspect, the software module performs the same processing as that performed by the hardware module. Is described in a program, and the software module obtaining means obtains a software module corresponding to the identification code and stores the software module in the execution program storage unit. .

According to an eleventh aspect of the present invention, in the information processing system according to the ninth aspect, there is provided an identification code recording means for recording an identification code of a hardware module reconfigured in the programmable logic circuit, The hardware module obtaining means obtains a hardware module corresponding to an identification code not recorded in the identification code recording means among the identification codes of the hardware modules described in the program, and obtains the programmable logic circuit. Is reconfigured.

According to a twelfth aspect of the present invention, in the information processing system according to the tenth aspect, there is provided an identification code recording means for recording an identification code of a software module stored in the execution program storage unit, The software module obtaining means obtains a software module corresponding to an identification code not recorded in the identification code recording means among identification codes of the software modules described in the program, and executes the execution program. It is stored in the storage unit.

According to a thirteenth aspect of the present invention, in the information processing system according to the ninth aspect, the information processing system further includes identification code recording means for recording an identification code of a hardware module reconfigured in the programmable logic circuit. The hardware module obtaining means obtains at least one or more hardware modules corresponding to the identification code recorded in the identification code recording means before executing the program, and reconfigures the programmable logic circuit. It is characterized by.

According to a fourteenth aspect of the present invention, in the information processing system according to the tenth aspect, there is provided an identification code recording means for recording an identification code of a software module stored in the execution program storage unit, The software module acquisition unit acquires at least one software module corresponding to the identification code recorded in the identification code recording unit before executing the program, and stores the acquired software module in the execution program storage unit. It is characterized by doing.

According to a fifteenth aspect of the present invention, in the information processing system according to any one of the first to fourteenth aspects, the execution module determining means refers to an execution module selection condition set in advance. It is characterized in that it is determined whether the processing module described by the program is executed by the software module or the hardware module.

According to a sixteenth aspect of the present invention, in the information processing system according to the second, fourth, sixth, or eighth aspect, the execution module determining means executes the processing module when executing the processing module. As the execution module selection condition, it is determined whether or not the reconfiguration of the hardware module of the process to be executed into the programmable logic circuit has been completed, and when the reconfiguration has been completed,
The processing is determined to be executed by a programmable logic circuit reconfigured by a hardware module.

According to a seventeenth aspect of the present invention, in the information processing system according to the second, fourth, sixth or eighth aspect, the programmable logic by a hardware module is executed in parallel with the execution of the program. The circuit is reconfigured, and when the processing module is executed, it is determined whether or not the reconfiguration of the hardware module of the processing to be executed to the programmable logic circuit has been completed, and the reconfiguration has been completed. In some cases, the processing is determined to be executed by a programmable logic circuit reconfigured by a hardware module.

According to an eighteenth aspect of the present invention, in the information processing system according to the second, fourth, sixth, or eighth aspect, the identification code indicating the hardware module is described in a program. And an identification code recording means for recording an identification code of the hardware module reconfigured in the programmable logic circuit. The execution module selection means, when the processing module is executed, the identification code recording means When the identification code of the hardware module of the process to be executed is recorded in the identification code recording unit, it is determined that the reconfiguration of the hardware module has been completed, and the process is executed by hardware. The decision to execute on a programmable logic circuit reconfigured by the module To.

[0064]

In the information processing system according to the present invention, one of a software module and a hardware module is described in a program in advance, and the other of the software module and the hardware module is included in the system. Are stored in the storage device section.

The hardware (or software) module stored in the storage unit is read out by hardware (or software) acquisition means,
Circuit information is reconfigured (or stored in the storage unit) in the programmable logic circuit.

The execution module determining means determines whether to execute a processing unit by a software module or a hardware module at the time of executing a program or before executing the program.

As in the prior art, the software processing part and the hardware processing part are not fixedly determined in advance in the application program.
At the time of the determination of the execution module, it can be determined to select an efficient execution module as the whole process described in the program based on various conditions that also take into account the reconfiguration time of the programmable logic circuit. .

In the inventions of claims 5 to 8, the hardware module or the software module is not provided in the system, but is obtained through a network.

Therefore, in the case of the present invention, it is necessary to provide a storage unit for storing hardware modules in advance and a storage unit for storing software modules in advance in the system. However, the system configuration can be simplified. Even if it is difficult to obtain a hardware module or a software module from the network due to a fault in the network, the same processing is executed in the case of the present invention. Since there are software modules and hardware modules that perform processing, it is possible to continue processing without interruption by using them.

In the information processing system according to the ninth and tenth aspects of the present invention, the identification code of the hardware module corresponding to the software module or the identification of the software module corresponding to the hardware module is included in the program. The code is described.
The hardware module obtaining means obtains the hardware module indicated by the identification code and reconfigures the programmable logic circuit. Further, the software module indicated by the identification code is obtained and stored in an execution program storage unit such as a main memory.

Therefore, in the ninth and the first aspects of the present invention,
According to the invention of No. 0, it is not necessary to acquire and store in advance a correspondence between a software module and a hardware module constituting a program as a table or the like.

In the information processing system according to the eleventh aspect of the present invention, the identification code of the hardware module which has been reconfigured in the programmable logic circuit is stored in the identification code storage means. The hardware module obtaining means obtains a hardware module corresponding to an identification code not recorded in the identification code storage means among the identification codes of the hardware modules described in the program, and obtains the programmable logic circuit. Reconfigure.

Therefore, according to the eleventh aspect of the present invention, the same circuit information as that already reconfigured in the programmable logic circuit is not reconfigured in the programmable logic circuit, and the reconfiguration time is wasted. Can be omitted, and hardware processing using circuit information already reconfigured into a programmable logic circuit can be efficiently used.

In the information processing system according to the twelfth aspect of the present invention, the identification code of the software module already stored in the execution program storage unit is stored in the identification code storage unit. Then, the software module obtaining means obtains a software module corresponding to an identification code not recorded in the identification code storage means among the identification codes of the software modules described in the program, and Store in the storage unit.

Therefore, according to the twelfth aspect of the present invention, the same information as the software module already stored in the execution program storage unit is not rewritten in the execution program storage unit. Waste can be eliminated, and the already stored software modules can be used efficiently.

According to the thirteenth aspect of the present invention, when processing by an application program of the same type has been performed in the past, some identification codes stored in the identification code storage means of the hardware module are used. Get the hardware module before running the program,
Reconfigure to a programmable logic circuit. As a result, the reconfiguration of the programmable logic circuit by the hardware module whose use is predicted in advance is performed before the execution of the program, and the processing time as a whole can be reduced.

According to the fourteenth aspect of the present invention, when processing of the same type of application program has been performed in the past, the identification code stored in the identification code storage means of the software module is used for some of them. Get the software module before running the program,
It is stored in the execution program storage unit. Thereby, the software module whose use is predicted in advance is stored in the execution program storage unit before the execution of the program, and the processing time as a whole can be reduced.

According to the invention of claim 15, an execution module selection condition is set in advance, and the execution module selection condition is referred to at the time of execution of a program to be executed by either the software module or the hardware module. Decide what to do. Therefore, in the invention of claim 15, by setting the execution module selection condition in advance, not only the processing time but also other modules can be used to determine which module to execute the processing. can do.

For example, as the execution module selection condition, the smaller of the reconfiguration time of the hardware module into the programmable logic circuit and the processing time of the software module, or the case where the memory consumption for processing is different between the two modules, The smaller of its memory consumption,
There are various types, such as the one in which the execution time required for the processing by the software module and the hardware module is short, the combination of the above, and the like, which can be set by the user according to various requests.

Further, in the invention according to claim 16, when the execution module determining means attempts to execute the processing,
If the reconfiguration of the hardware module corresponding to the processing has been completed, it is determined that hardware processing by a programmable logic circuit is executed instead of software processing.

Regarding the processing time, generally, hardware processing is faster than software processing, so that the processing time as a whole can be reduced by adopting the invention of claim 16.

According to the seventeenth aspect of the present invention, the start of the program is started by software processing, and at the same time, the reconfiguration of the program logic circuit by the hardware module is performed in parallel. Then, when executing the processing unit,
When the reconfiguration of the programmable logic circuit has been completed, hardware processing using the programmable logic circuit is executed.

For example, in the case of repetitive processing, the first processing is executed by software processing, but the same processing is performed by hardware processing after the reconfiguration of the programmable logic circuit is completed.

Even though it is a repetitive process, from the beginning,
If the processing by the programmable logic circuit is to be unified, the start of the processing is delayed until the reconfiguration of the programmable logic circuit is completed. Since the processing is performed by the wear processing, reduction of the processing time can be expected as a whole.

According to the eighteenth aspect of the present invention, the hardware module corresponding to the identification code stored in the identification code storage means has already been reconfigured into a programmable logic circuit. Then, the hardware module is acquired from the storage unit or the network, and the execution module determination unit determines to select the processing by the hardware module without executing the reconfiguration.

Therefore, the hardware modules that have already been reconfigured do not overlap and are reconfigured, and the time for reconfiguring the programmable logic circuit can be omitted. As a result, the overall processing time can be shortened and the efficiency can be reduced. Good processing can be performed.

[0087]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of an information processing system according to the present invention will be described below with reference to the drawings.

[First Embodiment] An information processing system according to the present invention, in which at least a part of the processing is processed by a programmable logic circuit whose circuit configuration can be reconfigured, is first described.
FIG. 1 shows a main conceptual configuration of the embodiment.

In this embodiment, a target application program (which may be simply called a program) 100 separates a series of processes to be executed by the program into a plurality of processes. It is configured as a module. This module is referred to as a processing module in this specification.

In the first embodiment, the program 1
Each processing module constituting 00 is configured by a software program whose processing is described in a programming language so that the CPU executes the processing. This software program is called a software module SM. Therefore, in the case of this embodiment,
The application program 100 includes a set of a plurality of software modules SM.

In this embodiment, the storage device 20
0, a module HM in which the same processing as the processing performed by each of the software modules SM is described by circuit information for reconfiguring into a programmable logic circuit (this module is referred to as a hardware module in this specification) is stored and prepared. I do. The storage device 200 may be provided in the information processing system, or may be a storage device on a network.

In the case of this example, the program 100
As shown in (1), it is composed of a header part HED and a main part PRG, and the main part PRG is composed of a set of a plurality of software modules SM as described above. And
In the header HED, the identification code ID of the corresponding hardware module HM, which is described by circuit information for reconfiguring the same processing as each software module SM into a programmable logic circuit, is described.

In this case, the identification code ID is described in the program 100 so that the software module SM and the hardware module HM that perform the same processing are associated with each other. For example, in this example, each software module SM is arranged in the order according to the processing execution order on the program of the plurality of software modules SM of the main body PRG.
Code ID of hardware module HM corresponding to
Is described in the header section HED.

Hardware module acquisition means 300
Is the identification code ID described in the program 100
By using the hardware module HM that executes the same processing as that executed by the software module SM,
It is obtained from the storage device 200 in the system or from the storage device 200 on the network. Then, the hardware module acquisition unit 300 reconfigures the circuit based on the acquired hardware module HM on the programmable logic circuit 400.

The software processing by the software module SM of the program 100 is executed by the CPU 500.

Actual application program 100
Is executed by the execution module determining means 600 for each processing module, selecting which of the software module SM and the hardware module HM is to be executed. In this embodiment, the execution module determining unit determines which module executes the processing module based on the execution module selection condition set in the selection condition setting unit 700.

In the selection condition setting means 700, various selection condition items such as processing time by software or hardware, memory consumption, and reconfiguration time of a programmable logic circuit are assumed in advance. Alternatively, an execution module selection condition can be set by combining a plurality of condition items.

The selection condition setting means 700 is provided so that the execution module selection condition can be changed by the user. Therefore, specific execution module selection conditions are determined in advance for the execution module determination means 600, and without changing the selection conditions,
When the execution module is determined according to the selection condition, the selection condition setting means 700 is included in the execution module determination means 600. In this case, there is no need to particularly provide the execution module.

The execution module is determined by the execution module determining means 600 before the program is executed or when the program is executed. In the first embodiment, the processing is performed at the time of executing the program and at the time of starting execution of each processing module.

[Example of Hardware Configuration of First Embodiment] FIG. 3 is a block diagram showing an example of a hardware configuration of an information processing system 10 according to the first embodiment of the present invention. In the information processing system 10 of this embodiment, the chipset 1 is connected to the host bus 11B of the CPU 11.
2, a main memory 13 composed of a DRAM is connected via a memory controller (not shown) included in the memory 2.

The host bus 11B is connected to a PCI bus 14 via a host-PCI bus bridge (not shown) included in the chipset 12. The PCI bus 14 is connected to a programmable logic circuit 16 via a programmable logic circuit interface 15, a hard disk drive 18 via a hard disk interface 17, and a communication interface 19.

The communication interface 19 is connected via a network 20 such as a LAN or the Internet to a storage device 21 in which circuit information reconfigured in the programmable logic circuit 16 is stored.

The hard disk read and written by the hard disk drive 18 stores application programs. The application program may be stored in a storage device (server) on the network 20 in some cases.

The hard disk of the hard disk drive 18 may store circuit information reconfigured in the programmable logic circuit 16. In the case of this example, the hard disk read / written by the hard disk drive 18 forms a storage device in the information processing system 10.

In this embodiment, the hardware acquisition means 3
00 and the execution module determination means 600 are implemented as software as one function of the OS of the information processing system 10 shown in FIG.

Next, the structure of the programmable logic circuit 16 is shown in FIG. As shown in FIG. 5, the programmable logic circuit 16 includes a configuration memory 160 for storing circuit information, a logic cell 161, a wiring area 162, and an input / output terminal 163.

The configuration memory 160
SRAM in the logic cell 161 and the wiring region 162,
It is composed of a rewritable memory element such as a DRAM. When the address ADR is given to the configuration memory 160 and the data DA of the new circuit information is stored, the circuit configuration in the logic cell 161 and the logic cell 161 and the input / output terminal 163 are determined according to the circuit information.
Are reconfigured in the connection state of the wiring region 162 that connects the two. This series of operations is called a configuration. By rewriting a part of the configuration memory 160, the circuit can be partially reconfigured even when the programmable logic circuit is operating.

As shown in FIG. 5, data to be processed is input to a circuit element 164 formed by being reconfigured in the programmable logic circuit 16, and the processing result is output.

[Explanation of Processing According to First Embodiment] FIG. 6 is a flowchart showing a basic processing flow in the first embodiment of the present invention. As described above, in this embodiment, the hardware acquisition unit and the execution module determination unit are implemented as software as one function of the OS of the information processing system 10 in FIG. Thus, the processing is executed by the OS.

In the example described below, it is assumed that the selection condition setting means 700 of FIG. 1 is not provided, but is included in the execution module determination means 600. In the first embodiment, the hardware processing by the programmable logic circuit whose configuration has been completed can generally be performed at a higher speed than the corresponding software processing. It is determined whether or not the reconfiguration of the hardware module corresponding to the processing module to be executed into the programmable logic circuit 16 has been completed. When the reconfiguration has been completed, the processing is performed by the programmable module reconfigured by the hardware module. Executing in a logic circuit "is set.

Prior to execution of the application program 100, first, as shown in FIG.
The identification code ID of the hardware module HM described in the header section HED in the inside is read, and the hardware module H configured on the programmable logic circuit 16 is read.
M is recognized by the hardware module acquisition means 300 (step S11).

Next, two routines are executed in parallel. One is hardware module acquisition means 300
The other is the execution of the configuration of the programmable logic circuit 16 by the execution module determination means 600, and the determination of the software module SM or the hardware module HM for each processing module and the execution of the processing module by the program by the execution module determination means 600 It is.

Hardware module acquisition means 300
Is the first identification code I of the previously read identification code ID.
The circuit information of the hardware module HM corresponding to D is transferred from the storage device 18 in the information processing system 10 or the storage device 21 on the network 20 to the configuration memory 160 of the programmable logic circuit 16 to execute the configuration. Then, in response to the inquiry from the execution module determining means 600, the success or failure of the configuration is answered (step S12).

When the configuration of the first hardware module HM is completed, the hardware module obtaining means 300 determines whether or not there is a next hardware module HM (step S13). If there is, step S1
2, the circuit information of the hardware module HM corresponding to the identification code ID is stored in the storage device 18 in the information processing system 10 or the storage device 2 on the network 20.
1 to the configuration memory 160 of the programmable logic circuit 16 to execute the configuration.

Hardware module acquisition means 300
Executes the above-described processing for all the hardware modules HM of the identification code ID read earlier to perform the configuration.

The execution module determination means 600 inquires of the hardware module acquisition means 300 whether or not the configuration of the hardware module HM corresponding to the processing module to be executed is completed (step S14). If the configuration of the corresponding hardware module HM is completed, the processing by the hardware module HM is performed (step S15), and if the configuration is not completed, the corresponding software module S
The processing by M is performed (step S16).

When the processing of the processing module is completed, it is determined whether there is a next processing module (step S17). If there is a next processing module, the process returns to step S15. Then, the processing by this application ends.

Here, communication between the hardware module acquisition means 300 and the execution module determination means 600 is performed in the system 10 of FIG.
Specifically, this is performed as follows.

That is, when the hardware module HM is configured on the programmable logic circuit 16, it is detected by the OS running on the CPU 11 via the PCI bus 14, and the hardware functioning as a part of the OS The module acquisition unit 300 notifies the execution module determination unit 600.

Also, the processing status of the program is
Transfer of the circuit information of the hardware module HM and the start of the configuration from the execution module determining unit 600 functioning as a part of the OS to the hardware module obtaining unit 300 Or interruption is instructed.

As described above, in this embodiment,
When the processing module is executed, if the corresponding hardware module HM is reconfigured in the programmable logic circuit 16, the processing of the processing module is executed by the hardware module.

As described above, generally, unless processing time for configuration into a programmable logic circuit is taken into consideration, processing by hardware enables higher-speed processing. Therefore, as described above, a series of processing by the application program can be performed at high speed by executing the processing by the hardware module in which the configuration is completed from the time when the configuration is completed.

[Example of Specific Example of Processing (First Example)] Next, a specific example of the processing of the first embodiment will be described with reference to the flowcharts of FIGS. 7, 8 and 9. One embodiment will be described below.

FIG. 7 is a circuit diagram of the first embodiment shown in FIG.
5 is a flowchart showing the entire detailed processing flow corresponding to the flowchart of FIG. FIG. 8 shows a detailed flowchart of step S22 of the configuration routine of the hardware module HM in FIG. FIG. 9 is a detailed flowchart of step S32 of the processing routine by the software module SM or the hardware module HM in FIG.

In FIG. 7, the software module S
The processing by the M or the hardware module HM and the configuration of the hardware module HM are executed in parallel.

Here, in the first embodiment, the software module SM or the hardware module HM
Are performed, and a series of processes including these M types of processing modules is repeated N times.

As shown in FIG. 7, prior to the execution of the application program, the identification code of the hardware module is read from the header of the application program (step S11). Thereafter, a routine R20 for performing configuration of the hardware module HM and a routine R30 for performing processing by the software module SM or the hardware module HM.
Are executed in parallel.

In the routine R20, first, a variable i indicating how many hardware modules HM of the M types of hardware modules have been configured is initialized (step S20), and then the hardware module HM is initialized. The process proceeds to step S22 for executing the configuration processing routine R40.

In the configuration processing routine R40 in step S22, as shown in FIG. 8, it is confirmed whether or not the i-th hardware module HM exists on the programmable logic circuit 16 (step S41). If there is, it notifies the OS that it has already been configured (step S43). The i-th hardware module HM is a programmable logic circuit 16
If not, the configuration in step S42 is performed.

In the configuration of step S42, first, it is confirmed whether the circuit information of the hardware module HM exists in the storage device in the information processing system 10, and if it exists, the storage device in the information processing system 10 is checked. From the storage device 21 on the network 20, and performs configuration.

Then, when the configuration of the hardware module HM is completed, the process proceeds to step S43, where the end of the configuration is notified to the OS, and returning to FIG. 7, the variable i is counted up (step S23).

If the processing corresponding to the hardware module HM is started before the configuration of the hardware module HM is completed, the software module SM or the hardware module H
In the routine R30 for performing processing by M, processing by the software module SM is performed, but the configuration of the hardware module HM is continued.

Then, during the configuration of all the M types of hardware modules HM,
It is determined that the variable j that counts the number of the series of repetitive processes executed by the application program 100 satisfies j> N (step S24), and when the application ends, the M types of hardware modules HM Some are not configured.

However, if the storage device in the information processing system 10 has room, the storage device 21 on the network 20
It is also possible to continue obtaining the circuit information from.
By doing so, when the same type of application is subsequently executed, the acquisition of the circuit information from the network 20 has been completed, and the access time can be reduced accordingly. Further, even if a failure occurs in the network 20 and the necessary hardware module HM cannot be acquired later when the acquisition is performed from the network 20, the influence thereof is minimized.

Next, the variable i and the variable M are compared in order to confirm whether or not the hardware module HM to be configured remains (step S25).
If the variable i is equal to or smaller than the variable M, the configuration of the next hardware module HM is started, and if the variable i is larger than the variable M, all the hardware modules HM are configured on the programmable logic circuit 16. Then, the configuration processing of FIG. 8 ends.

Next, in FIG. 7, in a routine R30 executed in parallel with the routine 20, first, a variable j for counting the number of series of repetitive processes is initialized (step S31), and thereafter, the software module SM Alternatively, the process proceeds to step S32 of the routine R50 for executing the processing by the hardware module HM.

In the routine R50 of step S32, as shown in FIG. 9, first, a variable k for counting the number of processing modules of the M types of processing modules is initialized (step S32). S51).

Next, the k-th hardware module H
In order to confirm whether or not M is configured on the programmable logic circuit 16, in this routine R50, a variable i indicating the order of the configuration of the M types of hardware modules HM has been completed, The processing module that is to execute the processing compares the number of the M types of processing modules with the variable k (step S52).

If the variable k is smaller than the variable i, it is known that the configuration of the hardware module HM corresponding to the k-th processing module has been completed on the programmable logic circuit 16, so that the processing is performed by the hardware module HM. Execute (Step S53).

If the variable k is equal to or larger than the variable i, the hardware module HM corresponding to the k-th processing module has not been configured on the programmable logic circuit 16 yet. The process is executed by the SM (step S54).

Next, a variable k indicating the order of the processing module is counted up (step S55).
For the next (k + 1) th processing module, the previous k
The steps from step S52 to step S55 are executed in the same manner as the
The above-described processing steps are repeated up to the processing module (step S56). When the process for the last M-th processing module is completed, the process returns to the routine of FIG.

In FIG. 7, the variable j of the repetition is counted up (step S33), and the next repetition processing is started. When the repetition processing is performed N times, the application ends (step S34).

As described above, in the first embodiment, in the application program for performing the N repetitions of the M kinds of processing modules, the processing by the software module SM is first executed.
During the repetitive processing, M kinds of hardware modules H
The configuration of M is gradually completed, and the completed hardware modules HM are sequentially used. Therefore, as the number of repetitions of the repetition processing increases, the number of hardware modules HM for which the configuration is completed also increases, the processing speed gradually increases, and the overall processing time is shortened.

[Another Example of Processing of First Embodiment (Second Example)] Next, a more detailed example in which the first embodiment of the present invention is applied to image processing ( The second embodiment will be described. In this second embodiment,
3 of linear transformation processing, noise removal processing and contour enhancement processing
By performing three types of processing on image data using three types of image filters as described below,
Image processing for sharpening an unclear image is performed.
First, each image filter will be described.

[Description of Example of Filter for Noise Removal Processing]
The spatial filter processing, which is one of the image processing, performs an operation on a single or a plurality of pixels of an image file composed of unit pixels. This corresponds to a certain pixel (data x _{l, m} )
Pixels (data p _{l, m} ) in the vicinity of the mask data filter
_{As a} process of obtaining a pixel value x _{l, m} after processing by multiplying by _{l, m} and multiplying by a coefficient N, the following equation (1) can be used. Here, the mask data filter
By changing the values of _{l, m} and the coefficient N, the spatial filter can execute various processes.

[0146]

(Equation 1)

FIG. 10 shows an example of mask data of an image filter called a Gaussian filter which performs a smoothing process of a Gaussian distribution on an image to remove noise. The data x _{l, m} of the center pixel and the data p _{l, m} of 8 pixels in 3 × 3 pixels in the vicinity thereof are added with the coefficient filter mask data.
The data is multiplied by _{l and m} , added together, multiplied by a coefficient N (= 1/16), and replaced with the data of the central pixel. By performing this filter processing, image noise can be removed.

FIG. 11 shows a software module SmABC for realizing the Gaussian filter processing of FIG.
001 program. FIG.
Shows a circuit of a hardware module HmABC001 realizing the Gaussian filter processing of FIG.

As described above, in this case, a given processing module has a pair of a software module and a hardware module having the same input / output specifications. Each module has a unique identification code. For example, if the Gaussian filter processing is provided with a code for identifying the processing “ABC001”, the software module SM includes:
A prefix Sm indicating that the module is a software module is attached, an identification code SmBC001 is assigned, and a prefix Hm indicating that the module is a hardware module is assigned to the hardware module HM.
An identification code of 1 will be given.

The software module SM is, for example, C
/ C ++ is a compilation of a source program written in a language such as
Is circuit information that configures the circuit configuration shown in FIG. 12 on the programmable logic circuit 16, for example.

FIG. 11 shows an example of a C program serving as a software module of the Gaussian filter. For the original image data p [l] [m] to be operated on, for
FIG. 10 shows a double loop configuration using statements in advance.
After multiplying and accumulating the array filter [l] [m] to which the filter coefficients shown in (1) are substituted, and shifting down by 4 bits by a bit shift operator, 1/16 operation is realized.

FIG. 12 shows an example of a circuit configuration of a corresponding Gaussian filter using hardware. Three pixels of p [l-1] [m-1], p [l] [m-1], p [l + 1] [m-1] in the mask area to be filtered from the original image file The minute data is transferred to the hardware module HM as one data. For example, in the case of 8-bit data per pixel, three data are combined and transferred as 24-bit data.

The transferred data is input to IN of the hardware module, and is transferred to the register 10 at the first clock.
1, 102 and 103 are input. The combined data is separated here as outputs D1, D2, D3, and these outputs D1, D2, D3 are stored in registers 111, 1 respectively.
12, 113 and adders 211, 212, 213.

Then, at the next clock, p [l-1] [m], p
Data for three pixels [l] [m] and p [l + 1] [m] similarly appear at outputs D1, D2, and D3. At this point, adder 2
Outputs A1, A2, and A3 of 11, 212, and 213 are A1 = p [l-1] [m-1] + p [l-1] [m] A2 = p [l] [m-1] + p [l] [m] A3 = p [l + 1] [m-1] + p [l + 1] [m]

The outputs of the adders 211, 212, and 213 are simultaneously input to the registers 121, 122, and 123 and the adders 221, 222, and 223.

Then, at the next clock, p [l-1] [m +
1], p [l] [m + 1] and p [l + 1] [m + 1]
Similarly, it appears at outputs D1, D2, and D3.

At this time, the adders 211, 212, 213
The outputs of A1, A2, and A3 are A1 = p [l-1] [m] + p [l-1] [m + 1] A2 = p [l] [m] + p [l] [m + 1] A3 = p [l + 1] [m] + p [l + 1] [m + 1], and the outputs A of the adders 221, 222 and 223
A4 = p [l-1] [m-1] + p [l-1] [m] × 2 + p [l-1] [m + 1] A5 = p [l] [ m-1] + p [l] [m] × 2 + p [l] [m + 1] A6 = p [l + 1] [m-1] + p [l + 1] [m] × 2 + p [l + 1] [m + 1].

Here, the registers 101, 102, 10
3,111,112,113,121,122,133
Is stopped, and the shift register 30 is stopped.
1, the output A5 of the adder 222 is doubled by shifting one bit higher, and the shift register 301
Is output A7.

Next, the outputs A4 and A6 of the adders 221 and 223 and the output A7 of the shift register 301 are summed by the adders 231 and 232, and the shift register 30
2 to lower 4 bits, 1/1
6 is performed. With the above, G in the unit mask area
The aussian filter processing ends. Thereafter, by repeating this processing, processing of the entire image is performed.

As described above, in this embodiment, Bi-n
Gaussi by the ominal filter circuit configuration
Although an filter is realized, various other algorithms can be considered.

[Description of Example of Filter for Contour Enhancement Processing]
FIG. 13 shows Lapla detecting an edge by the second derivative.
This is mask data obtained by adding an original image to an image filter called a cyan filter. By performing this filter processing, the outline of the image can be enhanced.

FIG. 14 shows a software module SmXY for realizing the Laplacian filter processing of FIG.
This shows a program example of Z001. FIG.
Reference numeral 5 denotes a circuit example of a hardware module HmXYZ001 for realizing the Laplacian filter processing of FIG.

FIG. 14 is an example of a C program having an algorithm similar to that of FIG. 13, in which an array filter [l] [m] in which filter coefficients are substituted is replaced with coefficients of an edge emphasis filter shown in FIG. It is.

FIG. 15 is a block diagram of Lapla by hardware.
It is an example of a circuit configuration of a cian filter. First, as a data stream, for example, p [l] [m], p [l-1] [m], p [l] [m-1],
p [l] [m + 1] and p [l + 1] [m] are configured and input to the input terminal IN of the hardware module in time series.

When the data stream is input by four clocks, the image data p [l] [m] and p [l-1]
[m], p [l] [m-1], p [l] [m + 1], p [l + 1] [m] are output terminals 34, 3 of registers 44, 43, 42, 41, respectively.
3, 32, 31 and input terminal IN. Then, at this time, by the operations of the adders 45, 46 and 47, p [l-1] [m] + p [l] [m-1] + p [l] [m +1] + p [l + 1] [m] is output.

On the other hand, the shift register 50 shifts the input data to the left by 2 bits, so that 4 × p [l] [m] is output to the output terminal 37 of the shift register 50.

The data at the output terminal 37 of the shift register 50 and the output terminal 3 of the adder 47 are output from the subtractor 48.
The subtraction with the data of No. 8 is performed, and the output terminal 39 of the subtractor 48 receives 4 × p [l] [m] − (p [l−1] [m] + p [l] [m−1] + P [l] [m + 1]
+ P [l + 1] [m]), and the output terminal 39
The output data p [l] [m] of the output terminal 34 of the register 44 is added to the output data of
Obtained in T.

[Description of Example of Filter for Linear Conversion Processing]
FIG. 16 shows an example of a program of a software module SmPQR001 that realizes a filter for performing a linear transformation of a single pixel of an image, and FIG. 17 shows an example of a circuit of the hardware module HmPQR001. By performing this filtering process, the density distribution of the image can be linearly converted to correct the contrast and the like.

The example of FIG. 16 is an example of a software module in which a filter for performing a linear conversion of a single pixel of an image is described in C language, and uses a linear conversion represented by the following equation (2).

X (l, m) = a × p (l, m) + b Equation (2) FIG. 17 shows an example of a circuit for realizing this linear conversion.
In this example, the linear transformation is a lookup table (LU
T) method is used. That is, for the input data IN, a value OUT corresponding to the equation (2) is output with reference to the table 55.

The table 55 can be realized by setting table data in a memory circuit such as an SRAM or a ROM in advance. Also, a table can be realized by creating a truth table of input and output according to equation (2) and configuring a circuit with basic logic gates such as an AND gate, an OR gate, and an exclusive OR gate. .

In the linear conversion operation, pixel data p [l] [m] are sequentially transferred from the original image data to the hardware module as input data IN, and output data OUT corresponding to the input data is stored in table 55. And output.

[Description of Second Embodiment of Specific Example of Processing] In the second embodiment, the above-described three image filters are successively processed to increase the image contrast and remove noise. This realizes an image processing application capable of enhancing an outline and sharpening an unclear image.

The structure of the application program AP will be described with reference to FIG. Software module SM used in this application program AP
And a list of identification codes ID for associating with the hardware module HM are added to the header part HED of the application program AP.

In the program AP, the hardware module SM and the software module HM are called as duplicated processing.

The processing module used is ABC00
1, XYZ001, and PQR001.
The header part HED includes identification codes HmABC001, Hm of the hardware module HM corresponding to these processes.
XYZ001 and HmPQR001 are described.

The software module SM and the hardware module HM have the same argument and return value and are completely compatible with each other, so that the application program AP can see the same processing module.

Next, the operation of this image processing is shown in the flowchart of FIG. 19 and the continuation of FIG.
The flowcharts of FIGS. 19 and 20 correspond to the processing operations described with reference to FIGS. 7 to 9, and corresponding steps are denoted by the same step numbers.

FIG. 21 is a timing chart of this image processing operation. Using the flowcharts of FIGS. 19 and 20 and the timing chart of FIG. 21,
The image processing operation of the second embodiment will be described below. In FIG. 21, the process a shows the linear transformation PQR001, the process b shows the noise removal process ABC001 using the Gaussian filter, and the process c shows the contour enhancement process XYZ001 using the Laplacian filter.

The number of processing modules used in FIG. 7 to FIG. 9 is three since there are three types of processing modules to be used: linear conversion PQR001, noise removal processing ABC001, and contour enhancement processing XYZ001. Further, since the processes a to c are repeatedly executed for each plane of R (red data), G (green data), and B (blue data) of the image, the number of repetitions N in FIGS. It becomes 3.

In FIG. 21, when the application program is started at time t0, initialization processing of the program AP and preparation of a processed image are performed. At the same time, the process of reading the identification code ID in the header portion HED of the application program AP, obtaining the circuit information of the hardware module HM described therein, and configuring the programmable logic circuit on the
Start from t1.

In FIG. 19, j for counting the number of repetitions is initialized to j = 1 (step S31),
Processing for the R plane of the image is started. Next, a variable k indicating the module data to be processed is initialized to k = 1 (step S51).

In FIG. 21, processing a (PQR001)
At the time point t2 immediately before the execution of, the OS is inquired of the completion of the configuration (step S52). If not completed (k ≧ i), application program A
P executes a process using the software module SmPQR001 (step S53).

Thereafter, the time t immediately before the processing b and the processing c
At 4 and t6, a similar inquiry is made to the OS. However, in this example, as shown in the timing chart of FIG. 21, the corresponding hardware module HmABC00
1, the configuration of HmXYZ001 is not completed, and the software module Sm
The process is executed using ABC001 and SmXYZ001, and the first iteration of the process is completed.

On the other hand, as shown in FIG. 21, when the hardware module HmPQR001 of the process a is configured on the programmable logic circuit 16,
S is notified of the completion of the configuration at time t8 (step S43).

After the first iteration of the above-described repetition processing is completed, a second iteration of the repetition processing for processing the G plane of the image is started (j = 2), and the program proceeds again to time t9 immediately before the processing a. Again, the system inquires of the OS about the completion of the configuration (step S52). When there is a response that the configuration is completed (k <i),
This time, the processing data is transferred to the hardware module HmPQ
After passing it to R001 and processing by hardware, at time t11
Then, only the result is returned to the program (step S53).

At time t12 immediately before the process b, an inquiry is made to the OS (step S52).
As shown in FIG. 21, since the configuration of the corresponding hardware module HmABC001 is not completed, the software module SmABC001
Is performed (step S53).

However, when an inquiry is made to the OS at time t16 immediately before the process c, in this example, as shown in FIG. 21, the corresponding hardware module HmXYZ00
Since the configuration of No. 1 has been completed, the hardware module HmXYZ001 performs processing (step S53), and the second iteration of the processing is completed.

After the second repetition processing is completed, the third repetition processing for processing the B plane of the image starts (j = 3). At this time, the time t18 immediately before each process
, T20, t22, when the configuration is queried from the OS, the corresponding hardware module HmPQ
Since all of R001, HmBC001, and HmXYZ001 are configured on the programmable logic circuit 16, the processes a, b, and c are all performed by the hardware modules HmPQR001 and HmBC00.
At 1, HmXYZ001, the process is executed, the third iteration of the process ends, and the application ends.

As described above, also in the second example of the first embodiment, the configuration of the hardware module into the programmable logic circuit 16 is performed in parallel while executing the processing by the software module. After the configuration is completed, hardware processing is performed by the programmable logic circuit 16, so that the software processing and the hardware processing are efficiently performed without considering the configuration time. As a result, the processing time as a whole can be reduced.

[Second Embodiment] Next, the configuration of an information processing system according to a second embodiment of the present invention will be described with reference to FIG.
Shown in

In the second embodiment, the identification code of the hardware module HM acquired by the hardware module acquisition means 300 and configured in the programmable logic circuit 400 is recorded in the identification code recording means 800. However, this is different from the first embodiment. Other components are the same as in the first embodiment.

In the case of this embodiment, the identification code recording means 800 is obtained from the storage device in the information processing system or the storage device 21 on the network 20 by the hardware module obtaining means 300 and is stored in the programmable logic circuit 400. The identification code ID of the reconfigured hardware module HM is recorded in the reconfiguration order. Therefore, the use history of the hardware module HM is recorded in the identification code recording device 800.

The hardware configuration of the second embodiment is based on the information processing for realizing the first embodiment shown in FIG. 3 by configuring the identification code recording means 800 as described below. It can be realized with the same hardware configuration as the system 10.

That is, the configuration of the hardware module HM is completed, and step S4 in FIG.
As shown in FIG.
Is notified to the system 1, the identification code of the hardware module HM for which configuration has been completed is
The identification code recording unit 800 is realized by recording the data in a hard disk or the main memory 13 using a storage device in the storage unit 0, for example, the hard disk drive 18 in FIG.

[Example of Specific Example of Processing (Third Example)] Next, a first example (hereinafter, referred to as a third example) of the second embodiment will be described with reference to FIG. This will be described with reference to a flowchart.

The third embodiment is an example of a process in which a paper document is read by a scanner and converted into an electronic document. A paper document is composed of a character portion described by characters and an image portion of a figure or a photograph.

As shown in FIG. 23, first, a paper document is read using a scanner at a resolution and the number of gradations necessary for reading an image portion, and is stored as image data (step S61). Next, the read image data is separated into a character portion and an image portion by using a known character image separation processing technique (step S62).

The image data of the separated character portion is subjected to edge emphasis preprocessing by a first application using a Laplacian filter (step S63).
Recognition is performed using a known character recognition technique (step S6).
4) Convert the data into character data represented by a character code (step S65).

The contrast of the image data of the image portion is adjusted by the second application by the linear conversion processing described in the second embodiment (step S6).
6) The noise is removed by the Gaussian filter described in the second embodiment (step S67), and the edge is enhanced by the Laplacian filter described in the second embodiment (step S68). Conversion to suitable image data (step S6
9).

Finally, the character data of the character portion and the image data of the image portion are edited into a desired layout using, for example, commercially available electronic document editing software (step S7).
0), the electronic document is completed.

The first application and the second application are both identification codes of the hardware module HM which performs the same processing as the software module SM constituting the application, similarly to the application shown in the second embodiment. The ID is stored in the header section HED of the application.

That is, the first application is L
The identification code HmXYZ001 of the hardware module of the aplacian filter is included in the header part HED, and the second application is Gaussia.
Identification code HmA of hardware module of n filter
BC001 and the identification code HmPQR001 of the hardware module for linear conversion are included in the header part HED.

[0204] The hardware module acquisition means 300 of the second embodiment transmits the hardware module HM from the first application and the second application in the same procedure as the procedure described in the first embodiment. The hardware module HM to be configured is recognized by reading the identification code ID.

For example, when the first application is executed in the order of the second application, when the first application is executed, the hardware module HmXYZ001 executes the operation of the programmable logic circuit 400.
The identification code HmXYZ001 is recorded in the identification code recording means 800.

Then, when the second application is executed, the hardware module obtaining means 300
Are three kinds of hardware modules HmPQR001,
It is necessary to acquire and configure HmABC001 and HmXYZ001. However, the hardware module acquisition unit 300 refers to the identification code recording unit 800, and the hardware module HmXY001 is acquired.
It can be seen that Z001 is already configured on the programmable logic circuit.

Therefore, when executing the second application, the hardware module acquisition means 300 does not configure the hardware module HmXYZ001 in an overlapping manner. But,
Since the hardware module HmXYZ001 is already configured on the programmable logic circuit 400, Laplac can be used without going through the hardware module configuration procedure described in the first and second embodiments.
HmXYZ0 software module for ian filter
01 can be replaced with a hardware module for processing.

[Example of Specific Example of Processing (Fourth Example)] Next, another example (hereinafter, referred to as a fourth example) of the second embodiment of the present invention will be described.

The first application for performing character recognition from image data and the second application for converting image data into an image suitable for display display, as described in the third embodiment.
These applications are independent processes, and can therefore process different image data. This fourth embodiment is similar to the first and second embodiments, respectively.
Is a case where different applications process different image data.

In the fourth embodiment, when the first application and the second application are executed successively, the hardware module HmXY commonly used is referred to by referring to the identification code recording means 800.
It can be seen that Z001 is already configured on the programmable logic circuit after executing one application. Therefore, when the other application is executed, the configuration of the hardware module shown in the first and second embodiments is not performed, and
The software module of the aplacian filter is replaced with a hardware module HmXYZ001 for processing.

In the fourth embodiment, when one of the applications is executed, the operation of the information processing system is stopped, and the operation of the system is resumed later to execute the other application. By doing so, the configuration of the hardware module can be performed efficiently.

That is, when the system is restarted and before the processing of the other application is started, the hardware module HM corresponding to the recorded identification code is referred to the identification code recording means 800 and the programmable logic circuit 16 Configure above.

Thus, when the processing of the other application is started, the hardware module Hm that is already used in common with the previously processed application
XYZ001 is configured on the programmable logic circuit 400.

Therefore, without going through the hardware module configuration procedure shown in the first and second embodiments, L
hardware module HmXYZ0 that uses the software module of the aplacian filter in common
01 and can be processed.

[Third Embodiment] In the first and second embodiments described above, whether each processing module is performed by the software module SM or the hardware module HM is determined when the application program is executed. Although the determination is made, as described above, it may be performed before the execution of the application program.

In the third embodiment, the execution module is determined by the execution module determining means 600 before the execution of the application program. Information processing system 6 in the case of the third embodiment
FIG. 24 shows an example of the hardware configuration of the "0".

The information processing system 60 according to the third embodiment uses the LCD bus and the CR
The display 61 made of T is a display interface.
The key operation unit 63 is connected through a key interface 64 while being connected through the face 62. Others are the same as the information processing system of FIG.

[Example of Specific Example of Processing (Fifth Example)] An example (hereinafter, referred to as a fifth example) of the third embodiment is the same as the above-described image processing application program. An example in which the execution module is determined before executing the program when performing contrast adjustment, noise removal, and contour enhancement on image data will be described.

In the case of the fifth embodiment, the identification code of each software module SM and the hardware module H
The identification code of M is described correspondingly, and information on the capability of each module, for example, the time required for each process, the memory usage of the software module, the use of the programmable logic circuit cell of the hardware module The amount is described.

[0220] The information processing system 60 according to this embodiment executes the header H before executing the application program.
Obtain ED information. Then, information on the capabilities of the software module SM and the hardware module HM is displayed on the screen 6 of the display 61.
Display in 1D.

FIG. 25 shows a display 61 of the information processing system 60 which is displayed before executing the above-described image processing.
It is an example of the screen 61D. That is, in this embodiment, the software module S
The processing time, the memory usage of the software module, and the usage of the programmable logic circuit cell of the hardware module, which are described corresponding to the respective identification codes of M and the hardware module HM, are displayed in a table format.

The user can determine the expected processing time, the amount of memory provided in the information processing apparatus, and the programmable logic circuit 16.
The key operation unit 63 is used to specify which module performs each processing module in consideration of the number of cells included in the processing module.

In the display example of FIG. 25, contrast adjustment and contour enhancement are processed by a hardware module having a short processing time, and the required number of cells exceeds the number of cells of the programmable logic circuit 16. Noise removal is
It is instructed to process with a software module.

The screen 61D displays, as a result of the instruction, an estimated total processing time of 5602 milliseconds, a maximum used memory amount of 2923 kilobytes, and a total used cell when the processing is executed by the combined processing module. Number 10
It is displayed that there are 84 cells. Therefore, if this is satisfactory, the user instructs the key operation unit 63 to start the program under this condition.

As described above, in the case of the third embodiment, before starting the program, the user can freely determine which of the software module and the hardware module to use for execution of each processing module. Selection can be instructed. Therefore, not only processing speed,
Appropriate processing can be performed in consideration of the memory usage and the like.

[Fourth Embodiment] As described above, the transfer of circuit information to the programmable logic circuit 16 is performed from the storage device 21 on the network or the storage device 18 inside the system. To transfer circuit information,
There are several methods depending on the system configuration.

For example, in parallel with the execution of the application, a method of performing information transfer and configuration while downloading necessary information from the network as needed, or temporarily transferring all information from the network to a storage device such as a hard disk in the system. There is a local transfer method only inside the system, such as reading after downloading, reading at any time in parallel with the execution of the application, and then local bus transfer and configuration.

However, in any case, the reconfiguration of the circuit must be completed before the application executes the circuit. When the transfer time is long, there is a problem that the application waits for execution, resulting in a reduction in processing speed.

As one of the methods for solving this problem,
There is a method disclosed in JP-A-8-76974. The method described in this publication is as follows.

In a data processing device having a programmable logic circuit, when power is turned on, circuit information stored in advance in a read-only memory is downloaded to a configuration memory in the programmable logic circuit. When downloading circuit information from the outside, the circuit information is copied to a predetermined RAM, and then downloaded from the RAM to a configuration memory in the programmable logic circuit.

Further, when circuit information is downloaded from the outside, the circuit information already in the configuration memory in the programmable logic circuit is compared with the new circuit information. This is a so-called caching technique.

However, the conventional method has the following problem.

That is, in the above-described conventional example, circuit information which cannot be resident due to the limitation of the circuit size of the programmable logic circuit although it is used repeatedly is
Reconstruct in a short time using so-called caching.
However, there are inadequacies in the capacity of the RAM, the method of managing the RAM, and the method of managing the type of data, and it cannot be said that efficient configuration can be performed.

The configuration data is temporarily
After being copied to a predetermined RAM, it is not downloaded to the configuration memory and directly transferred from the network to the configuration memory. Therefore, when viewed as a flow of data for transfer, the data passes through a PCI bus which is a common bus of the system, and as a result, the transfer time is long due to the traffic congestion state of the bus and an increase in the number of transfer stages. There is a problem.

When the power is turned on, only one-way transfer to the configuration memory is performed, such as download from a read-only memory or download of a copy once in the RAM. However, there is a problem in that the same information is stored in the configuration memory, and the memory capacity is not efficient.

The fourth embodiment solves the above problem.

FIG. 26 is a block diagram of the fourth embodiment. As can be seen from FIG. 26, in the fourth embodiment, a local memory 900 for temporarily storing the circuit information of the hardware module acquired by the hardware module acquiring means 300 is provided. Others are exactly the same as the case of the second embodiment.

In the fourth embodiment, when configuring the programmable logic circuit 400, the hardware module acquisition means 300 stores the circuit information in the local memory 900. At this time, the identification code recording means 800
Is recorded with an identification code of a hardware module having the circuit information configured and stored in the local memory 900.

Then, the header H in the program 100
When acquiring new hardware according to the identification code of the ED, the identification code of the hardware module to be acquired is stored in the identification code recording means 800 by referring to the identification code of the identification code recording means 800. When the circuit information is not configured in the programmable logic circuit due to the effect of the capacity of the configuration memory or the like, the contents stored in the local memory 900 are checked after the contents stored in the local memory 900 are checked. The configuration of the programmable logic circuit 400 is executed using the circuit information of the wear module.

As a result, data transmission via the PCI bus 14 becomes unnecessary, and the configuration of the circuit information of the hardware module into the programmable logic circuit can be performed at high speed.

That is, for example, in-system storage device 1
8 or from the network 20, the circuit information of the hardware module is temporarily stored in the main memory 1
3, the PCI bus 14 is used for transmitting circuit information for the configuration, but the local memory 900 is used as in the fourth embodiment. When the configuration of the programmable logic circuit 16 is executed based on the circuit information of the hardware module HM stored in the PCI bus 14, the PCI bus 14 does not transmit the circuit information at the time of the configuration. 14 can be used efficiently.

If the circuit information once configured in the programmable logic circuit is overwritten by other circuit information due to a shortage of the capacity of the configuration memory, it should be stored in the local memory 900. And the local memory 90 can be used even when the hardware module needs to be reconfigured into a programmable logic circuit.
0 to the configuration memory of the programmable logic circuit 400 to execute the configuration.

Further, as in the above-described embodiment, for example, prior to execution of an application after execution of two applications in succession, the identification code recording means 80 is executed.
Based on the identification code recorded in 0, the circuit information stored in the local memory 900 can be configured and configured in a programmable logic circuit at high speed.

FIG. 27 shows a hardware configuration example of the information processing system 70 in the case of the fourth embodiment.

This information processing system 70 is an SRAM or DR as a cache local memory for temporarily storing configuration circuit information.
A local memory 71 composed of AM is provided. The local memory 71 can be accessed from the programmable logic circuit 16, and the PCI bus 14 can be accessed via the programmable logic circuit interface 15.
You can also access from.

The circuit information stored in the configuration memory of the programmable logic circuit 16 can be read out by controlling the address, and can be read from the main memory 13 or the storage device via the local memory 71 or the PCI bus 14. Hard disk drive 1
8 can be transferred.

The other configuration of the information processing system 70 is as follows.
It is completely the same as the information processing system 10 of FIG.

The programmable logic circuit 16 and the memory 1
The speed at which circuit information is transferred between the storage device 3 and the storage device 18 varies depending on factors such as the type of device, transfer bus width, bus operating frequency, transfer mode, transfer bus traffic state, and transfer path.

Here, a memory or a storage device having a high transfer rate of circuit information to the programmable logic circuit 16 is called a high rank, and a memory or a storage device with a low transfer rate is called a low rank. In the fourth embodiment, the configuration memory, the local memory 71, and the main memory 1 in the programmable logic circuit 16 are arranged in order from the highest order.
3. Assume that the order is a hard disk drive 18 as a storage device in the system, and a storage device 21 connected via a network.

Next, the basic operation of the fourth embodiment is the same as that of the first embodiment. When an application program is executed, a software module and a hardware module are used as processing modules. The processing is performed while deciding which of the two is to be used as shown in the flowchart of FIG.

[Embodiment of Specific Example of Processing (Sixth Embodiment)] In the sixth embodiment, the local memory 71 is used to improve the efficiency of the configuration. The configuration processing which is the operation of the main part of the sixth embodiment will be described with reference to the flowcharts shown in FIGS. 28, 29 and 30.

As shown in FIG. 28, when acquiring a hardware module, the hardware module acquiring means 300 refers to the identification code recorded in the identification code recording means 800 to store the configuration in the configuration memory. It is checked whether there is circuit information corresponding to the hardware module to be tried (step S71). If there is, the configuration is completed without performing the configuration (step S7).
2). If not, the circuit information of the local memory 71 is confirmed (step S73). Local memory 71
If there is circuit information above, the local memory 71
(Step S74).

FIG. 29 is a flowchart of a configuration routine from the local memory 71. As shown in FIG. 29, it is determined whether there is a sufficient free area in the configuration memory (step S81). If there is enough free space, step S83
Then, the circuit information is transferred from the local memory 71 to the configuration memory of the programmable logic circuit 16, and the configuration is executed as it is. If there is no free area, the process proceeds to step S82 to overwrite the hardware module with a lower priority, and then proceeds to step S83 to perform configuration.

If there is no circuit information in the local memory 71, the circuit information in the main memory 13 is confirmed (step S75). If there is circuit information in the main memory 13,
A process of transferring the circuit information from the main memory 13 to the local memory 71 and the configuration memory of the programmable logic circuit 16 is performed (Step S7).
6).

FIG. 30 shows a flowchart of a routine for the transfer process from the main memory 13.
In transferring data from the main memory 13, first, a vacant area in the configuration memory of the programmable logic circuit 16 is checked (step S91). If the vacant area is not sufficient, the circuit information is overwritten with lower priority circuit information. Determine the area to be overwritten (step S
92), and proceed to the next step S93.

If the free space on the configuration memory is sufficient, steps S91 to S93 are performed.
To confirm a free area on the local memory 71 (step S93). If the free area of the local memory 71 is not sufficient, the process proceeds to step S94 to determine the area to be overwritten in order to perform the transfer by overwriting the circuit information with the lower priority. Then, the next step S9
In 5, the circuit information is transferred from the main memory 13 to the local memory 71, and the configuration of the programmable logic circuit 16 is performed based on the transferred circuit information.

If the free area of the local memory 71 is sufficient, the process jumps from step S93 to step S95 to transfer the circuit information from the main memory 13 to the local memory 71, and to program based on the transferred circuit information. The configuration of the logic circuit 16 is performed.

Returning to FIG. 28, the main memory 1
If there is no circuit information in No. 3, the search is made to a lower-level circuit information storage destination. In this embodiment, the circuit information is stored in the main memory
(Step S77). Also in this case, if there is no free area on the main memory 13, the main memory 13
Overwrite the circuit information with the higher priority.

After the transfer to the main memory 13, the same processing as when circuit information exists in the main memory 13 is performed, and the transfer is performed to the local memory 71 and the configuration memory of the programmable logic circuit 16. As described above, the circuit information is written to the configuration memory of the programmable logic circuit 16 and the local memory 71 that can perform the transfer at the highest speed.
Will also be forwarded.

The transfer and configuration of the programmable logic circuit 16 from the local memory 71 to the configuration memory are different from the transfer and configuration of the main memory 13 by the PC.
Since the data does not pass through the I bus 14, there is no congestion with other data transfer and the configuration can be executed at high speed.

Next, using the local memory 71, 4
FIG. 3 shows a specific example in which one hardware module is configured in the programmable logic circuit 16.
This will be described with reference to FIG.

In the sixth embodiment, a hardware module is stored in, for example, a storage device 20 on a network based on an identification code described in a header HED of a program.
And by using the local memory 71, circuit information is configured in the programmable logic circuit 16 at higher speed.

FIG. 31 shows a processing flow using the four hardware modules A to D. The processing order of the hardware modules is A → B → C → A → D. Since the processing by the hardware module A is performed twice, the priority of the hardware module A is the highest. The hardware modules A, B,
FIG. 32 shows the arrangement of C and D. In this case, since the hardware module A and the hardware module C have an overlap, they cannot be simultaneously configured.

The configuration procedure of these hardware modules A to D will be described with reference to FIG.

At the processing time tc0, the transfer of the hardware module A from the storage device 21 on the network is started, and its circuit information is temporarily stored in the main memory 13. Then, the data is transferred from the main memory 13 to the local memory 71 and the configuration memory of the programmable logic circuit 16 during the processing time tc1 to tc2.

Since the hardware module A has the highest priority, if the memory capacity of the local memory 71 is not sufficient, the hardware modules B, C, and D are not stored in the local memory 71, and these hardware modules are not stored. B, C, and D are lower-level main memories 1
3, or stored in the hard disk drive 18 as an internal storage device. The configuration of the hardware module A is completed in the processing time tc2.

Next, the hardware modules B and C
Are processing times tc1 to tc2 and processing times tc3 to tc4, respectively.
Is started from the storage device 21 on the network 20, and the configuration to the programmable logic circuit 16 is completed in the processing time tc4 and the processing time tc6.

Here, when the processing time tc5 for starting the configuration of the hardware module C is reached, the hardware module C on the programmable logic circuit 16 is constructed by overwriting a part of the hardware module A. Therefore, the programmable logic circuit 1
As the configuration state on 6, the hardware module A becomes invalid, the hardware module B remains valid, and the hardware module C becomes valid from the processing time tc6.

Here, when transferring the hardware module C to the local memory 71, the local memory 71
You need to consider the free space. In the case of this embodiment, since the capacity of the local memory 71 is not enough to store all of the hardware modules A, B, and C, the area of the local memory 71 of the hardware module B is overwritten with the hardware module C. And store it.

This is because the hardware module B has a lower priority than the hardware module A. Therefore, the information of the hardware module C is stored in the local memory 71 from the processing time tc5.

Next, the processing by the hardware module A is performed again. In order to reconfigure the previously invalidated hardware module A,
From the processing time tc7 when the processing of the application program by the hardware module C is completed, the circuit information of the hardware module A stored in the local memory 71 is transferred to the configuration memory of the programmable logic circuit 16.

Therefore, the hardware module C becomes invalid at the time of the processing time tc7, the hardware module A is reconfigured into a programmable logic circuit, and the configuration is completed at the time of the processing time tc8. From the state of storage in the memory, the transfer as indicated by Tra in FIG. 31 has been performed from the local memory 71 in FIG. 31 to the configuration memory of the programmable logic circuit 16.

Finally, the configuration of the hardware module D is performed.

In the above example, the circuit information of the hardware module is temporarily stored in the main memory 13 from the storage device 21 on the network 20 and transferred to the local memory 71 and the configuration memory.
The data may be directly transferred from the network 20 to the main memory 13, the local memory 71, and the configuration memory.

Here, when the capacity of the memory for storing the circuit information is used efficiently, the storage state of the memory is preferably such that the storage state of the main memory 13 does not exist in FIG.

After the processing time tc5 after the data is directly transferred from the network 20 to the local memory 71 and the configuration memory of the programmable logic circuit 16, the hardware module B is replaced by the hardware module C in the local memory 71. And the circuit information remains only in the configuration memory.

If the hardware module B of the configuration memory of the programmable logic circuit 16
A new hardware module is configured in the area of
When overwritten, if there is a plan to use the hardware module B again, the hardware module B is transferred from the configuration memory to the local memory 71 and stored.

Information about the use schedule of the hardware module can be obtained, for example, by analyzing the program in advance. In the case of this embodiment, the identification code I is added to the header part HED of the program.
Since D is described in the order of the processing module, it can also be known by referring to the arrangement of the identification codes ID of the header part HED.

Further, by referring to the identification code recorded in the identification code recording means 800, it can be estimated from the past use history. In this example, from the past use history of the hardware module HM used by the identification code of the identification code recording unit 800, the circuit information of the hardware module HM to be used is obtained from the configuration memory of the programmable logic circuit.
The data is transferred to the local memory 71.

By doing so, the memory capacity related to high-speed transfer between the local memory 71 and the configuration memory of the programmable logic circuit 16 can be used efficiently.

Next, an embodiment in which circuit information of the hardware module HM is communicated between the configuration memory of the programmable logic circuit 16 and the local memory 71 having a capacity larger than that of the configuration memory will be described with reference to FIG. Will be explained.

In the width of the address bus connecting the configuration memory 160 of the programmable logic circuit 16 and the local memory 71, and the width of the data bus,
Since the width of the address bus of the local memory 71 is larger, the lower bits are made to correspond to the address bus width of the configuration memory 160.

By controlling the upper bits of the address bus of the local memory 71, it is possible to configure a memory space divided into a plurality of parts with the same memory capacity as the configuration memory 160 and the same address control.

Although the data bus width is not necessarily required to be the same, the width is, for example, a multiple of a byte unit from the viewpoint of controllability. On the other hand, the information of the identification code ID of the hardware module HM stored in each memory space is recorded in the identification code recording means 800, and the information of the recorded identification code is stored in response to the configuration request. Selectively transferred based on

By performing the configuration and control in this manner, when the configuration is performed in units of the divided memory space, the batch transfer can be performed, so that the transfer control of the hardware module is simplified, and the configuration is further improved. Can be speeded up.

Further, in a configuration using a plurality of hardware modules as shown in FIG. 32, when a hardware module that is used repeatedly by combining a plurality of hardware modules is generated, for example, the hardware module A and the hardware module B are combined. When used, the wiring information for connecting these is also stored in the local memory 71 in association with the memory space divided into a plurality of parts.

The information on the stored hardware modules and wiring information is stored in the identification code recording means 800.
Will be recorded. Therefore, when the configuration becomes necessary, the hardware module (A + B) and the wiring information are not individually and sequentially transferred on the basis of the recorded information, but are collectively or partially stored in the configuration memory. Can be transferred at high speed.

[Fifth Embodiment] In the first, second, third, and fourth embodiments described above, the application programs are
A hardware module, which is composed of a set of software modules and performs the same processing as the software module, is obtained by the identification code of the header part HED of the program, and the execution module is determined before or during execution of the program.

However, according to the present invention, on the contrary, the application program is constituted by a set of hardware modules, and a software module which performs the same processing as the hardware module is replaced by a header part HE of the program.
In the case of acquiring from the storage device in the system or the storage device on the network by the identification code of D, the first embodiment and the second embodiment described above can be obtained simply by replacing the software module with the hardware module. The same processing as in the third and fourth embodiments can be performed.

The reason is that after both modules are obtained, the procedure for determining the execution module is the same.
It is not necessary to acquire again a software module stored in the main memory 13 as a main storage device as a storage unit for the execution program, and the software module is stored in the main storage device before the application is started. Because you can do it.

FIG. 34 is a block diagram showing such a case. FIG. 34 corresponds to the second embodiment. In the case of the configuration corresponding to the first embodiment, the identification information storage unit 800 does not exist.

In this case, the hardware module HM described in the application program 110
Is transferred to the programmable logic circuit 400 to be reconfigured.

Also, the software module acquiring means 330 corresponding to the hardware module acquiring means of the above-described embodiment converts the acquired software module into
Stored in the execution program storage means 550,
To run in This execution program storage means 4
The information processing system 40 includes the main memory 13 as described above.

[Effects of Embodiment] As described above, in the first, second, fourth, and fifth embodiments, at least a part of the processing is performed. In an information processing system processed by a programmable logic circuit whose circuit configuration can be reconfigured, in parallel with the execution of an application program by a software module, by configuring a hardware module that performs the same processing as a software module, The program can be executed with the best combination of the software module and the hardware module in consideration of the reconfiguration time of the program logic circuit, and the highest processing capability of the information processing system can be exhibited.

Therefore, unlike the related art, it is not necessary to fixedly determine in advance the part to be processed by the software module and the hardware module in the application program.

According to the first embodiment, the second embodiment, the third embodiment, and the fourth embodiment, a hardware module is stored in a storage device on a network. Even if the network communication is disconnected during the process, the processing can be continued by the software module without interrupting the processing.

Similarly, according to the fifth embodiment, even if a software module is stored in a storage device on a network and network communication is disconnected during the processing, the processing is interrupted. Instead, the processing can be continued by the hardware module.

In any of the first to fourth embodiments, when executing a plurality of application programs, the hardware module configured in the programmable logic circuit is recorded in the identification code recording means 800. Eliminates redundant configuration of commonly used hardware modules, minimizing the reconfiguration time of programmable logic circuits, and maximizing the processing power of information processing systems Becomes

Similarly, according to the fifth embodiment, when executing a plurality of application programs, the software modules stored in the main memory are recorded in the identification code recording means 800. This eliminates the need to redundantly store software modules that are to be used, minimizes the load time to the main memory, and enables the information processing system to exhibit the highest processing capability.

In the first, second, and fourth embodiments, the identification code recording means 8
Since the hardware module can be configured on the programmable logic circuit before the start of the application program based on the history of use of the hardware module recorded in 00, the hardware module can be configured from the start of the execution of the application program. The information processing system can be used efficiently, and the highest processing capability of the information processing system can be exhibited.

Similarly, in the fifth embodiment, similarly, the software module is stored in the main memory before the start of the application program, based on the history of use of the software module of the identification code recording means 800. Therefore, the CPU can be efficiently used from the start of the execution of the application program, and the highest processing capability of the information processing system can be exhibited.

In the case of the third embodiment, before starting a program, a module to be processed is designated to perform a process according to the state of the information processing apparatus or a user's preference. Can be.

Further, in the case of the fourth embodiment, circuit information of a hardware module can be communicated between a local memory and a configuration memory of a programmable logic circuit. It is sufficient if the circuit information is stored in any of them, and the capacity of the memory capable of high-speed transfer can be used efficiently.

Further, in the case of the fourth embodiment, by having a memory space in which the local memory is divided into a plurality of parts with the same capacity as the configuration memory space,
A plurality of hardware modules including simultaneously configured circuit information and wiring information can be collectively or partially transferred at high speed in units.

Further, since the information processing system according to the present invention can perform either the processing by the software module or the processing by the hardware module as in the fifth embodiment, the program is It can be described as a set of modules or a set of hardware modules.

[0306]

As described above, according to the present invention, in an information processing system in which at least a part of processing is processed by a programmable logic circuit whose circuit configuration can be reconfigured, the processing is executed by software, It is possible to flexibly determine whether to execute processing by hardware using a logic circuit, and, as in the past, in an application program, a processing module is fixedly determined in advance by a software module and a hardware module. No need to do.

Further, the program can be executed by the best combination of the software module and the hardware module in consideration of the reconfiguration time of the program logic circuit, and the highest processing capability of the information processing system can be exhibited. Become.

Also, the configuration of the hardware module and the software module commonly used in the application program is not duplicated, and the reconfiguration time of the programmable logic circuit can be minimized. It is possible to demonstrate the highest processing capacity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conceptual configuration of a first embodiment of an information processing system according to the present invention.

FIG. 2 is a diagram for explaining an example of an application program used in the information processing system according to the present invention.

FIG. 3 is a diagram illustrating a hardware configuration example of a first embodiment of the information processing system according to the present invention;

FIG. 4 is a diagram illustrating an example of a programmable logic circuit.

FIG. 5 is a diagram illustrating an example of a programmable logic circuit.

FIG. 6 is a flowchart for explaining main processing operations of the first embodiment of the information processing system according to the present invention.

FIG. 7 is a flowchart illustrating a specific example (first example) of processing of the first embodiment of the information processing system according to the present invention;

FIG. 8 is a flowchart illustrating a part of the processing routine of FIG. 7;

FIG. 9 is a flowchart illustrating a part of the processing routine of FIG. 7;

FIG. 10 is a diagram for explaining one of processing modules used in a specific example of processing (second example) in the first embodiment of the information processing system according to the present invention;

FIG. 11 is a diagram for explaining one of the software modules used in the second embodiment.

FIG. 12 is a diagram for explaining one of the hardware modules used in the second embodiment.

FIG. 13 is a diagram for explaining one of processing modules used in a specific example of processing (second example) in the first embodiment of the information processing system according to the present invention;

FIG. 14 is a diagram for explaining one of the software modules used in the second embodiment.

FIG. 15 is a diagram for explaining one of the hardware modules used in the second embodiment.

FIG. 16 is a diagram for explaining one of software modules used in the second embodiment.

FIG. 17 is a diagram for explaining one of the hardware modules used in the second embodiment.

FIG. 18 is a diagram for describing an application program used in the second embodiment.

FIG. 19 is a flowchart illustrating the flow of a process according to the second embodiment.

FIG. 20 is a flowchart of a part of the flowchart of FIG. 19;

FIG. 21 is a timing chart illustrating the flow of a process according to the second embodiment.

FIG. 22 is a block diagram showing a conceptual configuration of a second embodiment of the information processing system according to the present invention.

FIG. 23 is a flowchart for explaining a processing flow of a specific example (third example) of processing according to the second embodiment;

FIG. 24 is a diagram illustrating an example of a hardware configuration of an information processing system according to a third embodiment of the present invention;

FIG. 25 is a diagram for explaining a specific example (fifth embodiment) of the processing in the case of the third embodiment of the information processing system according to the present invention;

FIG. 26 is a block diagram showing a conceptual configuration of a fourth embodiment of the information processing system according to the present invention.

FIG. 27 is a diagram illustrating an example of a hardware configuration of an information processing system according to a fourth embodiment of the present invention;

FIG. 28 is a flowchart for explaining a specific example (sixth example) of processing in the case of a fourth embodiment of the information processing system according to the present invention;

FIG. 29 is a flowchart of a part of the processing routine of FIG. 28;

FIG. 30 is a flowchart of a part of the processing routine in FIG. 28;

FIG. 31 is a timing chart for explaining a processing flow of the sixth embodiment.

FIG. 32 is a diagram for explaining the circuit arrangement formed on the programmable logic circuit for explaining the sixth embodiment;

FIG. 33 is a diagram illustrating a main part of hardware for explaining a sixth embodiment;

FIG. 34 is a block diagram showing a conceptual configuration of a fifth embodiment of the information processing system according to the present invention.

FIG. 35 is a diagram illustrating one conventional information processing system.

FIG. 36 is a diagram for explaining another example of the conventional information processing system.

FIG. 37 is a diagram for explaining yet another one of the conventional information processing systems.

[Explanation of symbols]

Reference Signs List 10 information processing system 11 CPU 12 chipset 13 main memory 14 bus 15 programmable logic circuit interface 16 programmable logic circuit 17 hard disk interface 18 hard disk drive 19 communication interface 20 network 21 storage device on network 60 information processing system 61 display 62 display interface 63 Key operation unit 64 Key interface 70 Information processing system 71 Local memory 100 Application program 160 Configuration memory 200 Storage device in information processing system or on network 300 Hardware module acquisition unit 330 Software module acquisition unit 400 Programmable logic circuit 4 0 execution program storage means 500 CPU 600 executing module determination means 700 selecting condition setting unit 800 identification code storage means 900 local memory

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroyuki Miyake 430 Nakai-cho, Nakai-machi, Ashigara-kami, Kanagawa Prefecture Inside Green Tech Nakai Fuji Xerox Co., Ltd. Inside

Claims (35)

[Claims] The present invention executes a series of processes described by a program including a plurality of processing modules each including a software module in which processes are described in a program language, and a part of the series of processes is executed. An information processing system capable of being processed by a programmable logic circuit, wherein a hardware module in which the same processing as that performed by a software module in the program is described by circuit information to be reconfigured in the programmable logic circuit is stored. A storage device unit, a hardware module obtaining unit that obtains the hardware module from the storage device unit and reconfigures the programmable logic circuit, a processing module described in the program, the software module, Run on either of the hardware modules The information processing system characterized in that it comprises, with an execution module determination means for determining prior to execution of the program Luca. 2. A program for executing a series of processes described by a program composed of a plurality of processing modules comprising software modules in which processes are described in a programming language, and a part of the series of processes is described. An information processing system capable of being processed by a programmable logic circuit, wherein a hardware module in which the same processing as that performed by a software module in the program is described by circuit information to be reconfigured in the programmable logic circuit is stored. A storage device unit, a hardware module obtaining unit that obtains the hardware module from the storage device unit and reconfigures the programmable logic circuit, a processing module described in the program, the software module, Run on either of the hardware modules The information processing system characterized in that it comprises, with an execution module determination means for determining during execution of the processing module of the program Luca. 3. A part of processing can be processed by a programmable logic circuit, and is described by a program including a plurality of processing modules including hardware modules in which processing is described by circuit information included in the programmable logic circuit. An information processing system for executing a series of processes performed by the storage device, the storage device storing a software module in which the same process as a hardware module in the program is described in a program language; Software module obtaining means for acquiring the software module from the storage module and storing the software module in the execution program storage unit; and executing the processing module described in the program by either the software module or the hardware module. Before running the program The information processing system comprising: the Mel execution module determining means. 4. A part of the processing can be processed by a programmable logic circuit, and is described by a program including a plurality of processing modules including hardware modules in which processing is described by circuit information included in the programmable logic circuit. An information processing system for executing a series of processes performed by the storage device, the storage device storing a software module in which the same process as a hardware module in the program is described in a program language; Software module obtaining means for acquiring the software module from the storage module and storing the software module in the execution program storage unit; and executing the processing module described in the program by either the software module or the hardware module. The processing of the program The information processing system characterized by comprising an execution module determination means for determining at joule execution. 5. A program for executing a series of processes described by a program composed of a plurality of processing modules each including a software module in which processes are described in a program language, and a part of the series of processes is executed. An information processing system capable of being processed by a programmable logic circuit, wherein a hardware module described by circuit information to be reconfigured in the programmable logic circuit, the same processing as that performed by a software module in the program, is executed via a network. Hardware module acquisition means for acquiring and reconfiguring the programmable logic circuit; and executing the processing module described in the program by the software module or the hardware module. Execution module to decide before execution The information processing system comprising: the Lumpur determining means. 6. A program for executing a series of processes described by a program composed of a plurality of processing modules including software modules in which processes are described in a program language, and a part of the series of processes is executed. An information processing system capable of being processed by a programmable logic circuit, wherein a hardware module described by circuit information to be reconfigured in the programmable logic circuit, the same processing as that performed by a software module in the program, is executed via a network. Hardware module acquisition means for acquiring and reconfiguring the programmable logic circuit; and executing the processing module described in the program by the software module or the hardware module. Of the processing module The information processing system comprising: the execution module determination means for determining at the. 7. A part of the processing can be processed by a programmable logic circuit, and is described by a program configured by a plurality of processing modules including hardware modules in which processing is described by circuit information included in the programmable logic circuit. An information processing system for executing a series of processes performed by a software module described in a program language, which is the same as the process performed by a hardware module in the program, via a network, Software module obtaining means for storing the processing module described in the program, and execution module determining means for determining which of the software module and the hardware module to execute the processing module described in the program before executing the program. It is characterized by having An information processing system to be. 8. A part of the processing can be processed by a programmable logic circuit, and is described by a program including a plurality of processing modules including hardware modules in which processing is described by circuit information included in the programmable logic circuit. An information processing system for executing a series of processes performed by a software module described in a program language, which is the same as the process performed by a hardware module in the program, via a network, A software module obtaining means to be stored in a storage module, and an execution module for determining whether to execute the processing module described in the program by the software module or the hardware module when the processing module of the program is executed Decision means The information processing system comprising: a. 9. The information processing system according to claim 1, wherein the identification code indicating a hardware module that performs the same processing as the processing performed by the software module is a program. Wherein the hardware module obtaining means obtains a hardware module corresponding to the identification code and reconfigures the programmable logic circuit. 10. The information processing system according to claim 3, wherein the identification code indicating a software module that performs the same processing as the processing performed by the hardware module is a program. Wherein the software module obtaining means obtains a software module corresponding to the identification code and stores the software module in the execution program storage unit. 11. The information processing system according to claim 9, further comprising: identification code recording means for recording an identification code of a hardware module reconfigured in said programmable logic circuit; Among the identification codes of the hardware modules described in the program, a hardware module corresponding to an identification code not recorded in the identification code recording means is obtained, and the programmable logic circuit is reconfigured. Information processing system. 12. The information processing system according to claim 10, further comprising: an identification code recording unit that records an identification code of a software module stored in the execution program storage unit; Obtaining a software module corresponding to an identification code not recorded in the identification code recording means among the identification codes of the software modules described in the program, and storing the software module in the execution program storage unit. An information processing system characterized by the following. 13. The information processing system according to claim 9, further comprising: identification code recording means for recording an identification code of a hardware module reconfigured in said programmable logic circuit; An information processing system comprising: acquiring at least one or more hardware modules corresponding to an identification code recorded in an identification code recording unit before executing a program, and reconfiguring the programmable logic circuit. . 14. The information processing system according to claim 10, further comprising: an identification code recording unit that records an identification code of a software module stored in the execution program storage unit; At least one or more software modules corresponding to the identification code recorded in the identification code recording means are obtained before execution of a program, and stored in the execution program storage unit. Processing system. 15. The information processing system according to claim 1, wherein the execution module determining unit refers to a preset execution module selection condition and executes a process described in the program. An information processing system, which determines whether a module is executed by the software module or the hardware module. 16. The information processing system according to claim 2, 4, 6, or 8, wherein the execution module determining unit determines the execution module selection condition as the execution module selection condition when the processing module is executed. It is determined whether or not the reconfiguration of the hardware module of the processing to be performed into the programmable logic circuit has been completed. When the reconfiguration has been completed, the programmable logic reconfigured by the hardware module is executed. An information processing system characterized in that it is determined to be executed by a circuit. 17. The information processing system according to claim 2, wherein the reconfigurable logic circuit is configured by a hardware module in parallel with the execution of the program. At the time of execution of the processing module, it is determined whether or not reconfiguration of the hardware module of the processing to be executed into the programmable logic circuit has been completed, and when the reconfiguration has been completed, the processing is performed by hardware. An information processing system, which is determined to be executed by a programmable logic circuit reconfigured by a module. 18. The information processing system according to claim 2, wherein the identification code indicating the hardware module is described in a program and the programmable logic is An identification code recording unit for recording an identification code of the hardware module reconfigured in a circuit, wherein the execution module selecting unit refers to the identification code recording unit when executing the processing module, and performs the identification. When the identification code of the hardware module of the process to be executed is recorded in the code recording unit, it is determined that the reconfiguration of the hardware module has been completed, and that the process is reconfigured by the hardware module. An information processing system characterized in that it is determined to be executed by a logic circuit. . 19. The information processing system according to claim 1, wherein the identification code indicating a hardware module that performs the same processing as the processing performed by the software module is a program. And an identification code recording means for recording an identification code of a reconfigured hardware module in the programmable logic circuit, and a local memory for temporarily storing circuit information of the hardware module, Provided at a position where data can be directly communicated with the configuration memory of the logic circuit, wherein the hardware module obtaining means obtains the hardware module based on an identification code in the program and sends the hardware module to the programmable logic circuit. To reconfigure and before The information processing system characterized in that for storing circuit information of the hardware module was obtained also transferred to the local memory. 20. The information processing system according to claim 3, wherein an identification code indicating the hardware module is described in a program, and the programmable logic circuit An identification code recording means for recording an identification code of a reconfigured hardware module is provided, and a local memory for temporarily storing circuit information of the hardware module is directly stored in a configuration memory of the programmable logic circuit. The circuit information of the hardware module corresponding to the identification code in the program is obtained from the storage device or a network, and reconfigured into the programmable logic circuit, and the local memory is provided. The feature is that it is also transferred and stored Information processing system. 21. The information processing system according to claim 19, wherein before execution of said program, circuit information of a hardware module of said local memory is referred to by referring to an identification code of said identification code recording means. And reconfiguring circuit information of at least one hardware module existing in the local memory from the local memory into the programmable logic circuit. 22. The information processing system according to claim 19, wherein the circuit information of the hardware module is stored based on a use history of the hardware module recorded in the identification code recording unit. An information processing system wherein data is transferred from a configuration memory of a programmable logic circuit to the local memory and stored. 23. The information processing system according to claim 19, wherein a memory space of the local memory is set in units of a storage capacity equivalent to an entire area of a configuration memory in the programmable logic circuit. Is divided into a plurality of units, and the circuit information of the hardware module is communicated between the configuration memory and the local memory according to the divided memory space unit. Processing system. 24. The information processing system according to claim 19, wherein a functional circuit simultaneously configured in the programmable logic circuit by a plurality of the hardware modules and their wiring information. An information processing system, wherein the circuit information of the hardware module is stored as one piece of circuit information corresponding to an arbitrary memory space of the configuration memory or the divided local memory. 25. The information processing system according to claim 19, further comprising: an identification code recording unit for recording an identification code of the used hardware module, wherein the configuration memory or the division memory is used. An information processing system, wherein information of the hardware module stored in an arbitrary memory space of a specified local memory is recorded in the identification code recording means by the identification code. 26. A program for executing a series of processes described by a program composed of a plurality of processing modules including software modules in which processes are described in a program language, and a part of the series of processes is described. An information processing method capable of being processed by a programmable logic circuit, comprising preparing a hardware module in which the same processing as that performed by a software module in the program is described by circuit information to be reconfigured in the programmable logic circuit. The processing module described in the program may be executed by the software module or the hardware module, based on a preset execution module selection condition. The feature is that it is decided when the program is executed. Information processing method that. 27. The information processing method according to claim 26, wherein said hardware module is obtained through a network. 28. A part of the processing can be processed by a programmable logic circuit, and is described by a program including a plurality of processing modules including hardware modules in which the processing is described by circuit information included in the programmable logic circuit. An information processing method for executing a series of processes performed by a software module in which the same process as that performed by the hardware module in the program is described in a program language, and is described in the program. The execution of the processing module by the software module or the hardware module is determined based on a preset execution module selection condition before or at the time of execution of the program. An information processing method, comprising: 29. The information processing method according to claim 28, wherein said software module is obtained through a network. 30. The information processing method according to claim 26, wherein an identification code indicating the hardware module performing the same processing as the processing performed by the software module is described in the program. An information processing method comprising: obtaining the hardware module corresponding to the identification code; and reconfiguring the programmable logic circuit. 31. The information processing method according to claim 28, wherein an identification code indicating a software module performing the same processing as that performed by the hardware module is described in a program. An information processing method comprising: obtaining a software module corresponding to an identification code; and storing the software module in an execution program storage unit. 32. The information processing method according to claim 30, wherein an identification code indicating the hardware module performing the same processing as the processing performed by the software module is described in the program, and The identification code of the hardware module reconfigured in the logic circuit is stored in the identification code storage unit, and the identification code of the hardware module described in the program is recorded in the identification code storage unit. An information processing method comprising: obtaining the hardware module corresponding to an identification code that is not performed; and reconfiguring the programmable logic circuit. 33. The information processing method according to claim 31, wherein an identification code indicating the software module performing the same processing as that performed by the hardware module is described in the program, and The identification code of the software module stored in the program storage unit is stored in the identification code storage unit, and among the identification codes of the software module described in the program, the identification code is stored in the identification code storage unit. An information processing method comprising: obtaining the software module corresponding to an identification code that is not recorded; and reconfiguring the programmable logic circuit. 34. The information processing method according to claim 30, wherein an identification code of the reconfigured hardware module is recorded in the programmable logic circuit, and at least the identification code corresponding to the recorded identification code is recorded. An information processing method comprising: acquiring one or more hardware modules before executing the program; and reconfiguring the programmable logic circuit. 35. The information processing method according to claim 31, wherein an identification code of the software module stored in the execution program storage unit is recorded in an identification code recording unit, and the identification code recording unit stores the identification code in the identification code recording unit. An information processing method comprising: acquiring at least one or more software modules corresponding to a recorded identification code before executing the program and storing the software module in the execution program storage unit.