JPH11220791A - Sound processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sound processor which is of low-cost and simultaneously reproduces a plurality of channels. SOLUTION: This sound processor is constituted of a single semiconductor element, and has a function to actively and efficiently harks access to the resource of a common bus as the bus master of the common bus and reproduces sound waveform data which is pulse code-modulated and can simultaneously reproduce a plurality of sound channels expressed as a product of M and N by time-divisionally multiplexing and outputting data of N sets (N is the natural number which is not less than 2) of sound channels to M sets (M is natural number) of an in dependent digital analog conversion means 5 converting digital data of the sound channel into analog sound signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is suitable for use in, for example, video game machines, personal computers, electronic musical instruments, communication network information equipment, portable information equipment, communication karaoke equipment, educational toys, learning teaching equipment, and the like. The present invention relates to a pulse code modulation (hereinafter abbreviated as PCM) type sound processor and a sound processor including the sound processor.

[0002]

2. Description of the Related Art Conventionally, in information processing devices such as home video game machines and personal computers and electronic musical instruments,
There are many devices equipped with a sound processing device that generates music and sound effects in accordance with the progress of software and a user's operation.

[0003] Music reproduction by such a sound processing apparatus is performed by controlling a sound source while interpreting in real time score data in which information such as a pitch, a tone, a mute, and a tone effect of a sound to be reproduced is arranged on a time axis. This is done by sequentially setting parameters for performing the operations.

[0004] As one kind of such a sound processing device,
2. Description of the Related Art PCM tone generators which store basic sound waveform data of musical instruments and the like as PCM data, convert the pitches thereof in accordance with a designated pitch and the like, and reproduce the data are widely used.

[0005] For example, Super Famicom (registered trademark)
A PCM sound source device used in a video game machine such as a TV or PlayStation (registered trademark) is connected as a bus slave to a common bus having a central processing unit (hereinafter abbreviated as CPU) as a host as a bus master. ing. In this specification, resources on the side of receiving addresses, such as memories and input / output control devices, are called bus slaves, whereas resources on the side of issuing addresses, such as CPUs, are called bus masters. These PCM tone generators store sound processing programs and the like in their own local ROM (read only memory), and score data, audio waveform data, and echo work areas in a local RAM (random access memory).

A personal computer PCM tone generator such as Sound Blaster 32/64 (registered trademark) is connected as a bus slave to a system bus (PCI bus, ISA bus, etc.) of the personal computer, and provides score data, an audio waveform table, and the like. Is stored in its own local ROM or local RAM.

In such a PCM tone generator, it is necessary for a bus master of a common bus such as a host CPU to transfer various data to a local RAM before reproducing sound.

[0008]

The method used in the PCM tone generator described above requires not only a large-capacity local memory such as a local ROM or a local RAM to store various data, but also a simultaneous memory. There is a problem that the number of instruments that can be played back and the length of PCM data that can be played back in a stream are limited by the capacity of the local memory.

In the above-mentioned specific system, it is possible to rewrite the data in the local RAM during reproduction, but for that purpose, a bus master of a common bus such as a host CPU or a DMA controller must take charge of data transfer. Rather, this degrades the processing performance of the entire system.

Furthermore, the conventional PCM tone generator uses a digital multiplication circuit for multiplying audio data for effects such as an envelope and an echo, and requires a large circuit scale to perform high-speed multiplication. Was to do.

Further, the conventional PCM tone generator performs digital addition for simultaneous reproduction of a plurality of channels, and performs high-precision digital adder and digital-analog conversion for simultaneous reproduction of many channels. Is required, which contributes to an increase in circuit size.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and is not subject to a functional limitation due to the capacity of a local memory, and imposes a processing burden on a host device such as a CPU. It is an object of the present invention to provide a sound processor and a sound processing device which can achieve simultaneous reproduction of multiple channels at a low cost without using.

According to a first aspect of the present invention, there is provided a sound processor which is constituted on a single semiconductor device and reproduces pulse code modulated audio waveform data, comprising a sequence control means, an address bus and a data bus. An address for the common bus is issued through the bus interface means based on control from the bus interface means for the common bus and the sequence control means, and reading and writing of data with respect to resources connected to the common bus are performed. , A data holding means for holding a part of the data read by the bus master means, and M sets (M is a natural number) of independent digital data for converting digital data of an audio channel into an analog audio signal. Analog conversion means, and a digital / analog conversion means. The data of N sets (N is a natural number of 2 or more) of audio channels are time-division multiplexed to data output control means for controlling output of data to be output and digital-to-analog conversion means required for reproduction. And a time-division multiplexing means for outputting data of a plurality of sets of audio channels represented by the product of M and N at the same time.

With the above-described configuration, the sound processor can actively access the resources connected to the common bus. That is, since direct access to the vast address space is possible,
It is possible to take in data without relying on another bus master such as U. Further, the size of the audio waveform data and the data of various parameters is not limited by the capacity of the local memory. Further, since the sound processor does not require a large-capacity local memory, it can be provided at low cost.

Further, by independently providing M sets of digital-to-analog conversion means and performing digital-to-analog conversion of data of N sets of audio channels by time division multiplexing, a plurality of data expressed by the product of M and N can be obtained. Simultaneous reproduction of data of a set of audio channels is realized with a small circuit scale. This makes use of the fact that if the period of the time division multiplexing is sufficiently short, the multiplexed sound sounds as if it were mixed.

According to a second aspect of the present invention, the bus master means includes:
It is determined whether or not the data required for reproduction is stored in the data holding means. If the data required for reproduction is not stored in the data holding means, it is connected to a common bus. The gist of the sound processor further includes a function of acquiring the data from a resource and storing the data in the data holding unit.

Normally, the time required to acquire data from a data holding means such as a local memory is shorter than the time required to acquire data from resources connected to a common bus. , The processing capability of the sound processor can be expected to be improved. Further, since unnecessary access to resources connected to the common bus is reduced,
The other bus masters of the common bus can use the common bus more, and it is expected that the processing capability of the entire system including the sound processor can be improved.

According to a third aspect of the present invention, the digital-to-analog conversion means comprises a plurality of digital-to-analog converters, respectively, and cascade-connects the respective digital-to-analog converters to form an analog multiplication circuit. The gist of the present invention is the sound processor.

The cascade connection here is to connect the output of a voltage output type digital-to-analog converter (hereinafter abbreviated as DAC) as a reference voltage of another DAC. Accordingly, the output voltage of the latter is proportional to the input data of the former and the latter, so that an analog multiplying circuit can be configured.

In a conventional PCM tone generator, volume control, envelope function, and the like are realized by multiplying these parameters and audio waveform data using a digital multiplier. However, a high-speed digital multiplier requires a large circuit scale. In addition, since the conversion to the analog audio signal by the DAC is performed collectively after all the operations are processed by the digital arithmetic unit, a high-precision DA signal is output.
C is required.

The present invention uses a cascaded DAC instead of the digital multiplier and the high-precision DAC, and achieves the same function with a small circuit scale. This is derived as a result of paying attention to the fact that the multiplication performed here is limited to speech processing, so that it is unnecessary to have an accuracy that is audibly distinguishable or higher.

Here, the volume of the entire output audio signal and the volume of each audio channel are called a main volume and a channel volume, respectively, and the function of performing amplitude modulation on the audio waveform to generate various tone effects is called an envelope. In the sound processor that performs these controls, an optimum configuration example for each of monaural sound reproduction and stereo sound reproduction was searched for and derived.

An example of an optimal configuration for reproducing monaural sound is provided with one main volume control DAC, and each of the digital / analog conversion means includes one channel volume control DAC and one envelope control D.
AC, one DAC for audio waveform reproduction, and one DAC for midpoint output of the waveform. The M channel volume control DACs are cascade-connected in parallel to the next stage of the main volume control DAC. One envelope control DAC is cascade-connected to each next stage, and one audio waveform reproduction DAC and one waveform midpoint output DAC are cascade-connected in parallel to each next stage. A first mixing unit that mixes the outputs of the M audio waveform reproduction DACs, and a second mixing unit that mixes the outputs of the M waveform midpoint output DACs. The outputs of the first and second mixing means are respectively connected to two inputs of a differential amplifier provided inside or outside the semiconductor. In addition,
If M is 1, that is, if there is only one set of digital-to-analog conversion means, no particular mixing means is required, and the output of the audio waveform reproduction DAC and the waveform midpoint output DA
It is sufficient that the outputs of C are connected to the differential amplifiers.

An example of an optimum configuration for stereo sound reproduction is provided with one main volume control DAC, and each of the digital / analog conversion means includes one channel volume control DAC and one first envelope. Control DAC, one second envelope control DAC, one DAC for reproducing the first audio waveform, one DAC for reproducing the second audio waveform, one DAC for outputting the middle point of the first waveform, and one DAC for outputting the midpoint of the first waveform. 2
It is composed of a DAC for outputting a waveform middle point. The M channel volume control DACs are cascade-connected in parallel to the next stage of the main volume control DAC, and each first envelope is connected to the next stage thereof. Control DAC
And a second envelope control DAC are cascade-connected in parallel, and a first audio waveform reproduction DAC and a first waveform midpoint output DAC are cascade-connected in parallel at the next stage of each first envelope control DAC. , Each second
At the next stage of the envelope control DAC, one DAC for reproducing the second audio waveform and a DAC for outputting the middle point of the second waveform are cascaded in parallel, and the M DACs for reproducing the first audio waveform are provided.
First mixing means for mixing the outputs of the M first waveform middle point output DACs, and M number of the second audio waveform reproduction DAs.
A third mixing means for mixing outputs of C, and a fourth mixing means for mixing outputs from the M number of DACs for outputting the middle point of the second waveform.
Wherein the outputs of the first and second mixing means are connected to two inputs of a first differential amplifier provided inside or outside the semiconductor, respectively, and the third and fourth mixing means are provided. Are connected to two inputs of a second differential amplifier provided inside or outside the semiconductor device, respectively.

However, the configuration described above can be used not only for stereophonic sound reproduction but also for other uses. Also in this configuration, when M is 1, no mixing means is particularly necessary as described above, and the output of the DAC for reproducing the audio waveform and the output of the DAC for outputting the midpoint of the waveform are respectively connected to the differential amplifier. It should just be.

When an analog multiplying circuit is configured using cascade connection, simply connecting a DAC results in an output waveform whose amplitude is modulated only in the positive direction with a certain voltage value as a lower end. I will. Therefore, in the above two configuration examples, the DAC for waveform midpoint output, which has exactly the same structure and characteristics as the DAC for audio waveform reproduction and always receives the data of the center point of the waveform amplitude, is called the DAC for audio waveform reproduction. By connecting them in parallel and using their outputs as the two inputs of the differential amplifier, the output waveform can be amplitude-modulated in both positive and negative directions with the center of the waveform amplitude as the origin.

According to a fourth aspect of the present invention, when the data output control means outputs data to the digital-to-analog conversion means, the data output control means sets a silent state for a predetermined period between adjacent time-division multiplexed audio channels. The gist of the sound processor further includes a function of performing control to be provided.

This is intended to prevent interference between time-division multiplexed audio channels.

It is desirable that the period length of the silent state can be set programmably by a control register or the like. This is to make it possible to select an optimum period length according to the characteristics of the DAC and the like.

According to a fifth aspect of the present invention, when the data output control means outputs data to the cascaded digital-to-analog converters, the data output control means controls the timing of outputting data to a certain digital-to-analog converter. The data is output to the digital-to-analog converter connected to the next stage at a later timing so as to eliminate interference between time slots due to signal delay between the cascaded digital-to-analog converters. The gist of the sound processor further has a function of controlling timing.

When data is simultaneously output to each stage of the cascaded DAC, interference occurs between time-division multiplexed audio channels due to the time required for signal transmission between the DACs. It causes inaccurate reproduction and noise. The present invention is to eliminate this interference.

It is desirable that the above-mentioned output timing can be set programmably by a control register or the like. This is to make it possible to select the optimum output timing according to the characteristics of the DAC.

According to a sixth aspect of the present invention, the audio waveform data is composed of two arrays, and an end code is provided at the end of each of the arrays. From the beginning, immediately after reading the end code of the first array, reading is performed from the beginning of the second array, and after reading the end code of the second array, the second array is successively read. The gist of the sound processor further includes a function of reading from the beginning.

In the sound processor and sound processing apparatus of the PCM system, as one method of waveform data compression, the sound of a sampled musical instrument is decomposed into two parts, an initial striking sound and a vibrating sound. A method of repeatedly reproducing about one or two cycles while performing amplitude modulation is generally used. Here, the portion of the initial impact sound is called an attack portion, and the portion of the vibration sound is called a loop portion. In many musical instrument waveforms, the attack portion shows a waveform close to noise including various frequency components, such as the waveform of a percussion instrument, and the loop portion shows a waveform in which a similar waveform is attenuated and repeated at a certain cycle.

According to the present invention, the reproduction of the audio waveform composed of the above-mentioned attack section and loop section can be performed very easily.
In addition, this is achieved in order to achieve the control without controlling other functional blocks such as a CPU.

According to a seventh aspect of the present invention, there is provided an accumulating means, and means for storing pitch control information, wherein the pitch control information is read out at regular time intervals, and is accumulated by the accumulating means. The gist of the present invention is that the sound processor is characterized in that part or all of the calculation result is used as address information of access to the common bus by the bus master means.

Normally, in pitch conversion performed for the purpose of changing the pitch of an audio waveform, a method of obtaining the waveform data after pitch conversion by complementing the original data without changing the data output timing to the DAC is widely used. Used.
In this method, extremely high-precision pitch conversion can be performed depending on the algorithm of the complementary operation, but the amount of operation is large and a large circuit scale is required.

In the present invention, the cycle of reading the data stored in the data holding means or the resources of the common bus is varied, and the data is output to the digital-to-analog conversion means in synchronization therewith. The pitch conversion is realized very easily. If the conversion speed of the DAC in the digital / analog conversion means is sufficient, the pitch conversion can be performed without deteriorating the sound quality.

According to an eighth aspect of the present invention, there is provided the sound processor, wherein the bus interface means is provided independently for a plurality of common buses.

When the sound processor is connected to a plurality of common buses, a bus interface means is required for each common bus. Here, it is desirable that the bus interface means be provided independently for each common bus, and to access the common bus only when there is an access request according to the request of the bus master means regardless of the operation of other buses. Thereby, even when the sound processor accesses one of the common buses, another bus master can access the other common bus.

The ninth aspect of the present invention further comprises interrupt request control means for generating an interrupt request signal controlled by the sequence control means, wherein the bus master means controls reading of audio waveform data; Envelope / preset control means for controlling reading of envelope data and parameters for controlling sound reproduction, and access to the common bus from the waveform read control means and access to the common bus from the envelope / preset control means. The sound processor comprises access arbitration means for arbitration, wherein the bus interface means comprises first bus interface means for a first common bus, and second bus interface means for a second common bus. Abstract It is intended to.

According to a tenth aspect of the present invention, there is provided a semiconductor device comprising a single semiconductor device and having an independent data transfer capability.
And a second bus, a central processing unit and the sound processor as bus masters of the first and second buses, a memory connected to the first bus, and a first bus for arbitrating the first bus. And a second bus arbitration unit for arbitrating the second bus.

[0043]

FIG. 1 is a schematic diagram showing a basic configuration of a sound processor according to the present invention. This sound processor comprises a sequence control means 1, a bus master means 2, a bus interface means 3, a data holding means 4,
M sets of digital / analog conversion means 5, 5 ',. . , Time-division multiplexing means 6, data output control means 7, first mixing means 8, second mixing means 9, differential amplifier 10,
The accumulating means 11 comprises a main volume control DAC 12.

Hereinafter, each means will be described.

The sequence control means 1 generates a processing sequence and controls the operation of the bus master means 2 based on the generated sequence. This may be a sequencer configured by a counter or a timer, or a processor such as a CPU may be used.

The bus interface means 3 is for inputting and outputting signals to and from a common bus located outside the sound processor. Usually, as shown in an embodiment to be described later, an interface with a bus composed of control signals such as an address bus, a data bus, and a read / write signal is performed, but the bus is not necessarily limited to this configuration. Not something. When a common bus is accessed by a plurality of bus masters, bus arbitration is performed by a bus arbitration signal or the like. The bus interface means may also perform processing for such bus arbitration. Further, as described above, an interface with a plurality of common buses may be used. in this case,
It is preferable that the bus interface unit decodes the address issued by the bus master unit, determines which common bus is to be accessed, and interfaces with the common bus to be accessed.

The bus master means 2 accesses the common bus via the bus interface means 3 under the control of the sequence control means 1. The bus master acquires channel volume data, envelope data, audio waveform data, and other parameters for controlling audio reproduction from resources such as a memory connected to the common bus. Further, the apparatus may further have a function of writing the current state of the sound processing or the like to a resource such as the memory. The bus master means may be configured by wired logic, or may be realized by a processor such as a CPU.

The data holding means 4 holds the data acquired by the bus master means 2. Also,
It may further have a function of temporarily storing data to be written by the bus master means 2 to resources of a common bus such as a memory. The data holding means may be constituted by a memory such as a RAM, or may be a register file constituted by a flip-flop or a latch.

The bus master means 2 judges beforehand whether or not necessary data is stored in the data holding means 4 before accessing the resources of the common bus such as a memory. If not stored, it is desirable to further have a function of accessing the data if it is not stored, acquiring the data, and updating the data of the data holding means. As a result, access to the common bus can be reduced as much as possible, and not only the processing performance of the present sound processor can be improved, but also the period during which another bus master can use the common bus is increased.

The M (M is a natural number) digital-to-analog conversion means 5, 5 ',. . Is for converting at least audio waveform data into an analog audio signal, each of which may be a single digital-to-analog converter or a plurality of digital-to-analog converters as shown in FIG. It may be constituted by a container.

By the way, in order to perform a variety of sound reproduction and a sound reproduction faithful to the original sound using a small amount of sound waveform data,
Performing amplitude modulation of a speech waveform using a so-called envelope is extremely effective. As shown in FIG. 8, a one-cycle sound waveform serving as a fundamental wave is repeatedly reproduced and multiplied by time-varying envelope data to reduce the sound signals of various musical instruments to a small sound. Can be reproduced with waveform data.

When simultaneously reproducing audio waveform data of a plurality of channels, as in the case of reproducing music using a plurality of musical instruments, it is indispensable to control the volume of each channel.

As described above, in order to control the envelope and the channel volume, it is necessary to multiply those parameters by the original audio waveform data. In a conventional PCM tone generator, these multiplications are performed by a digital multiplier, but in the present invention,
As shown in FIG. 1, the operation is performed by an analog multiplication circuit constituted by cascaded DACs.

Here, the configuration of the digital / analog conversion means shown in FIG. 1 is for monaural reproduction. FIG. 2 shows an example of the configuration of the digital / analog conversion means for stereo reproduction.

The main volume control DAC 12 shown in FIGS. 1 and 2 is for controlling the volume of the entire audio signal. The output of this DAC is M sets of digital / analog conversion means 5, 5 ',. . , The analog multiplier circuit is configured as described above. The data output to the main volume control DAC 12 may be performed by a bus master of a common bus such as an external CPU via a control register, or may be performed by the data output control means 6 like other DACs. There may be.

The channel volume control DACs 13, 13 ',. . Is for controlling the volume of each audio channel.

The envelope control DAC 1 shown in FIG.
4, 14 ',. . Is for controlling the envelope of each audio channel. The envelope L control DACs 17, 17 ',. . And the envelope R control DACs 18, 18 ',. . Are for controlling the envelopes of the left channel and the right channel of each audio channel, respectively. By changing the values set in these, effects such as a pan pot can be easily achieved.

The audio waveform reproducing D shown in FIGS. 1 and 2
AC15, 15 ',. . Is for converting PCM audio waveform data into an analog audio signal. In the example shown in FIG. 2, the same audio waveform data is input to the left and right channels, but different data may be input.

D for outputting the middle point of the waveform shown in FIGS.
AC16, 16 ',. . Is DAC1 for audio waveform reproduction
5, 15 ',. . It has exactly the same structure and characteristics. However, as input data, data that is the center point of the waveform amplitude is always input. DA for audio waveform playback
C15, 15 ',. . The waveform output from the main volume control DAC and the channel volume control DAC
In addition, due to the cascade connection with the envelope control DAC, the amplitude is modulated only in the positive direction with a certain voltage value as the lower end. The purpose of the DAC for outputting the waveform midpoint is to generate an offset voltage for causing the waveform output from the differential amplifier to be amplitude-modulated in both positive and negative directions with the center point of the waveform amplitude as the origin.

FIG. 3 shows an example of an audio waveform output from the differential amplifier. The waveform output from the audio waveform reproduction DAC and the waveform output from the waveform midpoint output DAC connected in parallel with the audio waveform reproduction DAC are output to the differential amplifier at the subsequent stage, The difference between the voltage values of the waveforms is amplified by the differential amplifier.

The time-division multiplexing means 6 outputs data of N sets (N is a natural number of 2 or more) of audio channels when outputting data to the M sets of digital / analog converting means via the data output control means 7. Are time-division multiplexed and output. As a result, each digital / analog converting means reproduces the data of the N sets of audio channels in a time-division manner. If the time-division period is sufficiently short, the N sets of audio waveforms are perceptually mixed. Sounds like it is.

FIG. 4 shows an example of a time-division multiplexed audio waveform. Here, four audio waveforms of channel A, channel B, channel C and channel D are multiplexed. What is important here is that in the case of time-division multiplexing of N sets of audio waveforms, the frequency of time-division multiplexing should be higher than the sampling frequency of the original sound by N times or more. In the example of FIG. 4, time-division multiplexing is performed at a frequency four times the sampling frequency of the original sound.

FIG. 5 shows an example of time division multiplexing of data output to the digital / analog conversion means. In this figure, four sets of digital / analog conversion means
Each of the four sets of audio channels is time-division multiplexed to achieve the simultaneous reproduction of 16 channels (channels 0 to 15). When time-division multiplexing is performed by a plurality of sets of digital / analog converting means, if the timing of channel switching is the same for each digital / analog converting means, the noise level may increase. It is desirable that the timing is different for each digital-to-analog conversion means. In the time division multiplexing, as shown in FIG. 5, a method in which a cycle including all audio channels is repeated is preferable.

The data output control means 7 controls data output to the M sets of digital / analog conversion means.

When the data output control means 7 performs data output, it has a function of providing a fixed period of silence between each audio channel in order to eliminate interference between the time-division multiplexed audio channels. It is desirable. The silence period here is created by outputting data indicating the midpoint of the amplitude to the audio waveform reproduction DAC. When a channel volume control DAC and an envelope control DAC are provided, data for which the multiplication result is 0 should be output to them at the same time.

In the example shown in FIG. 5, a silent period is also provided.

It is desirable that the length of the silent period can be set programmably by a control register or the like.

When the DACs are cascaded, interference may occur between time-division multiplexed audio channels due to signal delay. In order to eliminate this interference, the data output control means 7 delays the timing of outputting data to a DAC cascade-connected to the next stage by a certain time with respect to the timing of outputting data to a certain DAC. It is desirable to have further functions.

It is desirable that the length of this delay can be set programmably by a control register or the like.

The first mixing means 8 mixes the outputs from the M audio waveform reproducing DACs. As shown in FIG. 1, the second mixing means 9 is required when each of the M sets of digital-to-analog conversion means 5 includes a DAC for outputting a waveform midpoint. DAC
Mix the output of Each mixing means may be a simple one configured using, for example, a resistor.

In the example shown in FIG. 2, the first mixing means 8 and the second mixing means 9 perform mixing for the left channel, and the third mixing means 19 and the fourth mixing means 20 perform mixing for the right channel. Do.

The differential amplifier 11 includes a first mixing unit 8
And an amplifier for amplifying the difference between the signals output from the second mixing means 9 and outputting an audio signal. The differential amplifier may be provided in a semiconductor device in which the present sound processor is configured, or may be provided outside the semiconductor.

In the example shown in FIG. 2, the first differential amplifier 21 is used to amplify the difference between the outputs of the first mixing means 8 and the second mixing means 9 and to output the left channel audio signal L. The second differential amplifier 22 is used to amplify the difference between the outputs of the third mixing means 19 and the fourth mixing means 20 and to output the right channel audio signal R.

The accumulating means 11 is used for pitch conversion which is performed by changing a cycle for reading out audio waveform data and envelope data. The pitch control information is read out at regular intervals and accumulated by accumulating means, and the accumulated result is processed to become an address pointer of the data. Therefore, if a large value is set in the pitch control information, the increment of the address pointer is performed quickly, and if a small value is set, the increment is slow.

The pitch control information may be stored in an independent data holding means, but is stored in the data holding means 4 in the example shown in FIG.

FIG. 6 shows a model of accumulating means for pitch conversion. The pitch control information stored in the pitch control information storage means is read out at regular intervals, and is accumulated by an accumulator including data holding means such as a register and an adder. The accumulation result is converted into address information by the bus master means 2 or the like.

As an example of address conversion, there is a method of adding the upper N bits of the accumulation result as an offset address to a base address indicating the head of an array in which data is stored. FIG. 7 shows an example of pitch conversion in audio waveform reproduction based on this method.

In the example shown in FIG. 7, two cases where the pitch control information is 0.2500 and 0.3536 are taken, and the resulting waveforms are compared.

In this example, the audio waveform data is stored in the memory for each byte. This is an 8-bit P
This is CM data, and is represented by two's complement. The data in the figure is in hexadecimal notation. The address indicating this data is incremented by one for each byte.

The integer part of the accumulation result is used as an offset address indicating the data. The two resulting waveforms are shown in FIG. as a result,
The frequency of the waveform when the pitch control information is 0.3536 is a multiple of the square root of the frequency when the pitch control information is 0.2500, that is, a half octave higher.

The bus master 2 starts reading from the head of the first array in which the audio waveform data is stored, and immediately after reading the end code of the first array,
After reading the end code of the second array from the head of the second array and reading the end code of the second array, the system further has a function of continuously reading the second array from the head. This function is very suitable for reproducing the sound waveform of a musical instrument composed of an attack part and a loop part.

FIG. 8 shows the relationship between an example of a speech waveform composed of an attack portion and a loop portion and the above-mentioned first and second arrays. The attack portion of the voice waveform shown here is similar to a striking sound including various wide-range frequency components, and the entire attack portion is stored as PCM data in the first array. The loop section shown here can be reproduced by amplitude-modulating the repetition of one cycle of the waveform using an envelope. The waveform data of one cycle of the loop is
Are stored as PCM data.

In the sound processor shown in FIG. 1, the head address of the first array and the head address of the second array are suitably stored in the control register or the data holding means 4.

[0084]

FIG. 9 shows an outline of a main part of a sound processor according to the present invention as an embodiment. The sound processor includes a control register 31, a local RAM 32, an ALU /
Accumulator 33, sequencer 34, waveform read control circuit 3
5, envelope / preset control circuit 36, interrupt request control circuit 37, access arbitration circuit 38, first bus interface 39, second bus interface 40,
Data output control circuit 41, main volume control DAC
42, a DAC block 43, a first mixer 44, a second mixer 45, a third mixer 46, a fourth mixer 47, a first differential amplifier 48, a second differential amplifier 49, and a local bus.

The sound processor is connected to two common buses located outside the sound processor, a first bus and a second bus. An external bus master such as a CPU can control the sound processor through the first bus. The sound processor can access resources such as a memory connected to the first bus and the second bus.

The control register 31 is connected to the first bus, and holds control data of each unit written from a bus master of the first bus such as a CPU. A bus master such as a CPU can read the data from the control register 31 to know the current state of the sound processor.

The local RAM 32 is composed of 192 × 16 bits and a total of 384 bytes.
5 and the data obtained by the envelope / preset control circuit 36 and the progress of the processing. The local RAM 32 provides the function of the data holding unit 4 shown in FIG.

The ALU / accumulator 33 performs arithmetic logic operation and accumulation. The waveform read control circuit 35 and the envelope / preset control circuit 36 are used for performing an address calculation, and the interrupt request control circuit 37 is used for calculating an interval between interrupt request signals. ALU / accumulator 33
Provides the function of the accumulation means 11 shown in FIG.

The sequencer 34 controls the waveform read control circuit 35, the envelope / preset control circuit 36, and the interrupt request control circuit 37 based on a time schedule generated by an internal counter.
When performing audio reproduction, channel volume data, envelope data L, envelope data R, and audio waveform data of each audio channel are read from the local RAM 32 and output to the data output control circuit 41 by time division multiplexing. The sequencer 34 provides the functions of the sequence control means 1 and the time division multiplexing means 6 shown in FIG.

The waveform read control circuit 35 converts the audio waveform data of each audio channel from the memory connected to the first bus or the second bus based on the control data written in the control register 31 and the control from the sequencer 34. Controls reading.

Further, the waveform read control circuit 35
Has the function of reproducing the audio waveform data composed of the second array and the second array as described above.

Envelope / preset control circuit 36
Control for reading the envelope data L / R of each audio channel from the memory connected to the first bus or the second bus based on the control data written in the control register 31 and the control from the sequencer 34; Before starting the sound reproduction, it controls an operation called a preset for reading various parameters for controlling the sound reproduction from the memory connected to the first bus into the local RAM 32.

The access arbitration circuit 38 includes a waveform read control circuit 35 and an envelope / preset control circuit 36.
Arbitration of access to the first bus and the second bus from the Internet. The waveform read control circuit 35, the envelope / preset control circuit 36, and the access arbitration circuit 38 together provide the function of the bus master means 2 shown in FIG.

The interrupt request control circuit 37 generates an interrupt request signal to the external CPU based on the control data written in the control register 31 and the control from the sequencer 34. This interrupt request signal is sent to the external CPU
Are generated at regular time intervals to manage the sound processor based on the score data. The interrupt request control means 37 has four interrupt sources, each of which generates an interrupt request at an independent time interval using the ALU / accumulator 33. The output interrupt request signal is a logical sum of these four interrupt requests.

The first bus interface 39 accesses the memory connected to the first bus based on the access request to the first bus arbitrated by the access arbitration circuit 38. In a system that requires bus arbitration when accessing the first bus, access is performed based on a bus arbitration signal.

The second bus interface 40 accesses the memory connected to the second bus based on the access request for the second bus arbitrated by the access arbitration circuit 38. In a system in which bus arbitration is required when accessing the second bus, access is performed based on a bus arbitration signal. The first bus interface 39 and the second bus interface 40 together provide the function of the bus interface means 3 shown in FIG.

The data output control circuit 41 temporarily stores channel volume data, envelope data L / R and audio waveform data output to the DAC block 42 in internal registers, and outputs the data to the DAC block 42 at appropriate timing. The data output control circuit 41 can eliminate interference between audio channels arranged in adjacent time slots by providing a certain period of silence between time slots of time-division multiplexed audio channel data. In addition, the main volume data, the channel volume data, the envelope data L / R, and the audio waveform data are output with a slight time difference in the order, so that the audio channels between the cascaded DACs are delayed by a signal delay. Interference can be eliminated.
The length of the silence period and the period of the time difference can be set programmably through the control register 31.
These lengths can be optimized in accordance with the characteristics and the like.

The main volume control DAC 42 controls the volume of the entire audio signal based on the value written in the control register 31. The output of this DAC is DAC
4 sets of channel volume control DA in block 43
It is connected to the reference voltage input of C.

The DAC block 42 has four sets of digital
Each of the digital-to-analog conversion means is provided with one channel volume control DA.
C, one envelope L control DAC, one envelope R control DAC, two audio waveform reproduction DACs, and two waveform midpoint output DACs. Channel volume data, envelope data L, envelope data R, and audio waveform data are input from the data output control circuit 31, and a fixed value indicating the middle point of the waveform amplitude is input to the DAC for waveform middle point output. . These DACs
Are connected in the same manner as shown in FIG. 2
One of the two audio waveform playback DACs is for the left channel,
The other is for the right channel. DA for waveform midpoint output
The same applies to C. The cascaded DACs constitute an analog multiplication circuit, and achieve high-speed multiplication with a small circuit scale.

The first mixer 44 mixes the outputs from the four audio waveform reproduction DACs for the left channel.

The second mixer 45 mixes the outputs from the four waveform center point output DACs for the left channel.

The third mixer 46 mixes the outputs from the four audio waveform reproduction DACs for the right channel.

The fourth mixer 47 mixes the outputs from the four waveform midpoint output DACs for the right channel.

The first differential amplifier 48 amplifies the difference between the outputs from the first mixer 44 and the second mixer 45, and outputs a left channel audio signal L.

The second differential amplifier 49 amplifies the difference between the outputs from the third mixer 46 and the fourth mixer 47 and outputs a right channel audio signal R.

FIG. 10 shows the contents of the local RAM 32.

The local RAM 32 stores 24 bytes of data per audio channel for 16 channels, for a total of 38
4 bytes are stored. One word is 2 bytes, that is, 1
It consists of 6 bits. Words from 00h (h represents a hexadecimal number) words to 0Bh words are allocated for channel 0, and the remaining 15 channels are allocated to BFh words in order. The content of each channel is the same. Hereinafter, the data for channel 0 will be described as an example.

The 00h word stores waveform reproduction mode and waveform reproduction pitch control information. The waveform reproduction mode is data for selecting one of the four types of prepared waveform reproduction modes. The waveform reproduction pitch control information is information for controlling the pitch of waveform reproduction as described above.

The word 01h stores the current value of the first address of the waveform data array / current address of the waveform address.
Here, the head address of the first array is set by the CPU or the like before the reproduction, and the current address value of the waveform data is held during the reproduction.

The 02h word stores the start address of the second array of waveform data. Here, before playback,
The start address of the second array is set by U or the like, and the value is held during reproduction.

In the 03h word, the waveform data bank address is stored in the lower byte, and the upper byte is used as a waveform data cache. This sound processor is 2
The 4-bit address space can be accessed, and the waveform data bank address indicates the address of the upper 8 bits.
The waveform data bank address represents a 24-bit address in combination with the above-described waveform data first array head address / waveform address current value and waveform data second array head address. The waveform data cache is an area for temporarily storing the waveform data acquired from the memory. When the waveform data to be reproduced is stored at the same address as the previous time, the waveform read control circuit 35 acquires the data from the waveform data cache without acquiring the data from the memory.

The 04h word stores channel volume, envelope mode, and envelope pitch control information. The channel volume is output to the above-described channel volume control DAC, and controls the volume of channel 0. The envelope mode is data for selecting one of the four types of envelope control modes prepared. The envelope pitch control information is information for controlling the pitch of the envelope as described above.

In the 05h word, the envelope data L
The start address and the current address value are stored. Here, the head address of the envelope data L is set by the CPU or the like before the reproduction, and the current address value of the envelope data L is held during the reproduction.

In the 06h word, the envelope data R
The start address and the current address value are stored. Here, the head address of the envelope data R is set by the CPU or the like before the reproduction, and the current address value of the envelope data R is held during the reproduction.

In the 07h word, the envelope bank address and the current value of the envelope address (decimal part) are stored. The envelope bank address indicates the address of the upper 8 bits of the 24-bit address, and includes the above-described envelope data L head address and address current value;
A 24-bit address is represented together with the envelope data R start address and the current address value. The envelope address current value (decimal part) holds the accumulation result at the time of pitch conversion together with the envelope data L current value and the envelope data R current value.

The 08h word is used as an envelope data L cache and an envelope data R cache. Here, the envelope data to be set next is obtained from the memory by the envelope / preset control circuit and held.

In the 09h word, the envelope data L
The current value and the envelope data R current value are stored.

The 0Ah word stores the current value of the waveform address (decimal part). The waveform address current value (decimal part) holds an accumulation result at the time of pitch conversion together with the waveform address current value.

The 0Bh word stores an interrupt request signal timing. The interrupt request signal timing is
The interrupt request signal circuit 37 holds the accumulation result performed by using the ALU / accumulator 33. When an overflow occurs, the interrupt request signal circuit 37 generates an interrupt request signal.

Next, a sound processing apparatus using the sound processor according to the present invention will be described.

FIG. 11 schematically shows a main part of a sound processing apparatus according to the present invention. The sound processing device according to the present embodiment includes a central processing unit (CPU) 61,
Sound processor 62, DMA controller 63, internal memory 64, first bus arbitration circuit 65, second bus arbitration circuit 66, input / output control circuit 67, timer circuit 68, analog / digital converter 69, PLL circuit 70, clock driver 71 , A low voltage detection circuit 72, an external memory interface circuit 73, and a DRAM refresh control circuit 74 as necessary.

The present sound processing apparatus has a first bus composed of a 16-bit first address bus and a read / write signal, an 8-bit first data bus, and a 24-bit second bus.
A second bus including an address bus, a read / write signal, and an 8-bit second data bus is further provided.

Outside the sound processing apparatus, one or more external ROMs 75 and, if necessary, one or more external RAMs
A battery 78 is required for holding an oscillation circuit composed of the crystal oscillator 76, a crystal oscillator 77, and the like, and for holding data in a static RAM (hereinafter abbreviated as SRAM) as required.

Next, the function of each unit constituting the sound processing apparatus will be described.

The CPU 61 performs various calculations and controls the entire system according to a program stored in the memory. C
The PU 61 is a bus master of the first bus and the second bus, and can access resources connected to each bus.

As the sound processor 62, the sound processor of this embodiment shown in FIG. 9 is used as it is. The sound processor 62 is a bus master of the first bus and the second bus, and has an internal memory 64, an external RO
The data stored in the M75 and the external RAM 76 are read, and a stereo audio signal L / R is generated and output. The sound processor 62 is controlled by the CPU 61 through the first bus.

The DMA controller 63 has an external ROM 7
5 or the data transfer from the external RAM 76 to the internal memory 64. Further, it has a function of generating an interrupt request signal to the CPU to notify the completion of the data transfer. The DMA controller 63 is a bus master of the first bus and the second bus. The DMA controller 63 is controlled by the CPU 61 through the first bus.

The internal memory 64 includes a mask ROM, an SRA
M, and dynamic RAM (hereinafter abbreviated as DRAM). If the SRAM needs to be held by a battery, a battery 78 is required outside the sound processing apparatus. When a DRAM is mounted, an operation called “refresh” for holding stored contents is required periodically.

The first bus arbitration circuit 65 receives a first bus use request signal from each bus master of the first bus, performs arbitration, and issues a first bus use permission signal to each bus master. Each bus master is permitted access to the first bus by receiving the first bus use permission signal. Here, the first bus use request signal and the first bus use permission signal are shown as a first bus arbitration signal in FIG.

The second bus arbitration circuit 66 receives a second bus use request signal from each bus master of the second bus, performs arbitration, and issues a second bus use permission signal to each bus master. Each bus master is permitted access to the second bus by receiving the second bus use permission signal. Here, the second bus use request signal and the second bus use permission signal are shown as a second bus arbitration signal in FIG.

The input / output control circuit 67 communicates with an external input / output device or an external semiconductor device through input / output signals. Input / output data is read / written from the CPU 61 via the first bus.

The timer circuit 68 has a function of generating an interrupt request signal to the CPU 61 based on the set time interval. The setting of the time interval and the like is performed by the CPU 61 via the first bus.

The analog / digital converter 69 converts an analog level input voltage signal into a digital value.
Further, it has a function of generating an interrupt request signal to the CPU 61 to notify the completion of the conversion. The converted data is read by the CPU 61 via the first bus.

The PLL circuit 70 is constituted by a phase locked loop (PLL), and generates a high frequency clock signal obtained by multiplying a sine wave signal obtained from the crystal unit 77 outside the processor.

The clock driver 71 includes a PLL circuit 70
The received high frequency clock signal is amplified to a signal strength sufficient to supply the clock signal to each functional block.

The low voltage detection circuit 72 monitors the power supply voltage, and when the power supply voltage is lower than a predetermined fixed voltage, the PLL
A reset signal for the circuit 70 and other reset signals for the entire system are issued. Further, the internal memory 64 or the external RAM 76 is constituted by an SRAM,
When the data retention by the AM battery is required, a function is provided for issuing a battery backup control signal when the power supply voltage is equal to or lower than a predetermined fixed voltage.

The external memory interface circuit 73
It has a function of connecting the second bus to the external bus and a function of controlling the bus cycle length of the second bus by issuing a second bus cycle end signal.

The DRAM refresh control circuit 74 unconditionally acquires the right to use the first bus at regular intervals, and
The M refresh operation is performed.

[0139]

According to the sound processor of the present invention, the resources connected to the common bus can be actively accessed. That is,
Because it is possible to directly access the vast address space,
It is possible to take in data without relying on another bus master such as a CPU or other common bus. Further, the size of the audio waveform data and the data of various parameters is not limited by the capacity of the local memory. Further, since the sound processor does not require a large-capacity local memory, it can be provided at low cost.

The second effect of the present invention is that M sets of digital-to-analog conversion means are independently provided, and that data of N sets of audio channels are converted from digital to analog by time division multiplexing. And N, the simultaneous reproduction of data of a plurality of sets of audio channels represented by the product of N and N can be realized with a small circuit scale.

A third effect of the present invention is that it is determined whether or not data required for reproduction is stored in the data holding means, and the data required for reproduction is stored in the data holding means. If not, it has a function of acquiring the data from the resources connected to the common bus and storing the data in the data holding means. Normally, the time required to acquire data from a data holding unit such as a local memory is shorter than the time required to acquire data from a resource connected to a common bus, so that the above-described function must be provided. As a result, the processing capability of the sound processor can be improved. Further, since unnecessary access to resources connected to the common bus is reduced,
Other bus masters of the common bus such as U can use the common bus more, and it is expected that the processing capacity of the entire system including the present sound processor is improved.

A fourth effect of the present invention is that the multiplication performed by the sound processor of the present invention is limited to the sound processing, and therefore, it is not necessary that the accuracy beyond the audible distinction is unnecessary. Using a cascaded DAC without using a high-speed digital multiplier and a high-precision DAC that require a large circuit scale,
Similar functions can be exhibited with a small circuit scale.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of a sound processor according to the present invention.

FIG. 2 is a diagram illustrating a configuration example of a digital / analog conversion unit for stereo reproduction.

FIG. 3 is a diagram illustrating an example of an audio waveform output from a differential amplifier.

FIG. 4 is a diagram showing an example of a time-division multiplexed audio waveform.

FIG. 5 is a diagram illustrating an example of time division multiplexing of data output to a digital-to-analog converter.

FIG. 6 is a diagram showing a model of accumulating means for pitch conversion.

FIG. 7 is a diagram illustrating an example of pitch conversion in audio waveform reproduction.

FIG. 8 is a diagram showing an example of a speech waveform composed of an attack section and a loop section.

FIG. 9 is a schematic diagram of a main part of the sound processor of the embodiment.

FIG. 10 is a table showing contents of a local RAM according to the embodiment;

FIG. 11 is a schematic diagram of a main part of the sound processing device of the embodiment.

[Brief description of reference numerals]

DESCRIPTION OF SYMBOLS 1 Sequence control means 2 Bus master means 3 Bus interface means 4 Data holding means 5 Digital / analog conversion means 6 Time division multiplexing means 7 Data output control means 8 First mixing means 9 Second mixing means 10 Differential amplifier 11 Accumulation means 12 Main volume control digital-analog converter

Claims (14)

[Claims] 1. A semiconductor device comprising: a single semiconductor device;
A sound processor for reproducing pulse code modulated audio waveform data, comprising: a sequence control unit; a bus interface unit for a common bus including an address bus and a data bus; and a bus interface based on control from the sequence control unit. Bus master means for issuing an address to the common bus via means for reading and writing data to resources connected to the common bus; and data for holding a part of the data read by the bus master means. Holding means; M sets (M is a natural number) of independent digital / analog converting means for converting digital data of an audio channel into an analog audio signal; and data output controlling means for controlling data output to the digital / analog converting means And need for playback Time-division multiplexing means for time-division multiplexing and outputting N sets (N is a natural number of 2 or more) of audio channels for each digital / analog conversion means. A sound processor that can simultaneously reproduce data of multiple sets of audio channels represented by the product. 2. The bus master means determines whether or not data required for reproduction is stored in the data holding means, and data required for reproduction is stored in the data holding means. 2. The sound processor according to claim 1, further comprising a function of acquiring the data from a resource connected to a common bus when there is no data and storing the data in the data holding unit. 3. The digital-to-analog converter comprises a plurality of digital-to-analog converters, and each of the digital-to-analog converters is connected in cascade. A sound processor according to any one of the above. 4. One main volume control digital
Further comprising an analog converter, wherein each of the M sets of digital / analog conversion means comprises
One channel volume control digital-to-analog converter, one envelope control digital-to-analog converter, one digital-to-analog converter for audio waveform reproduction,
It is composed of one waveform midpoint output digital / analog converter, and the M channel volume control digital / analog converter is provided next to the main volume control digital / analog converter.
An analog converter is cascade-connected in parallel, and one envelope control digital-analog converter is cascade-connected to each next stage, and one digital-analog converter for audio waveform reproduction is provided to each next stage. A first mixing means for mixing the outputs of the M audio waveform reproduction digital-to-analog converters in parallel with each other and a cascade-connected digital-to-analog converter for outputting one waveform midpoint; Second mixing means for mixing the outputs from the digital-to-analog converters for outputting the waveform midpoints, wherein the outputs of the first and second mixing means are provided inside or outside the semiconductor. 3. The sound processor according to claim 1, wherein the sound processor is connected to two inputs of a differential amplifier. 5. One main volume control digital
Further comprising an analog converter, wherein each of the M sets of digital / analog conversion means comprises
One channel volume control digital-to-analog converter, one first envelope control digital-to-analog converter, one second envelope control digital-to-analog converter, one digital-to-analog converter for reproducing the first audio waveform , One digital-to-analog converter for reproducing the second audio waveform, one digital-to-analog converter for outputting the middle point of the first waveform, and one digital-to-analog converter for outputting the middle point of the second waveform The main channel control digital-to-analog converter has the following M channel volume control digital / analog converters.
Analog converters are cascaded in parallel, each of which has one first envelope control digital
An analog converter and a second envelope-controlled digital-to-analog converter are cascaded in parallel, and one digital-to-analog converter for reproducing the first audio waveform is provided next to each of the first envelope-controlled digital-to-analog converters. And a first waveform middle point output digital-to-analog converter are cascaded in parallel, and one digital audio-to-analog converter for reproducing the second audio waveform is provided next to each of the second envelope control digital-to-analog converters. And a second waveform midpoint output digital-to-analog converter cascaded in parallel, and a first mixing means for mixing the outputs of the M first audio waveform reproduction digital-to-analog converters; Second mixing means for mixing the output from the digital-to-analog converter for outputting the first waveform middle point, and the M second audio waves A third mixing unit that mixes the outputs of the digital-to-analog converters for reproduction; and a fourth mixing unit that mixes the outputs from the digital-to-analog converters for outputting the M second waveform middle points. The outputs of the first and second mixing means are respectively connected to two inputs of a first differential amplifier provided inside or outside the semiconductor, and the output of the third and fourth mixing means is 3. The sound processor according to claim 1, which is connected to two inputs of a second differential amplifier provided inside or outside the semiconductor. 6. The data output control means performs a control such that when outputting data to the digital-to-analog conversion means, a silence state for a certain period is provided between adjacent time-division multiplexed audio channels. The sound processor according to any one of claims 1 to 5, further having a function of performing: 7. The sound processor according to claim 6, wherein the period of the silent state is programmable. 8. The data output control means, when outputting data to the cascade-connected digital-to-analog converters, outputs the data to a certain digital-to-analog converter at the next stage with respect to the timing of outputting the data. Digital connected
The analog converter further outputs data at a later timing, and further has a function of controlling output timing so as to eliminate interference between time slots due to signal delay between the cascaded digital-analog converters. The sound processor according to claim 3. 9. The sound processor according to claim 8, wherein a timing at which the data output control means outputs data is programmable. 10. The audio waveform data is composed of two arrays, and an end code is provided at the end of each of the arrays.
Starting from the beginning of the array, reading immediately from the beginning of the second array immediately after reading the end code of the first array, and after reading the end code of the second array, 2. The apparatus according to claim 1, further comprising a function of reading the second array from the beginning.
10. The sound processor according to any one of claims 9 to 9. 11. An accumulating means, further comprising means for storing pitch control information, wherein the pitch control information is read out at regular time intervals, accumulated by the accumulating means, and one of the accumulation results is stored. 11. The sound processor according to claim 1, wherein a part or all of the sound processor is used as address information of an access to the common bus by the bus master unit. 12. The sound processor according to claim 1, wherein said bus interface means is provided independently for each of a plurality of common buses. 13. An interrupt request control means for generating an interrupt request signal under the control of said sequence control means, said bus master means for controlling reading of audio waveform data, envelope data and audio reproduction. Envelope / preset control means for controlling the reading of parameters for controlling the read / write control, and access arbitration means for arbitrating access to the common bus from the waveform read control means and access to the common bus from the envelope / preset control means. The sound processor according to any one of claims 1 to 11, wherein the bus interface means comprises first bus interface means for a first common bus and second bus interface means for a second common bus. 14. A first and second bus configured on a single semiconductor device and having independent data transfer capabilities, a central processing unit as a bus master of the first and second buses, and 14. A sound processor according to claim 12 or 13, a memory connected to a first bus, first bus arbitration means for arbitrating the first bus, and a second bus for arbitrating the second bus. A sound processing device including a bus arbitration unit.