JPH11215093A - Method and apparatus for transmission band variable of orthogonal frequency division multiplex modulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transmission system, which automatically follows a change on a reception side by varying transmission band width by means of changing the period of a clock. SOLUTION: A clock rate conversion part 10 of a transmission side changes a clock CK from a clock oscillator 11 into the clock of a rate corresponding to a changed band width. A synchronism detector 15 searches a SWEEP symbol with a NULL period detected from inputted signals R'sg and I'sg as references, phase-compares it with a matching pulse showing a received frame period, and controls the period of a clock CKrc on a reception side. A clock oscillator 12 raises/lowers the period of the outputted clock CKrc in accordance with the level of the voltage of a signal VC applied form the synchronism detector 15, namely, the clock rate conversion of the clock CKd of the transmission side. The clock CKrc and a frame period pulse FSTrc, which are used on the reception side, are made to follow the clock CKd and a frame period pulse FST, which are changed on the transmission side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an orthogonal frequency division multiplex modulation type digital transmission apparatus.

[0002]

2. Description of the Related Art In recent years, digitization of television broadcasting has been studied in Europe, the United States, and Japan. As a modulation method, OFDM (Orthogonal Freq) is used.
(UencyDivision Multiplex) modulation method is considered promising. The OFDM modulation system is a type of multi-carrier modulation system in which a large number of digitally modulated waves are added. At this time, the modulation system of each carrier is QPSK.
(Quadrature Phase Shift Keying) method or the like is used. When this OFDM signal is expressed by an equation, it is expressed as follows. First, assuming that the QPSK signal of each carrier is α _k (t), this can be expressed by equation (1). α _k (t) = _ak (t) × cos (2πkft) + b _k (t) × sin (2πkft) (1) where k indicates a carrier number and a _k (t) , B _k (t)
Is the data of the k-th carrier and takes a value of [-1] or [1]. Next, assuming that the number of carriers is N, the OFDM signal is a combination of N carriers, and if this is β _k (t), this can be expressed by the following equation (2). β _k (t) = Σα _k (t) (2) Here, k = 1 to N.

[0003] An OFDM signal is composed of the above signal units. This signal unit symbol is, for example, data of 1024 valid samples to which 32 samples of guard interval data are added, 396 sets of 1056 samples of symbols, and 4 sets of synchronization symbols added to all 40 symbols.
It is composed of a repetition of a stream unit called a frame composed of 0 symbols. FIG. 6 is a block diagram showing a basic configuration of the OFDM modem. Hereinafter, OFDM
The configuration and operation of the modem will be described with reference to FIG. The continuously input data Din is transmitted to the rate conversion unit 1
, And for each frame period of 400 symbols, for example, 4 symbol periods corresponding to a synchronization symbol period described later, and 273 to 7 in each information symbol.
It is output as data Dii during a period excluding the unnecessary carrier blank corresponding to a period up to 52 samples. Note that the rate conversion unit 1 outputs an FST signal indicating the start of the synchronization symbol period to other units every 400 symbols which is a frame period. The encoding unit 2T encodes the input data and outputs encoded data Rf and If mapped to two axes of I and Q.

[0004] IFFT (Inverse Fast Fourier Transfor
The m: inverse Fourier transform) unit 3A regards the encoded data Rf and If as frequency components and converts them into time-axis signals R and I consisting of 1024 samples. The guard addition unit 3B has 1024
For example, the waveform of the first 32 samples of the start period waveforms of the signals R and I composed of samples are added after 1024 samples, and the time waveform signals Rg and Ig of 1056 samples in total are output. The synchronization symbol insertion unit 5 outputs, for each of the information symbols m, the signals Rsg and Isg in which a synchronization symbol composed of, for example, four symbols has been inserted and stored in a memory or the like in advance.
Create and output This signal is quadrature-modulated by the quadrature modulation processing unit 8, becomes an OFDM modulated wave signal having a frame configuration as shown in FIG. 7B, and transmitted from the transmission side to the reception side. The clock CK from the clock oscillator 11
Is supplied to each part. The transmitted OFDM modulated wave is converted into a baseband OFDM signal by a quadrature demodulation processing unit 9 on the receiving side.
The signals are orthogonally demodulated and output as time axis signals R'sg and I'sg. The signals R'sg and I'sg are input to the synchronization detector 4, where a synchronization symbol group is detected, and an FST'r pulse representing a frame period is output to each unit. Further, the time axis signals R'sg and I'sg are input to the FFT unit 3C, and are converted from time waveform signals into frequency component signals R'f and I'f.
The signals R'f and I'f are decoded by the decoding unit 2R, and the signal D'o is output. Then, after being converted into a continuous data signal Dout by the rate reverse conversion section 7, it is output.

Next, a detailed configuration and operation of each section will be described. First, an example of the rate converter 1 is shown in FIG. The clock CK input to the rate converter 1 is PL
L / VCO 1-2 is input to PLL / VCO 1-2
Outputs a clock CKm having a frequency of N / G times. The clock CK is also input to the FST counters 1-4, where F is a frame reference for processing on the transmission side.
Generates and outputs ST pulse. This FST pulse is input to the WRST terminal and the RRST terminal of the FIFO memory 1-3, and serves as a reference for resetting writing and reading. The input continuous data Din is converted into a parallel signal by the serial / parallel (S / P) converter 1-1 and input to the FIFO memory 1-3. Here, the data signal Dii having the blank period as described above. (FIG. 7
(A)) is output.

Next, an example of the encoding unit 2T is shown in FIG.
explain. The signal Dii output from the rate converter 1 is input to the mapping ROMs 2-1 and 2-2, and is converted into signals at predetermined points on the I and Q axes. The signal in the period corresponding to the unnecessary carrier shown in (a) of FIG.
4 is replaced with "0", and the above-described signals Rf and If are created. The selectors 2-3 and 2-4 output the clock C
It is controlled by a controller 2-5 whose timing is determined based on the K and FST pulses. Next, an example of the IFFT conversion unit 3A will be described with reference to FIG. The controller 3A-2, whose timing is determined by the clock CK and the FST pulse, converts the input signals Rf and If into the time waveform signals R and I based on a signal of a symbol period including a guard period. . This can be specifically realized by using, for example, PDSP16510 of Pressy Corporation.

Next, an example of the guard adding section 3B will be described with reference to FIG. The signals R and I input here are
A delay unit 3B-1, which delays the signal by 1024 samples,
3B-2 and selectors 3B-3 and 3B-4, respectively, and each selector 3B-3 and 3B-4 outputs 1 to 10
The signals R and I which are not delayed until the 24th sample are 10
Delay unit 3B from 25th sample to 1056th sample
A signal delayed by 1024 samples in -1, 3B-2 is selected and output. As a result, the output signals Rg and Ig in which each symbol is composed of 1056 samples are 102
A time waveform of 1 to 32 samples is added to the 5th to 1056 samples. The selectors 3B-3 and 3B-4 are controlled by a controller 3B-5 whose timing is determined by the clock CK and the FST pulse. Next, an example of the synchronization symbol insertion unit 5 will be described with reference to FIG. The clock CK and FST
Controller 5 whose timing is determined by pulse
The ROMs 5-1 and 5-2 controlled by -5 generate the above-mentioned synchronization symbol signal at a timing corresponding to the FST pulse. Similarly, the selectors 5-3 and 5-4 controlled by the controller 5-6 whose timing is determined by the clock CK and the FST pulse are provided to the guard adding unit 3B
In the current stage of the guarded time signals Rg and Ig generated in the above, only four symbol periods, which are no signal periods, are stored in the ROM5-
The synchronization symbol signals from 1, 5-2 are selected and output. As a result, the time waveform signals Rsg and Isg shown in FIG. 7A into which the synchronization symbol signal is inserted are output.

Here, the NULL symbol shown in FIG. 7B is for roughly detecting the existence of a synchronization symbol group, and does not output any signal during this symbol period. The SWEEP symbol is for accurately determining the switching point of each symbol, and has a waveform that changes from the lower limit frequency of the transmission band to the upper limit frequency in one symbol period. Then, the D / A converter 81 of the quadrature modulation processing unit 8 performs D / A conversion of the real part signal Rsg and the imaginary part signal Isg of the time waveform signal.
2, the carrier signal of the frequency fc from the local oscillator 83 is used for the real part signal, and the carrier signal of the frequency fc of the local oscillator 83 is used for the imaginary part signal.
Quadrature modulation is performed on the signals shifted by 0 °, and these signals are combined to obtain an OFDM signal.

Next, the configuration and operation of the receiving side will be described. First, the transmitted frame-structured signal is input to the quadrature demodulation processing unit 9. In this process, the output of the quadrature demodulator 91 demodulated with the carrier signal of the voltage controlled oscillator 93 and the output demodulated with the carrier signal shifted by 90 ° are output as the imaginary part in the quadrature demodulator 91, contrary to the transmitting side. It is extracted as a signal. These demodulated analog signals of the real part and the imaginary part are converted into digital signals by the A / D converter 94. Next, an example of the synchronization detector 4 is shown in FIG. The quadrature demodulated digital signals R'sg and I '
sg is the NULL end detector 4-1 and the SWEEP operation unit 4
-2. The NULL end detector 4-1 detects a NULL symbol, which is a period of no signal, from a symbol group of a frame structure, detects a rough position of a synchronization symbol, and starts a NULL circuit from a NULL circuit by a timer circuit (not shown). SWEE symbol start time is estimated and SWEE
A P period flag pulse is output. SWEEP operation unit 4-
2 refers to the SWEEP period flag pulse and sets NULL
By the SWEEP symbol that exists after the symbol,
Search for the correct switching timing of each symbol.
More specifically, the pattern of the SWEEP symbol is stored in the built-in memory in advance, the input OFDM signal is correlated with the signal stored in the memory, and when the signal pattern of the memory matches the pattern of the OFDM signal. Input the coincidence pulse to the reset terminal of the frame counter 4-4.

The frame counter 4-4 has a value whose count number constitutes a frame period, for example, 422400 (= 1).
(056 × 400), the value is returned to 0, an FSTr pulse indicating the frame start timing is output, and counting is started again. After that, constant count,
That is, an FSTr pulse is output at each frame start point, indicating the frame start time. On the receiving side, the FSTr pulse is output to the FFT unit 3C, the decoding unit 2R, the rate inverse conversion unit 7
At the start timing. The FFT transformer 5 calculates F
OFDM demodulation is performed by dividing symbols based on the STr pulse and performing Fourier transform to output the frequency component signals R′f and I′f. The decoding unit 2R is, for example, RO
The signals R′f and I′f are identified by the M table method, and the decoded signal D′ o is calculated. Rate reverse converter 7
The operation timing is determined by the clock CKr and the FSTr pulse, and the configuration of the rate conversion unit 1 is inverted.
(Conversely). By the way, the transmitted OFDM
The bandwidth of the signal is twice the bandwidth of the baseband signals Rsg and Isg. The bands of the baseband signals Rsg, Isg are
It is determined depending on the data corresponding to the carrier input to the IFFT unit 3A.

Here, regarding the operation of the IFFT unit 3A,
This will be described with reference to FIG. The signal Rf, which is a frequency component, is
They are sequentially input in synchronization with a clock having a period of 1 / S. The first data f0 determines the amplitude level of carrier 0, which is a DC component. The second data f1 has a period of 1024 /
The amplitude level of carrier 1 of S is determined, and the third data f2 determines the amplitude level of carrier 2 of period 512 / S. The highest frequency component thus input is I
The highest frequency of the time waveform created by the FFT transform,
That is, the bandwidth is determined. In addition, the respective carriers that have been converted and created with their individual amplitudes determined in this way are added up to generate a time waveform signal R. However, this time waveform signal R is composed of data of a total of 1024 samples, and each sample data has a period of 1 / S
The clock is output in synchronization with the clock. That is, carrier 1
Is 1024 times the input clock cycle.

[0012]

When the transmission bandwidth is changed in the transmission apparatus of the conventional configuration described above,
The following parts need to be changed. 1) N / G characteristics of the PLL / VCO 1-4 of the rate conversion unit 1 on the transmission side due to the change of the transmission capacity. 2) Control characteristics of the controller 2-5 for changing the period of 0 to be replaced in order to reduce the unnecessary carrier amplitude to 0 in the encoding unit 2T on the transmission side. 3) In accordance with the band change, the synchronization insertion unit 5 on the transmission side
Data in ROMs 5-1 and 5-2 storing frequency patterns corresponding to SWEEP symbols. 4) The SWEEP symbol pattern stored in the internal memory of the SWEEP operation unit 4-2 of the synchronization detector 4 on the receiving side. 5) PLL / VCO characteristics of the rate reverse converter 7 on the receiving side. As described above, in the conventional transmission device, even if an attempt is made to change the transmission bandwidth, there are many parts that need to be changed on both the transmission side and the reception side, and the reception side does not follow the band variable processing performed on the transmission side. Therefore, the transmission bandwidth cannot be changed easily and instantaneously. An object of the present invention is to eliminate these drawbacks and to realize a transmission system capable of easily changing the bandwidth.

[0013]

According to the present invention, in order to achieve the above object, a clock rate supplied to each unit is changed on a transmission side, and a synchronization signal detected from a reception signal and a reception side clock are separated on a reception side. The phase of the frame signal is compared with the phase of the frame signal generated by the clock, and the clock frequency of the receiving clock oscillator is controlled based on the result, and the band to be demodulated on the receiving side is automatically made to follow the band on the transmitting side so that the transmission band can be varied. It was done. That is, in the IFFT conversion on the transmission side,
The n-th data fn has a period 102 of the n-th carrier.
Determine the amplitude level of 4 / (n · S). Where I
If the period of the clock supplied to the FFT conversion unit is changed, the frequency of the n-th carrier is also changed. The transmission bandwidth is determined by the highest frequency of the generated carrier. That is, the band can be varied by changing the clock cycle. Further, the symbol period is changed by changing the clock period, and the frame period determined by the number of symbols is also changed. On the receiving side, the period of the NULL symbol and the SWEEP symbol detected from the received signal, that is, the frame period of the transmitting side is compared with the FSTr period determined by the frame counter, and the receiving side clock is adjusted so as to eliminate the difference. Control the cycle of This makes it possible to construct a transmission system that automatically follows the band variable procedure performed on the transmission side.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An overall block configuration of an embodiment of a variable band transmission system according to the present invention will be described with reference to FIG.
On the transmitting side, a clock output terminal of the clock oscillator 11 is connected to the clock rate converter 10. A clock output terminal of the clock rate conversion unit 10 is connected to each clock terminal of the rate conversion unit 1, the encoding unit 2T, the IFFT unit 3A, the guard addition unit 3B, the synchronization symbol insertion unit 5, and the quadrature modulation processing unit 8. On the receiving side, the output VC of the synchronization detector 15 is connected to the terminal VC of the voltage controlled clock oscillator 12. Output FSTr of synchronization detector 15
Is connected to the FST terminal of the FFT unit 3C and the rate inverse conversion unit 7. Output CKr of voltage controlled clock oscillator 12
Is connected to the clock CK terminal of the FFT unit 3C, the rate inverse conversion unit 7, the quadrature demodulation processing unit 9, and the synchronization detector 15.

First, the band variable processing operation on the transmitting side will be described. When changing the transmission bandwidth, the clock rate conversion unit 10 converts the clock CK from the clock oscillator 11 into a clock having a rate corresponding to the bandwidth to be changed. That is, the clock rate converter 10 outputs the clock CKd at a rate that is (V / NR) times the rate of the clock CK. Here, the above-described frame period pulse FST output from the rate conversion unit 1 is:
For example, since the clock CKd is output every 1056 × 400 counts, the encoding unit 2T, IFF, which operates based on the clock CKd and the frame period pulse FST,
T section 3A, guard addition section 3B, synchronization symbol insertion section 5,
In the quadrature modulation processing unit 8, the sample rate is (V
/ NR) times the output data, respectively (NR / V)
Output will take twice as long. In the PLL / VCO 1-4 (FIG. 8) in the rate conversion unit 1, since the input clock rate is (V / NR) times, the clock CKm of the N / G ratio is also (V / NR) times. , The rate of the fetched data Din also becomes (V / NR) times. Here, for example, a case where (V / NR) is set to 1/2 will be described. In this case, in the IFFT section 3A, when the sample clock CKd becomes 1/2, each carrier interval becomes 1 /.
2 and the symbol period is doubled. At this time, since the number of carriers has not been changed, (V / NR) is １ ／.
In this example, the bandwidth is determined by the carrier interval × the number of carriers, and is halved. That is, the clock rate is set to (V
/ NR) times, the bandwidth can be changed to (V / NR) times.

Next, the band variable processing operation on the receiving side will be described. As described above, the synchronization detector 15 detects NULL from the input signals R'sg and I'sg.
A SWEEP symbol is searched based on the period, and the phase of the SWEEP symbol is compared with a coincidence pulse indicating the reception frame period, and the clock CK
Control the frequency of rc. Also, this clock CKrc is
For example, a frame cycle pulse FSTrc created by counting 1056 × 400 is output. Here, the FFT unit 3
C, the rate inverse converter 7 operates with the pulse FSTrc and the clock CKrc. Therefore, when the sample rate on the transmission side is multiplied by V / NR, the matching pulse that is a phase comparison reference with the FSTrc pulse is NR Since the period of the clock CKrc is changed to the frequency of V / NR times the normal time, the period and the phase of the FSTrc pulse coincide with the period of the coincidence pulse.

FIG. 2 shows a specific configuration of the synchronization detector 15 and will be described. The input signals R'sg and I'sg are N
UL end detector 15-1 and SWEEP operation unit 15-2
Is input to The SWEEP period flag pulse output from the NULL end detector 15-1 is output from the SWEEP operation unit 1
It is input to the ST terminal 5-2. NULL end detector 1
The clock CKrc is input to the CK terminals of the 5-1, the SWEEP operation unit 15-2, and the frame counter 15-4. The coincidence pulse output from the SWEEP operation unit 4-2 is input to the R terminal of the PLL 15-3. The output FSTrc of the frame counter 15-4 for counting 1056 × 400 clocks CKrc is provided by the circuit at the subsequent stage and the PLL1.
It is input to the V terminal of 5-3. The PLL 15-3 outputs a signal VC whose voltage changes in accordance with the phases of the pulses input to the V terminal and the R terminal, respectively. The voltage-controlled clock oscillator 12 generates the clock CKrc to be output in accordance with the level of the voltage of the signal VC applied from the synchronization detector 15, that is, in response to the clock rate conversion of the clock CKd on the transmission side. Increase or decrease the frequency. By the processing described above, the clock CKrc used on the receiving side
And the frame cycle pulse FSTrc can be made to follow the clock CKd and the frame cycle pulse FST changed on the transmission side.

Next, FIG. 3 shows a block configuration of a band variable transmission system according to a second embodiment of the present invention, and a description will be given focusing on parts different from FIG. The output clock CKrc of the clock oscillator 16 on the receiving side is input to the clock rate converter 17. The output clock CKrc of the clock rate converter 17 is connected to the CK terminals of the FFT unit 3C, the rate reverse converter 7, and the data check unit 18. An FSTrc pulse of the synchronization detector 15 is input to an FST terminal of the data confirmation unit 18, and an output D'o of the decoding unit 2R is input to a D terminal. As described above, the transmission bandwidth on the transmitting side is set to V / N
In the case of R (for example, 1/2), the carrier interval is V / NR because the number of carriers is not changed. Here, when the FFT conversion operation is performed at the original clock rate on the receiving side, that is, when the FFT conversion is performed with the carrier interval being 1, the output D′ o obtained from the decoding unit 2R is The tooth missing state becomes "0" every other line. On the other hand, the clock rate of the transmitting side is one time, and
When operating at a clock rate of / NR times, the decoding unit 2R
The output D'o obtained from the above is in a state where there is no data of the carrier with the higher frequency. Therefore, the state of the output D'o is checked by the data check unit 18 to check the change state of the clock rate on the transmitting side.

The data confirmation unit 18 controls the clock rate conversion unit 17 to change the clock rate so that the clock rate on the reception side becomes the clock rate corresponding to the clock rate change on the transmission side. Is output. Thereby, the clock rate converter 1
Reference numeral 7 denotes a clock CKrc on the receiving side,
8, the clock rate is changed to a clock rate corresponding to the clock rate change on the transmission side. Here, by making the clock rate conversion on the transmission side simple 1/2 times, 1/3 times, or the like, erroneous detection is reduced in the confirmation operation of the data confirmation unit 18 on the reception side. With the configuration described above, the clock CK used on the receiving side
rc and the frame cycle pulse FSTrc can follow the clock CKd and the frame cycle pulse FST changed on the transmission side.

Next, FIG. 4 shows a block configuration of a third embodiment of the variable bandwidth transmission system according to the present invention. This is shown in FIG.
In this configuration, a rate conversion unit 17 and a data confirmation unit 18 are added to the configuration described above, and the description of the operation is omitted. Here, the clock rate conversion units 10 and 17 change the clock rate to ２ ，, ３ ，, 1/3 only by the frequency division operation by the logic element.
Only the function to change to 4 etc. This is a configuration mainly used when the frequency change width of the voltage-controlled clock oscillator 12 on the receiving side can be changed only in a narrow range.
Next, FIG. 5 shows a configuration of an automatic band variable transmission system to which the present invention is applied. The line state monitoring device 106 checks the radio wave use state of the line to be used, and determines the frequency to be used and the usable bandwidth according to the degree of vacancy.
S1 is output to the control terminal of the variable band modulation device 101. Also, the switching control signal S2 is output to the control terminal of the frequency conversion transmitting device 102. The band variable modulation device 101 and the frequency conversion transmission device 102 show the configuration of the transmission side in FIG. 1, FIG. 3, and FIG. 4 in large blocks, and the band variable modulation device 101 includes a rate conversion unit 1 to a synchronization symbol insertion. The frequency conversion transmitting device 102 corresponds to the quadrature modulation processing unit 8.
Corresponding to In each case, a function capable of switching control from the outside is added. The variable-bandwidth demodulator 104 sends the switching control signal S3 to the frequency conversion receiver 103 based on the demodulation state such as the presence or absence of a carrier. The frequency conversion receiving device 103 and the variable band demodulation device 104 are the same as those in FIG.
FIGS. 3 and 4 show the configuration on the receiving side in a block diagram. The frequency conversion receiving device 103 corresponds to the quadrature demodulation processing unit 9 and the variable band demodulation device 104 includes the FFT units 3C to 3C.
This corresponds to the rate reverse conversion unit 7 and the like.

Hereinafter, this operation will be described. First, prior to the start of transmission, the transmission side sets the line status monitoring device 106
Thus, the radio wave use state of the used line is checked, and the frequency to be used and the usable bandwidth are determined according to the availability of the line. Then, the bandwidth used by the switching control signal S1 is
The frequency to be used is designated by the switching control signal S2 to the band variable modulation device 101 and the frequency conversion transmission device 102, respectively. As a result, in the variable-bandwidth modulation apparatus 101, the clock rate is changed as described above so that the used bandwidth is obtained, and the bandwidth is used. In the frequency conversion transmitting apparatus 102, the frequency to be used is
The local oscillation frequency is controlled to be the frequency to be used. Then, the transmission signal having the used frequency and bandwidth is transmitted to the receiving side. On the receiving side, on the other hand, the band variable demodulation device 104 determines whether the carrier is in a state in which all carriers do not exist, a state in which only a part of the carriers exists, or a state in which a planned carrier is almost present. Switching control signal S3 to frequency conversion receiver 1
03 is output. In the frequency conversion receiving apparatus 103, the reception frequency is switched by the switching control signal S3, and the transmission signal from the transmission side can be received. By employing these configurations, it is possible to construct a system for automatically searching for a free channel and transmitting data with a transmission bandwidth corresponding to the free band.

FIG. 15 shows the relationship between the frame cycle time when the clock rate is increased by one and the frequency component at that time. FIG. 16 shows the relationship between the frame cycle time when the clock rate is increased and the frequency component at that time. As described above, if the clock rate is reduced to 1/2, the frame period is doubled, but the frequency band is 1
/ 2. Therefore, one channel (ch) in the case of FIG.
The minutes band can be used separately in the case of FIG. That is, in the transmission system shown in FIG. 5, the frequency conversion transmission device 102 and the frequency conversion reception device 103 that can change the transmission and reception frequencies in units of 1/2 channel are combined. Thereby, the band for one channel can be used for a plurality of transmissions, and the limited transmission band can be used effectively.

[0023]

As described above, according to the present invention,
By changing the clock rate on the transmitting side, the bandwidth can be changed, and the receiving side can realize a transmission system that automatically tracks the change.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a data transmission system according to the present invention.

FIG. 2 is a block diagram showing a configuration of a synchronization detector 15 used in the present invention.

FIG. 3 is a block diagram showing the overall configuration of another data transmission system of the present invention.

FIG. 4 is a block diagram showing the overall configuration of another data transmission system of the present invention.

FIG. 5 is a block diagram showing an overall configuration of an automatic band variable transmission system to which the present invention is applied;

FIG. 6 is a block diagram showing the overall configuration of a conventional data transmission system.

FIG. 7 is a waveform time chart and a frame configuration waveform diagram of each unit according to the present invention.

FIG. 8 is a block diagram showing a configuration of a rate conversion unit 1.

FIG. 9 is a block diagram showing a configuration of an encoding unit 2T.

FIG. 10 is a block diagram showing a configuration of an IFFT unit 3A.

FIG. 11 is a block diagram showing a configuration of a guard adding unit 3B.

FIG. 12 is a block diagram showing a configuration of a synchronization symbol insertion unit 5;

FIG. 13 is a block diagram showing a configuration of a synchronization detector 4.

FIG. 14 is a view for explaining the operation of the IFFT unit 3A.

FIG. 15 is a diagram showing a relationship between a frame cycle time and a frequency component when the clock rate is 1 time.

FIG. 16 is a diagram illustrating a relationship between a frame cycle time and a frequency component when the clock rate is increased.

[Explanation of symbols]

1: rate converter, 2T: encoder, 3A: IFFT
Section, 3B: guard addition section, 5: synchronization symbol insertion section, 3
C: FFT unit, 2R: decoding unit, 7: rate inverse conversion unit,
8: Quadrature modulation processing unit, 9: Quadrature demodulation processing unit, 10, 1
7: clock rate converter, 11, 12, 16: clock oscillator, 15: synchronization detector, 18: data checker, 1
5-1: NULL end detector, 15-2: SWEEP operation unit, 15-4: frame counter, 15-3: PL
L.

Claims (5)

[Claims] When a transmission band is changed in an orthogonal frequency division multiplexing modulation transmission apparatus,
The clock frequency supplied to the clock rate conversion unit, the encoding unit, the IFFT unit, the guard addition unit, the synchronization symbol insertion unit, and the quadrature modulation processing unit is changed according to the transmission band to be used. The phase of the generated synchronization signal is compared with that of the frame signal generated by dividing the clock on the receiving side. Based on the result, the clock frequency of the receiving clock oscillator is controlled, and the band to be demodulated on the receiving side is automatically set to the band on the transmitting side. A transmission band variable method of an orthogonal frequency division multiplex modulation method, characterized in that a transmission band is varied by following. 2. A transmission apparatus of an orthogonal frequency division multiplex modulation system, wherein a clock rate conversion unit provided in a transmission apparatus changes an output clock frequency of a clock oscillator on a transmission side, and converts the clock into a rate conversion unit and an encoding apparatus. Department, IFF
The signal is supplied to a T unit, a guard addition unit, a synchronization symbol insertion unit, and a quadrature modulation processing unit, and the receiving device compares the phase of a synchronization signal detected from the reception signal with a frame signal generated by dividing the reception clock, A transmission device of an orthogonal frequency division multiplex modulation system, wherein the frequency of a reception clock oscillator is controlled based on the result, and the band to be demodulated on the reception side is automatically made to follow the band on the transmission side to vary the transmission band. 3. The orthogonal frequency division multiplexing modulation method according to claim 2, further comprising means for detecting carrier loss based on the decoded signal and controlling a clock rate on a receiving side. Transmission equipment. 4. The transmission device according to claim 2, wherein
A transmission apparatus of an orthogonal frequency division multiplexing modulation method, further comprising means for controlling a frequency and a phase of a reception clock oscillator by comparing a detected synchronization signal of a received signal with a frame synchronization phase. 5. The transmission apparatus according to claim 2, wherein the modulation system used here is a QAM system.