JP4519371B2 - Transmission device, transmission device, and reception device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal configuration including a main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a bit pattern indicating setting information of the main data Dt, a transmission device, a transmission device, and a reception device.
[0002]
[Prior art]
In recent years, OFDM modulation has begun to be used as a modulation scheme for digital transmission. OFDM modulation is transmission using a large number of carriers, and has a carrier called TMCC that transmits auxiliary data in addition to main data.
[0003]
The main data is a video or audio signal, and is a transport stream (hereinafter referred to as TS) obtained by compressing the main data by MPEG processing. Several years ago, video and audio were transmitted by analog FM. In analog FM, the SN of video and audio changes depending on the received electric field level. In mobile transmissions such as marathons where the electric field level changes drastically, the relayed video is likely to be a low-quality signal with a lot of noise and disturbance. Digital transmission such as OFDM digitizes information and uses error correction processing together. Therefore, even when the received electric field level changes, the same quality video can be relayed and transmitted as long as error correction is possible.
[0004]
If the electric field level falls below the limit value, error correction becomes impossible and image transmission becomes impossible.
This limit value is in a contradictory relationship with the amount of data to be transmitted.
In the case of 64QAM, convolution correction 5/6 mode, which has a large transmission amount of 60 Mbps, the limit CN is about 22 dB, and the limit of the reception electric field is about −75 dBm or more. If the transmission amount is as small as 12 Mbps, QPSK and convolution correction 1/2 mode, the limit CN is about 6 dB, and the limit of the received electric field is about -89 dBm or more, so that video can be transmitted. When the transmission rate is low, the compression rate is increased by MPEG processing, resulting in a phenomenon that the image quality is lowered.
[0005]
The environment for video transmission varies depending on the transmission distance and whether it is moving or fixed. The user in use decides whether to place importance on the transmission amount or the transmission limit according to the transmission environment, and determines the setting mode.
[0006]
The digital FPU (Field Pickup Unit) has four types of modulation settings, for example, 64QAM, 32QAM, 16QAM, and QPSK in order to meet such a request. The convolution ratio related to the strength of error correction also has five types of correction settings such as none, 5/6, 3/4, 2/3, and 1/2.
[0007]
This mode must be set identically on the transmission side and the reception side.
Note that these settings on the transmission side can be automatically set on the reception side if sent to the reception side, and an operation for setting the demodulation mode one by one becomes unnecessary.
Auxiliary data for automatically setting this setting instead of manually is transmitted using a carrier called a TMCC carrier.
In all cases, since the information is related to the basic mode, BPSK modulation with high transmission tolerance is performed and transmitted.
The receiving side demodulates the TMCC carrier, obtains the main data setting mode, and sets the setting mode of the main data receiving unit. If this function is used, the mode state on the receiving side can be automatically changed and set only by changing the setting on the transmitting side.
[0008]
Reference materials describing the outline of 64QAM to QPSK, error correction, and the like include P32 to 36 of the Journal of the Institute of Image Information and Television Engineers (Vol.52 No11 1988).
[0009]
FIG. 6 shows a configuration of a transmission apparatus that performs transmission of a conventional video signal.
In the transmission apparatus on the transmission side, the video signal input is input to MPEG-ENC7M and becomes compressed data. This compressed data becomes the main data. Transmission state information such as a modulation mode is auxiliary data. Data which is main data is data Dts scrambled by the SCL unit 7.
[0010]
The SCL device 7 detects the code 47h existing in the 204W (word) cycle of Data by 47-DET, and the 1/8 device 7-2 detects the eighth time of 47h, and a pulse based on this position is detected. Send to the PN generator 7-4, reset, generate a specific pattern for SCL, perform scramble processing to invert the input Data with this specific pattern for SCL, Based on the output of 7-2, output data Dts is generated by replacing the eighth 47h with B8h. Since 1W is 8 bits, B8h exists every 13056 bits.
[0011]
The data Dts is input to the main data modulator 1, and is mapped to, for example, predetermined data to become transmission data Dt.
Setting data, which is a condition for creating the transmission data Dt, is input to the mode setting terminal of the main data modulator 1 and the TMCC generator 2. The main data modulator 1 performs a modulation operation according to the frame pulse from the TMCC generator 2. The output Dt modulated by the main data modulator 1 and the output TMCCt modulated by the TMCC generator 2 are combined by an integrator 3 that operates on the basis of a frame pulse, and then OFDM-modulated. The IFt signal is composed of 17 MHz multi-carrier.
[0012]
The IFt signal generated by the integrator 3 is sent to the transmission radio frequency generator 11t, frequency-converted to a microwave signal, and power amplified. The antenna 12t transmits the modulated wave as a radio wave.
[0013]
Then, the radio wave that has reached the receiving antenna 12r of the receiving device on the receiving side via a transmission path that is a space is input to the receiving high frequency device 11r. Then, the reception high-frequency device 11r amplifies a weak signal and converts it into an intermediate frequency signal IFr of 130 MHz band. This IFr is input to the separator 4.
[0014]
The IFr signal is separated and demodulated by the separator 4 into a main data component Dr and an auxiliary data component TMCCr. Each signal is input to the main data demodulator 5 and the TMCC regenerator 6. The TMCC regenerator 6 sends a frame pulse regenerated based on information extracted from the input data to the main data demodulator 5.
The separator 4 and the main data demodulator 5 perform demodulation based on the frame pulse.
[0015]
Further, various setting information extracted by the TMCC regenerator 6 is input to the mode setting terminal of the main data demodulator 5 and determines the conditions for creating Drs. The output Drs of the main data demodulator 5 is input to the inverse SCL unit 8. The inverse SCL unit 8 detects, for example, a B8h code present in a period of 13056 bits by the 8TS-DET unit 8-1, and sends a pulse generated based on this position to the PN generator 8-4 with reset. An SCL pattern is generated. The reverse SCL pattern signal is subjected to reverse rotation of the Drs signal in the reverse SCL calculator 8-3, and the reverse B8h on the transmission side is replaced with 47h in the 47h replacer 8-5 to restore the unscrambled Data. Then, the original data is restored by decompression with MPEG-DEC8M.
[0016]
Note that the reset PN generators 7-4 and 8-4 initialize a PN pattern generated when a reset is input. If no reset is input, the initialization is automatically performed after 13056 clocks.
[0017]
FIG. 7 shows the configuration of the main data modulator 1 of FIG.
The setting data is input to the time axis converter 1-1, the error correction code adder 1-2, and the encoder 1-3, and determines the operation mode of each unit.
[0018]
The time-axis converter 1-1 takes time to insert a time space for inserting parity information created in subsequent processing, added TMCC information, and CP information (synchronous continuous pilot signal) into the input Data signal. Axis conversion is performed. This operation is performed according to the clock signal from the clock oscillator 1-4 on the basis of the frame signal. It operates at a speed that is partially faster than the input speed in order to secure free time space.
[0019]
The error correction code adder 1-2 performs a calculation from the input data and creates and adds a parity signal.
This operation is performed according to the clock signal from the clock oscillator 1-4 on the basis of the frame signal. The parity signal is added to the time space vacated in the previous stage.
In consideration of the processing delay time of the time axis conversion process in the previous stage, the process is started after a predetermined time has elapsed after the input of the frame signal. Subsequent processing starts with the frame signal as a reference in consideration of the processing delay in the previous stage.
[0020]
The encoder 1-3 collects input data bits and maps them to the I axis and the Q axis in accordance with the modulation mode indicated by the setting data. In the 64QAM mode, the input 6 bits are grouped and converted to a signal corresponding to any of 8 × 8 64 points. This 6-bit summarization process is also performed based on the frame signal.
If the 16QAM mode is designated, 4 bits are collectively converted into a signal corresponding to any of 4 × 4 16 points.
The clock oscillator 1-4 gives a constant frequency CK for operation to each of the processors described above.
[0021]
FIG. 8 shows an example of a frame signal and TMCC signals t and Dt signals. Bits of a specific pattern for SYNC of about 16 bits are arranged at time t00, and setting data is arranged from t01 thereafter.
Here, it is assumed that the frame is composed of 204 symbols.
Bits of a specific pattern for SYNC are arranged again at t10 when the next frame is started, and setting information is arranged after t11. Thereafter, this is repeated unless the setting information is changed. Incidentally, the receiving side searches using the property that a specific code bit for SYNC periodically appears, and extracts subsequent setting information.
[0022]
FIG. 9 shows the configuration of the TMCC generator 2 of FIG.
A setting data signal from the outside is input to the setting information generator 2-2. The frame signal from the frame generator 2-5 is input to the MUX 2-6. Outputs from the SYNC generator 2-1 and the setting information generator 2-2 are input to the MUX 2-6.
The MUX 2-6 sequentially switches the input SYNC code and setting information in accordance with the input frame signal, and outputs TMCCt.
[0023]
FIG. 10 shows a configuration of the integrator 3 of FIG.
The SEL / CP inserter 3-1 uses the frame signal as a reference, the Dt signal as an input, the TMCCt signal as another input, and the CP signal that is a reference pilot generated by itself as a reference timing. select.
[0024]
The operation is shown in FIG. Since the Dt signal from the main data converter 1 has a time space for the TMCCt and CP signals, the TMCCt signal and the CP signal are selected and inserted in the empty period. As for the signal input to the IFFT unit 3-2 at the next stage, for example, a CP signal is inserted every 8 data, and the TMCCt signal is also assigned to a pre-specified free time space.
[0025]
Returning to FIG. 10, the operation of each unit will be described.
For example, the IFFT device 3-2 regards 1024 pieces of data as frequency components and creates a waveform for about 50 μs, thereby performing multicarrier modulation. The first input data determines the modulation of the lowest carrier, and the next input data determines the modulation of the second lowest frequency carrier. Thereafter, this is continued 1024 times. As a result, a waveform for about 50 μs time called one symbol is created and output.
This operation is also started based on the frame signal.
[0026]
The guard adder 3-3 arranges a waveform corresponding to 1/16 symbol period of the end portion of one symbol of the input signal in a time vacant space of the symbol signal, and creates a waveform of 17/16 symbol period. A part of 1/16 period of one symbol signal is output twice. This period is called a guard interval. This operation is also started based on the frame signal.
[0027]
The quadrature modulator 3-4 converts the input signal into a baseband analog signal by DA conversion, and frequency-converts it to the local frequency equivalent from the local oscillator 83.
[0028]
FIG. 12 shows a conceptual diagram of an OFDM modulated wave that is an output of the integrator 3 of FIG.
The image of all carriers is shown in the upper part of the figure.
It is composed of multiple carriers of multiple carriers.
The breakdown of carrier waves is a data carrier, the majority of which is shown in white, and is modulated based on Data information. When encoding is 64QAM, one carrier is determined by 6-bit information.
In addition, CP carriers for measuring the frequency deviation and phase amplitude deviation of the oscillator 83, which are indicated by shading, are inserted at regular intervals. Usually, it is modulated at a constant value.
Furthermore, there is a TMCC carrier for sending TMCC information indicated by oblique stripes. This is because 1-bit information is encoded by BPSK.
This carrier wave is changed to the following information every symbol period.
Note that these frequency arrangements are constant regardless of time.
[0029]
Here, since the CP carrier is modulated with a constant amplitude and phase, reverse correction of the phase amplitude for returning the deviation of the amplitude and phase to a predetermined constant value is performed on the correction unit 4 in FIG. 7, the amplitude and phase are close to the transmission state including the data carrier.
[0030]
Since the data carrier changes in amplitude and phase depending on the combination of encoded 6 bits, it is difficult to use it for distortion correction of the transmission path, and a CP carrier modulated with constant information is indispensable.
[0031]
FIG. 13 shows the configuration of the separator 4 of FIG.
The output of the reception high-frequency unit is input to the quadrature demodulator 4-1, converted into a baseband, and then converted into a digital signal. This output is input to the FFT unit 4-2, converted into a frequency component signal, and sequentially output from a low frequency component. Note that the conversion is performed based on the FSTrc pulse created based on the frame signal and CKrc.
[0032]
The synchronous regenerator 4-3 controls the frequency of the CKrc based on the phase difference between the frame signal and the self-generated FSTrc. In addition, FSTrc serving as an operation reference is supplied to each unit.
[0033]
The corrector 4-7 corrects the distortion generated in the transmission path for the signal of the entire band from the phase and amplitude of the input CP. In addition, the frequency and phase of the oscillator 93 in the quadrature demodulator 4-1 are controlled to remove distortion.
These operations are performed based on the FSTrc pulse created based on the frame signal and CKrc.
[0034]
The output of the corrector 4-7 is input to the Dr selector 4-5 and the TMCCr selector 4-6. The Dr selector 4-5 gates and outputs only the portion corresponding to Dr based on the FSTrc pulse generated based on the frame signal and CKrc.
The TMCCr selector 4-6 also operates based on the FSTrc pulse generated based on the frame signal and CKrc, and gates and outputs only the portion corresponding to TMCCr.
[0035]
FIG. 14 shows the configuration of the main data demodulator 5 of FIG.
The setting data is input to the decoder 5-1, the error corrector 5-2, and the time axis converter 5-3 to determine the operation mode of each unit.
[0036]
The decoder 5-1 identifies the transmitted data value based on the mapping point of the input data Dr. As for the presence or absence of the target signal, the processing timing is determined based on the FSTrc pulse created based on the frame signal and CKrc.
[0037]
The error corrector 5-2 performs error correction based on the parity information of the identified signal. This conversion is also performed on the basis of the FSTrc pulse created based on the frame signal and CKrc.
[0038]
The time axis converter 5-3 converts an error-corrected signal that exists intermittently into continuous data. This conversion is also performed on the basis of the FSTrc pulse created based on the frame signal and CKrc.
[0039]
FIG. 15 shows the TMCCr signal and Dr signal.
Since bits of a specific pattern for SYNC of about 16 bits are arranged from time t00 to t01, it is necessary to reach time t01 whether or not it matches the specific pattern. That is, a SYNC extraction signal indicating the presence of SYNC is generated around t01.
The break in the Dt (n) data exists at time t00 and is already a past thing at time t01. Therefore, the SYNC extraction signal generated at t01 is delayed until the time t10, and Dt (n + 1) is used as the starting point. Eventually, the break detected from TMCCr is used to specify the start point of the next frame with a delay of approximately one frame period. Therefore, even if the transmission state is normalized at a time just before t00, the data of Dt (n) cannot be demodulated normally and is not used.
[0040]
FIG. 16 shows the configuration of the TMCC regenerator 6 of FIG.
The input TMCCr is input to the SYNC detector 6-3 and the serial / parallel converter 6-1. The output of the SYNC detector 6-3 is input to the reset terminal of the frame counter 6-4 and the delay device 6-14. From the frame counter 6-4, a latch signal for capturing parallelized information at a predetermined timing is output. The setting information sent from the transmission side is captured by the latch 6-2 and output.
The delay device 6-14 delays the SYNC extraction signal by time t10-t01 (approximately one frame period) and outputs it as a frame signal.
[0041]
[Problems to be solved by the invention]
When modulation setting or correction setting of main data is performed, the bit arrangement of related information sometimes becomes the same pattern as the SYNC pattern. In this case, the TMCC regenerator on the receiving side erroneously detects a part of this setting information as a SYNC pattern code. Information of the same pattern as this SYNC is called a pseudo SYNC. Since the pseudo SYNC which is a part of the bit sequence of the related information is repeatedly generated in the frame period, it cannot be distinguished from the normal SYNC pattern code, and is erroneously detected and captured forever.
[0042]
An object of the present invention is to provide a signal configuration, a transmission device, a transmission device, and a reception device capable of preventing the acquisition of a pseudo SYNC.
[0043]
[Means for Solving the Problems]
In the TMCC having a signal structure in which a SYNC pattern indicating a header portion and a bit pattern indicating predetermined control information are repeated at a predetermined frame period, the bit pattern indicating the predetermined control information following the SYNC pattern is changed to the SYNC. A signal configuration is characterized in that a frame inversion signal of a predetermined bit whose polarity is inverted every frame is inserted and arranged at an interval shorter than the bit length of the pattern.
[0044]
The present invention relates to a transmitting apparatus for transmitting a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration that repeats a bit pattern indicating setting information of the main data Dt at a predetermined frame period. A TMCC in which a frame inversion signal of a predetermined bit whose polarity is inverted every frame is inserted and arranged in a bit pattern indicating setting information of the main data Dt following the SYNC pattern at an interval shorter than the bit length of the SYNC pattern. A transmission apparatus comprising a generating means.
[0045]
The present invention transmits a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration in which a bit pattern indicating setting information of the main data Dt is repeated at a predetermined frame period, by a transmission device, In a transmission apparatus that receives and reproduces data by a receiving apparatus, a predetermined bit whose polarity is inverted for each frame at an interval shorter than the bit length of the SYNC pattern is added to a bit pattern indicating setting information of the main data Dt following the SYNC pattern Means for generating a TMCC in which a frame inversion signal is inserted and arranged in the transmitter, and the receiver activates the SYNC pattern indicating the header portion when the SYNC pattern is continuously extracted from the received TMCC for a predetermined frame. A transmission apparatus comprising means for outputting.
[0046]
The present invention provides a receiving apparatus for receiving a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration that repeats a bit pattern indicating setting information of the main data Dt at a predetermined frame period. A signal configuration in which a frame inversion signal of a predetermined bit whose polarity is inverted every frame is inserted and arranged in a bit pattern indicating setting information of the main data Dt following the SYNC pattern at an interval shorter than the bit length of the SYNC pattern And a means for validating the SYNC pattern indicating the header portion when the SYNC pattern is continuously extracted from the received TMCC for a predetermined frame.
[0047]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 2 shows the overall configuration of the embodiment of the transmission apparatus of the present invention.
In FIG. 2, the same parts as those in FIG. The difference is that the TMCC generator of FIG. 6 is set to 2s and the TMCC demodulator is set to 6e.
[0048]
FIG. 1 shows TMCCt generated by the TMCC generator 2s of FIG. 2 in comparison with a frame and main data Dt. One frame consists of a SYNC pattern indicating the header portion, a bit pattern setting first half information, a frame inversion signal, a setting second half information, a frame inversion signal, and a fixed value a indicating the setting information of the main data Dt. It consists of an array. Here, the bit lengths of the first half setting information, the second setting half information, and the fixed value a are set to be smaller than the bit lengths of the codes constituting the SYNC pattern. Also, frame positive signals are arranged at two locations in one frame, and frame negative signals are arranged at two locations in the next frame. That is, a frame inversion signal whose polarity is inverted every frame is inserted and arranged in the setting information. These frame inversion signals are composed of data of 1 bit or more.
[0049]
In this manner, the portions other than the SYNC pattern in one frame are divided so that each becomes smaller than the bit length of the SYNC pattern, and a frame inversion signal is inserted and arranged between each of them. FIG. 1 shows an example in which a portion other than the SYNC pattern is divided into three, and two frame inversion signals are arranged therebetween.
[0050]
FIG. 3 shows a configuration of the TMCC generator 2s of FIG.
The setting data signal from the outside is input to the setting first half 1/2 information generator 2-2 and the setting latter half 2/2 information generator 2-4. The frame signal from the frame generator 2-5 is input to the MUX 2s-6. The MUX 2-6s includes a SYNC generator 2-1, a setting first half information generator 2-2, a frame inversion signal generator 2s-3, and a setting second half 2/2 information generator 2-4 for each frame. The output from is input.
[0051]
As shown in FIG. 4, the frame inversion signal generator 2s-3 generates a frame inversion signal that alternately outputs positive and negative for each frame. MUX2s-6 selects and outputs the frame inversion signal from t02 to t03 and from t04 to t05.
[0052]
When the setting information is changed, there is a possibility that the setting information matches the SYNC pattern code if the frame inversion signal is either positive or negative. However, even if it matches the SYNC pattern code in the frame period from t00 to t10, it does not match in the next frame period from t10 to t20. Therefore, if the SYNC pattern code is detected as coincidence detection when the SYNC pattern code is found in two consecutive frames, the phenomenon of continuing to catch the pseudo SYNC can be prevented.
[0053]
FIG. 5 shows the configuration of the TMCC regenerator 6s shown in FIG.
The input TMCCr is input to the SYNC detector 6-3 and the serial / parallel converter 6-1. The output of the SYNC detector 6-3 is input to the 1-frame delay device 6-5s, and the output of the 1-frame delay device 6-5s and the output of the SYNC detector 6-3 are input to the AND gate 6-6s. The output of the gate 6-6s is input to the frame counter 6-4s. Therefore, when a SYNC pattern code is found in two consecutive frames, the AND gate 6-6s outputs a coincidence detection output.
[0054]
【The invention's effect】
According to the present invention, it is possible to obtain a signal configuration, a transmission device, a transmission device, and a reception device that can prevent pseudo SYNC capture.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a signal configuration of the present invention.
FIG. 2 is a diagram showing an overall configuration of an embodiment of a transmission apparatus of the present invention.
FIG. 3 is a diagram showing a configuration of a TMCC generator of FIG. 2;
4 is a diagram illustrating the operation of FIG. 3. FIG.
FIG. 5 is a diagram showing a configuration of a TMCC regenerator in FIG. 2;
FIG. 6 is a diagram illustrating a configuration of a transmission apparatus that performs transmission of a conventional video signal.
7 is a diagram showing a configuration of the main data modulator of FIG. 6;
FIG. 8 is a diagram illustrating an example of a frame signal, a TMCCt signal, and a Dt signal.
FIG. 9 is a diagram showing a configuration of the TMCC generator of FIG. 6;
10 is a diagram showing a configuration of the integrator of FIG. 6. FIG.
FIG. 11 is a data diagram illustrating the operation of FIG. 10 and the like.
12 is a diagram showing a conceptual diagram of an OFDM modulated wave, which is an output of the integrator of FIG. 6. FIG.
13 is a diagram showing a configuration of the separator of FIG. 6. FIG.
14 is a diagram showing a configuration of a main data demodulator in FIG. 6;
FIG. 15 is a diagram illustrating a TMCCr signal and a Dr signal.
16 is a diagram showing a configuration of a TMCC regenerator 6 in FIG.
[Explanation of symbols]
1: main data modulator, 2: TMCC generator, 3: integrator, 4: separator, 5: main data demodulator, 6: TMCC regenerator, 7: SCL unit, 7M: MPEG-2 encoder, 8: Inverse SCL unit, 8M: MPEG-2 decoder, 11t: transmission high frequency unit, 12t: transmission antenna, 11r: reception high frequency unit, 12r: reception antenna, 1-1: time axis converter, 1-2: error correction code addition 1-3: Encoder 1-4: CK oscillator 2-1: SYNC generator 2-2: First half setting information generator 2-3: Frame inversion generator 2-4 : Setting latter half 2/2 information generator, 2-5: frame generator, 2-6: MUX, 3-1: SEL / CP inserter, 3-2: IFFT device, 3-3: guard adder, 3 -4: Quadrature modulation processor, 4-1: Quadrature demodulator, 4-2: FFT device, 4- : Synchronous regenerator, 4-4: voltage controlled CKr generator, 4-5: Dr selector, 4-6: TMCCr selector, 4-7: corrector, 5-1: decoder, 5-2: Error corrector, 5-3: time axis converter, 6-1: SP converter, 6-2: latch, 6-3: SYNC detector, 6-4: frame counter, 6-5: frame delay unit, 6-6: AND gate, 6-14: delay device, 7-1: 47h detector, 7-2: 8 frequency divider, 7-3: SCL calculator, 7-4: PN generator with reset, 7 -5: B8h replacement, 8-1: B8h detector, 8-3: Inverse SCL calculator, 8-4: PN generator with reset, 8-5: 47h replacement.

Claims (3)

  In a transmitting apparatus for transmitting a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration in which a bit pattern indicating setting information of the main data Dt is repeated at a predetermined frame period, Means for generating a TMCC in which a frame inversion signal of a predetermined bit whose polarity is inverted every frame is inserted and arranged in a bit pattern indicating setting information of the main data Dt at an interval shorter than the bit length of the SYNC pattern; A transmission apparatus comprising:   A transmission device transmits a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration in which a bit pattern indicating setting information of the main data Dt is repeated at a predetermined frame period, and is received by a reception device Then, in the transmission apparatus that reproduces, a bit inversion signal of a predetermined bit whose polarity is inverted every frame at an interval shorter than the bit length of the SYNC pattern, in a bit pattern indicating setting information of the main data Dt following the SYNC pattern Means for generating a TMCC in which the TC pattern is inserted and arranged in the transmitter, and when the receiver extracts the SYNC pattern for a predetermined frame from the received TMCC, the SYNC pattern indicating the header portion is output as valid. A transmission apparatus comprising:   In a receiving apparatus for receiving a transmission signal having main data Dt, a SYNC pattern indicating a header portion, and a TMCC having a signal configuration in which a bit pattern indicating setting information of the main data Dt is repeated at a predetermined frame period, A transmission signal having a signal configuration in which a frame inversion signal of a predetermined bit whose polarity is inverted every frame is inserted and arranged in the bit pattern indicating the setting information of the main data Dt at an interval shorter than the bit length of the SYNC pattern. A receiving apparatus comprising: means for validating a SYNC pattern indicating the header portion when receiving and extracting the SYNC pattern from the received TMCC in a predetermined frame continuously.

Images