JP5167170B2 - Transmitting apparatus, receiving apparatus and transmission system - Google Patents

Description

  The present invention multiplexes digital data having a synchronization pattern, adds control information including the synchronization pattern to the header, and transmits the bit stream of the frame to detect the synchronization pattern, establish synchronization, and control information and The present invention relates to technology for acquiring digital data.

  As a digital data transmission method, a transmission device multiplexes digital data having a synchronization pattern, adds control information including the synchronization pattern to the header, and transmits a bit stream of the frame. A technique is known in which synchronization patterns are detected to establish synchronization, and control information and digital data are acquired. In this method, if a bit pattern that is exactly the same as the synchronization pattern exists in the received bit stream, the receiving apparatus establishes synchronization at an incorrect position and cannot acquire digital data correctly. Hereinafter, establishing synchronization at an incorrect position is referred to as “pseudo-synchronization”. As techniques for preventing this pseudo-synchronization, for example, the following methods (1) backward protection, (2) dummy bit insertion, (3) Patent Document 1, and (4) Patent Document 2 are known.

(1) Backward protection This method prevents pseudo-synchronization by detecting a synchronization pattern at regular intervals from a bit stream of data having a synchronization pattern at regular intervals. When the data to be transmitted is composed of continuous fixed-length packets and the synchronization pattern exists at the same position in each packet, the interval between the synchronization patterns is constant. Therefore, the transmission device transmits data having a synchronization pattern at regular intervals. The receiving device detects a synchronization pattern from the received bit stream of data, and skips the received data bit stream by an interval of a preset synchronization pattern. Then, it is determined whether or not the synchronization pattern is detected at the skipped position. When the number of times that the synchronization pattern is detected at the skipped position becomes a certain number or more, synchronization is established at that position. This technique is generally called back protection.

(2) Insertion of dummy bits This technique prevents dummy synchronization by inserting dummy bits into the same bit pattern as the synchronization pattern and generating a bit pattern that does not match the synchronization pattern. When the transmission apparatus detects the same bit pattern as the synchronization pattern in the bit pattern of the data to be transmitted, the transmission apparatus inserts a dummy bit into the bit pattern and transmits it. For example, if the synchronization pattern is “11111111” (a pattern in which “1” is 8 bits continuous), the transmission apparatus detects a bit pattern in which “1” is continuously present in 8 bits in the bitstream. A dummy bit “0” is inserted immediately before the bit to generate “111111101” and transmit it. The receiving apparatus removes the dummy bits and restores the original bit pattern. Thus, by generating the bit pattern in which the dummy bits are inserted, the receiving apparatus does not detect a bit pattern that matches the synchronization pattern from the bit stream of the received data. Thereby, pseudo synchronization can be prevented. This technique is widely used in HDLC (High-Level Data Link Control) procedures, standards for image encoding international standards such as MPEG.

(3) Patent Document 1
This method prevents pseudo-synchronization by generating a synchronization pattern including a fixed pattern and a variation pattern having different bit configurations in successive packets. The transmission device generates a synchronization pattern by a combination of a fixed pattern and a plurality of types of variation patterns, adds the synchronization pattern to data, and transmits the data. By using the above-described circuit for backward protection (rear synchronization protection circuit), the reception device does not continuously detect the synchronization pattern at the wrong position, so that the probability of occurrence of pseudo synchronization can be reduced. it can.

(4) Patent Document 2
This technique combines error correction processing and synchronization pattern detection processing. The receiver calculates the number of error detection bits at the time of error correction decoding, calculates the Hamming distance between the synchronization pattern and the received bit stream, and estimates the correct synchronization position from the number of error detection bits and the Hamming distance It is. Thereby, the probability of occurrence of pseudo-synchronization can be reduced.

Japanese Patent No. 3783563 Japanese Patent No. 3386699

  However, the methods (1) to (4) described above have the following problems. In the method of (1), when the same bit pattern as the synchronization pattern exists in the bit stream of the data to be transmitted at the same interval as the interval of the preset synchronization pattern, the receiving apparatus detects the synchronization pattern at the wrong position. Are detected continuously, and pseudo-synchronization is established.

  In the method (3), by increasing the types of variation patterns and increasing the types of synchronization patterns, the above-described problem (1) can be solved and the probability of occurrence of pseudo synchronization can be reduced. However, in principle, the occurrence probability of pseudo synchronization cannot be reduced to zero.

  In the method (2), the probability of occurrence of pseudo-synchronization is zero, but the bit stream of data to be transmitted becomes redundant due to the insertion of dummy bits. In addition, when the data is composed of continuous fixed-length packets, the packet length varies by inserting dummy bits. For this reason, the transport stream (hereinafter referred to as “TS”) format specified in ISO / IEC (International Organization for Standardization) 13818-1 is fixed. It is difficult to apply to a system that presupposes transmission of long data.

  In the method (4), the error correction encoding process is essential in the transmission apparatus, and the error correction decoding process is essential in the reception apparatus. In addition, if the interval between the synchronization patterns becomes longer, the load of the error correction decoding process and the load of the correct synchronization position estimation process become very large, and the circuit scale increases.

  Therefore, the present invention has been made in view of the above problems, and its purpose is to establish synchronization when a bit stream is transmitted by adding a header storing control information to digital data having a synchronization pattern. An object of the present invention is to provide a transmission device, a reception device, and a transmission system that can reduce the probability of occurrence of pseudo-synchronization in a reception device including a backward synchronization protection circuit used for the purpose.

  In order to solve the above-mentioned problem, a transmitting apparatus according to the present invention multiplexes digital data including a synchronization pattern and stores the multiplexed data in a plurality of data slots, adds control information including the synchronization pattern to a header and stores the header in the header slot, In a transmission device that transmits a bit stream of a frame composed of the header slot and a plurality of data slots, it is determined whether the same bit pattern as the synchronization pattern exists in a position other than the synchronization pattern in the bit stream, When the same bit pattern exists, a bit inversion unit that inverts a predetermined bit in the bit pattern, and flag information indicating the inverted bit position are generated, and a header is generated by adding the flag information and generating a header And a section.

  The transmission apparatus according to the present invention may be configured such that the bit length of the synchronization pattern is P (P ≧ 2), the predetermined bit inverted by the bit inversion unit is the last bit in the bit pattern, and the synchronization pattern is removed. 1 bit indicating whether or not the inverted bit exists in the block, flag information generated by the header generation unit when the bit stream is divided into consecutive P-1 bit blocks This flag is information assigned to each block.

  Further, the transmission device according to the present invention is provided in the reception device that receives the bitstream when the bit inversion unit includes a plurality of bit patterns that are the same as the synchronization pattern at positions other than the synchronization pattern in the bitstream. In addition, a predetermined number of bit patterns are selected from the plurality of bit patterns according to the number of stages of the backward synchronization protection circuit that detects the synchronization pattern and establishes synchronization, and inverts the predetermined bits in the selected bit pattern It is characterized by that.

  Further, in the transmission device according to the present invention, when the bit inversion unit includes a plurality of bit patterns that are the same as the synchronization pattern in positions other than the synchronization pattern in the bit stream, the type of the synchronization pattern and the synchronization pattern According to a transmission cycle, a predetermined number of bit patterns are selected from the plurality of bit patterns, and predetermined bits in the selected bit pattern are inverted.

  Further, in the transmission device according to the present invention, when the bit inversion unit includes a plurality of bit patterns that are the same as the synchronization pattern in positions other than the synchronization pattern in the bit stream, the bit in the predetermined position from the bit patterns. A pattern is selected, and predetermined bits in the selected bit pattern are inverted.

  Further, in the transmission device according to the present invention, the header generation unit generates flag information indicating the inverted bit position in a predetermined frame, and the flag information is used as a header of a frame immediately after the predetermined frame. It is characterized by giving to.

  In the transmitter according to the present invention, when the bit inversion unit inverts the predetermined bit, at least all of the same bit pattern as the synchronization pattern in the digital data stored in the data slot immediately after the header slot. And the predetermined bit for all of the same bit pattern as the synchronization pattern in the digital data stored in the data slot immediately before the header slot is inverted, and the header generation unit performs the inverted bit position in the predetermined frame. Flag information is generated, and the flag information is added to a header of the predetermined frame.

  The transmitting apparatus according to the present invention multiplexes digital data including a synchronization pattern and stores the multiplexed data in a plurality of data slots, adds control information including the synchronization pattern to a header and stores the header in the header slot. In a transmitting apparatus that transmits a bit stream of a frame composed of data slots, a first interleave unit that performs interleaving in units of bytes with a predetermined interleave length on the bit stream, and byte-length data constituting the bit stream An address information generating unit for generating address information for specifying the byte-length data, and interleaving in units of bytes at the same timing and the same predetermined interleave length as the first interleave unit for the address information. Second interleaving And the bit pattern interleaved by the first interleaving unit in a position other than the synchronization pattern in the bit stream, it is determined whether the same bit pattern exists, and the same bit pattern exists, A bit inversion unit for inverting a predetermined bit in the bit pattern, and flag information reflecting address information interleaved by the second interleave unit, and generating flag information indicating the inverted bit position, And a header generation unit that generates a header by adding flag information.

  Further, in the transmission device according to the present invention, the header generation unit is flag information reflecting the address information interleaved by the second interleave unit, and indicates the inverted bit position in a predetermined frame. And the flag information is added to the header of a frame two frames after the predetermined frame.

  In the transmitting apparatus according to the present invention, the address information includes a frame number, a slot number in a header slot and a data slot constituting the frame, and a byte number in byte-length data constituting the slot. When the bit inversion unit inverts the predetermined bit, at least the addresses before and after the address information in which the flag information in the header exists among the address information interleaved by the second interleave unit For the information, in the digital data corresponding to the slot numbers constituting the address information, the predetermined bits for all the same bit patterns as the synchronization pattern are inverted, and the header generation unit performs interleaving by the second interleaving unit. Reflected address information A flag information, and generating flag information indicating the bit position the reversal in the predetermined frame, the flag information, is applied to a header of the predetermined frame, it is characterized.

  Also, the transmitting apparatus according to the present invention sets the bit length of the synchronization pattern to P (P ≧ 2), the flag information generated by the header generation unit, and the bit stream from which the synchronization pattern has been removed is continuous within the one frame. When dividing into blocks for each P-1 bit to be performed, a 1-bit flag indicating whether or not the inverted bit exists in the block is information assigned to each block in the one frame. It is characterized by.

  The receiving apparatus according to the present invention also inverts a predetermined bit within the same bit pattern as the synchronization pattern of digital data including a synchronization pattern, adds flag information indicating the inverted position to a header, and inverts the predetermined bit. The digital data after being multiplexed is stored in a plurality of data slots, the header with the flag information is stored in the header slot, and the bit stream of the frame including the header slot and the plurality of data slots is received. In the receiving device, a synchronization establishment unit that detects the synchronization pattern from the received bitstream and establishes synchronization, and a header stored in a header slot in the received bitstream after the synchronization is established From the included flag information, identify the inverted bit position, To serial received bit stream, characterized by comprising a bit restoration unit for restoring the original bits by inverting bits of the specified bit position.

  In addition, a transmission system according to the present invention includes the transmission device and the reception device.

  As described above, according to the present invention, when a bit stream is transmitted by adding a header storing control information to digital data having a synchronization pattern, a backward synchronization protection circuit used for establishing synchronization is provided. In the receiving apparatus, the probability that pseudo synchronization will occur can be reduced to zero.

1 is a diagram illustrating an overall configuration of a transmission system (cable television system) according to an embodiment of the present invention. 6 is a diagram illustrating an example of a TS that is retransmitted by the transmission apparatus according to the first embodiment. FIG. 6 is a diagram illustrating an example of a frame generated by the transmission apparatus according to the first embodiment. It is a figure which shows the structure of the header used for Example 1. FIG. 1 is a block diagram illustrating a configuration of a transmission device according to Embodiment 1. FIG. 1 is a block diagram illustrating a configuration of a receiving device according to Embodiment 1. FIG. 3 is a flowchart illustrating an outline of a processing procedure performed by the transmission apparatus according to the first embodiment. It is a figure explaining the example of a bit inversion process. It is a figure explaining the structural example of a header. It is a figure explaining the example of a bit inversion process in case a false synchronous pattern exists in a header. 3 is a flowchart illustrating an outline of a processing procedure performed by the receiving apparatus according to the first embodiment. It is a figure explaining the example of a bit restoration process. It is a figure explaining the bit inversion process in case of the protection stage number 5. FIG. It is a figure which shows the structure of the header at the time of making 2 slots into bit inversion object in 1 frame. It is a figure explaining the bit inversion process in case of the protection stage number 7. It is a figure which shows the structure of the header when 1 slot is made into the bit inversion object in 1 frame. It is a figure which shows the structure of the TSMF header used for a cable television system. It is a figure which shows the structure of the TSMF header used for Example 2. FIG. FIG. 10 is a block diagram illustrating a configuration of a transmission device according to a second embodiment. 6 is a block diagram illustrating a configuration of a receiving device according to Embodiment 2. FIG. (A) is a block diagram which shows the structure of an interleave part. (B) is a block diagram showing a configuration of a deinterleave unit. 10 is a flowchart illustrating an outline of a processing procedure performed by a transmission apparatus according to the second embodiment. It is a figure explaining the process by a transmitter. It is a figure explaining the example of the data before and behind interleaving, and address information. It is a figure explaining the example of the address information after interleaving. It is a figure explaining the structural example of a TSMF header. 10 is a flowchart illustrating an outline of a processing procedure performed by a receiving apparatus according to the second embodiment. It is a flowchart which shows the outline of the detection procedure of inversion bit information, and the production | generation of address information C. It is a flowchart which shows the outline of the production | generation procedure of temporary address information A and B. FIG. It is a figure explaining the example of the address information A before and behind deinterleaving. It is a flowchart which shows the outline of a bit restoration process procedure. It is a figure explaining the example of a bit restoration process.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.
[Transmission system]
First, a transmission system according to an embodiment (example) of the present invention will be described by taking a cable television system for retransmitting a digital broadcast as an example. In the following description, for convenience, data is expressed in hexadecimal when it is in bytes, and expressed in binary when it is in bits. When the data is expressed in hexadecimal, 0x is added to the head of the data. When the data is expressed in binary, the data is enclosed in “”.

  First, information transmitted by digital broadcasting will be described. Information such as video, audio, and data transmitted by digital broadcasting is the ISO / IEC (International Organization for Standardization) 13818-1 standard and the Radio Industry Association standard. This is an MPEG-2 transport stream defined by (ARIB STD-B32). The TS is composed of a plurality of TS packets, and the TS packet is a 188-byte fixed length packet. A packet synchronization pattern (0x47) used for packet synchronization is given to the first byte of the TS packet.

  Each TS packet is given a 16-bit ID called ts_id and network_id at a predetermined position, and a 13-bit ID called a PID (Packet IDentifier) is also given at a predetermined position according to the information to be transmitted.

  FIG. 1 is a diagram showing an overall configuration of a transmission system (cable television system) according to an embodiment of the present invention. The cable television transmission system 1 includes a transmission station 4 such as a radio tower or an artificial satellite, a head end (transmission device) 2 provided in the cable television facility, and a plurality of reception devices 3. The transmitting station 4 transmits the digital broadcast wave of each broadcasting station, and the transmitting device 2 receives the digital broadcast wave transmitted from the transmitting station 4 and demodulates it. Then, the transmission device 2 extracts digital data from the digital broadcast wave, generates a frame suitable for the cable television system, modulates the signal according to a modulation method different from transmission by radio waves, and retransmits the frame to the reception device 3.

  An example of a frame suitable for a cable television system is TSMF (Transport Stream Multiplexing Frame) recommended by ITU-T Rec. J.183 “Time division multiplexing of multiple MPEG-2 transport streams over cable television systems”. . As an example of a cable television system modulation scheme, there is a scheme recommended in Annex C of ITU-T Rec. J.83 “Digital multi-programme systems for television, sound and data services for cable distribution”. The modulation schemes recommended in TSMF and ITU-T Rec. J.83 Annex C will be described later.

[Transmitting device (head end) and receiving device]
The transmission apparatus 2 receives and demodulates digital broadcast waves of a plurality of broadcast stations transmitted from the transmission station 4, takes out a plurality of TSs corresponding to each of the plurality of digital broadcast waves, and transmits a frame payload according to the bit rate. Data slots are allocated, a plurality of TSs are time-division multiplexed and stored in the data slots, frame headers are added to generate a frame, a bit stream of the frame is modulated, and an RF signal is transmitted.

  The receiving device 3 receives and demodulates the RF signal transmitted by the transmitting device 2, and receives TS that transmits the program requested by the user as request information (information for identifying the TS requested by the user, For example, based on ts_id / original_network_id), the demodulated bitstream is separated from the frame. Specifically, the receiving device 3 detects the packet synchronization pattern from the demodulated bit stream to establish packet synchronization, and then detects the frame synchronization pattern attached to the frame header to establish frame synchronization. Then, with reference to ts_id / original_network_id assigned to the frame header, the TS transmitting the program requested by the user is taken out.

  In the first and second embodiments described below, there are two types of synchronization patterns: a packet synchronization pattern assigned to each TS packet and frame header, and a frame synchronization pattern assigned to the frame header. The receiving device 3 must establish both packet synchronization and frame synchronization. When it is necessary to establish packet synchronization before establishing frame synchronization, processing for establishing frame synchronization is required separately from processing for establishing packet synchronization. On the other hand, when it is possible to establish frame synchronization before establishing packet synchronization, packet synchronization is automatically established by the process of establishing frame synchronization. This is because the relative position of the packet synchronization pattern with respect to the frame synchronization pattern is known, so when the frame synchronization pattern is detected and the frame synchronization is established, the packet synchronization pattern is detected and the packet synchronization is established at the same time. Because it will be.

  In the following first and second embodiments, a technique for preventing pseudo synchronization in packet synchronization will be described. Further, regarding frame synchronization after packet synchronization is established, pseudo synchronization does not occur by some other means. That is, the transmission apparatus 2 inverts the last bit (LSB) of the same bit pattern as the packet synchronization pattern. Then, the information indicating the inverted bit position (inverted bit information) is converted into a flag, the flag is added to the header, and the RF signal of the frame is transmitted. On the other hand, after the reception device 3 receives the RF signal of the frame transmitted by the transmission device 2 and packet synchronization is established, the flag given to the header is converted into inverted bit information, and the inverted bit information is used. Then, the bit inverted by the transmission device 2 is returned to restore the original bit pattern. The present invention can be applied to either synchronization of packet synchronization and frame synchronization.

  Hereinafter, for convenience of explanation, information indicating the bit position inverted so that pseudo-synchronization does not occur is expressed as “inverted bit information”, and “inverted bit information” is expressed by one bit or a plurality of bits for storing in the header. Things are written as “flags”.

  As described above, the inverted bit information refers to information indicating a bit position obtained by inverting a predetermined bit of a bit pattern so that pseudo synchronization does not occur in packet synchronization. This inverted bit information is information on the number of each TS packet in the TS (each TS packet stored in the data slot constituting the frame) and the bit position counted from the next bit of the packet synchronization pattern (packet synchronization byte). And is represented by For example, when the 10th bit of the TS packet # 3 excluding the packet synchronization byte is inverted, the inverted bit information is “the 10th bit of the TS packet # 3 excluding the packet synchronization byte”. Details of the flag will be described later.

[Example 1]
First, Example 1 will be described. In the first embodiment, when the same bit pattern as the packet synchronization pattern exists at a position other than the first 1 byte of the header or at a position other than the first 1 byte of the TS packet, the LSB of the predetermined bit pattern is inverted, Information indicating the inverted bit position is added to the header after one frame.

  FIG. 2 is a diagram illustrating an example of a TS that is retransmitted by the transmission apparatus 2 according to the first embodiment. As shown in FIG. 2, the transmission apparatus 2 receives one TS composed of a plurality of TS packets having a length of 188 bytes, frames it, and retransmits it using one carrier wave. The head of the TS packet is a 1-byte long packet synchronization pattern 0x47.

  FIG. 3 is a diagram illustrating an example of a frame generated by the transmission apparatus 2 according to the first embodiment. This frame includes a header having a length of 188 bytes, which is the same as that of the TS packet, and six TS packets. A header in which a packet synchronization pattern 0x47 is added to the first byte is stored in a header slot, and a TS packet is stored in a data slot, thereby forming a frame. Here, in order to simplify the description, the number of TS packets in one frame is made smaller than the number specified by TSMF. In the first embodiment, error correction processing, interleave processing, and the like are not performed. 2 and 3, “TSP” represents a TS packet, and “# 1”, “# 2”, and the like represent a TS packet number and a header number.

(header)
Next, the header used in the first embodiment will be described. FIG. 4 is a diagram illustrating the configuration of the header. This header is a. Packet synchronization pattern (0x47), b. “000” + frame PID (0x002F), c. “0001” + continuity index, d. “000” + frame synchronization pattern, e. Flag, f. private_data, and g. It is configured by crc and has a value as control information allocated exclusively for the header. Here, in order to simplify the explanation, the header information is set to be smaller than the information defined by TSMF.

  a. The packet synchronization pattern (0x47) is the same as the packet synchronization pattern given to the first byte of the TS packet. d. The frame synchronization pattern of “000” + frame synchronization pattern is a 13-bit length value 0x1A86,0x0579, and is used alternately for each frame.

  e. The flag (underlined part in FIG. 4) is information indicating the bit position by 1 bit of “0” or “1” when the LSB of the same bit pattern as the packet synchronization pattern is inverted, and constitutes a frame 6 214 bits are assigned to each data slot. These 214 bits are obtained when 187 bytes (1496 bits) obtained by subtracting 1 byte of the packet synchronization pattern from the data length of 188 bytes of the TS packet stored in the data slot is divided into consecutive 7-bit blocks. , Corresponding to the number of blocks. That is, the 1st to 7th bits, the 8th to 14th bits,..., The 1478th to 1484th bits, the 1485th to 1491th bits, and the 1492 to 1496th bits for the 187 bytes excluding the first 1 byte of the TS packet. A 1-bit flag is assigned to each block. Since the number of blocks per TS packet is 214, the total number of flags per TS packet is 214 bits (the smallest integer Y that satisfies Y ≧ 1496/7). For the 1492-1496th bit block, a 1-bit flag is assigned to the 5-bit length. For example, in TS packet # 3, when the 10th bit excluding the leading packet synchronization byte is inverted, the inverted bit information is “the 10th bit of TS packet # 3 excluding the packet synchronization byte”. Since the 10th bit is included in the second block (8th to 14th bit blocks) of the data slot # 3 in which the TS packet # 3 is stored, the e. The flag is a flag of the second bit among the 214 bits in data slot # 3 (TSP # 3), and “1” is assigned to this flag. This flag (the flag of the second bit among the 214 bits in data slot # 3 (TSP # 3)) is “1” when the bit indicated by the inverted bit information is any of the 8th to 14th bits. Is granted. In general, when the inverted bit information is “the Wth bit of TS packet #n excluding the packet synchronization byte”, if V is the smallest integer that satisfies V ≧ W / 7, e. As the flag, “1” is given to the flag of the V-th bit of 214 bits in data slot #n (TSP # n).

(Configuration of transmitter)
Next, the transmission device 2 in the first embodiment will be described. FIG. 5 is a block diagram illustrating a configuration of the transmission device 2 according to the first embodiment. The transmission device 2-1 includes a header generation unit 21, a header insertion unit 22, a bit inversion unit 23, and a transmission unit 24.

  When the transmission apparatus 2-1 receives and demodulates the digital broadcast wave including the TS from the transmission station 4, and extracts the TS, the header insertion unit 22 inputs the TS. The header insertion unit 22 inputs a header from the header generation unit 21 and inserts the header into the TS to form a frame. Specifically, the header is stored in the header slot of the frame, and six TS packets among the plurality of TS packets constituting the TS are stored in the six data slots, respectively. The frame configured by the header insertion unit 22 in this way is output to the bit inversion unit 23.

  The bit inversion unit 23 receives the frame from the header insertion unit 22 and, for the TS packet stored in the data slot of the frame, except for the position where the original packet synchronization pattern exists, the same bit pattern ( Hereinafter, it is determined whether or not “false synchronization pattern” exists. If the bit inverting unit 23 determines that there is a false synchronization pattern, the bit inverting unit 23 allows some false false of the multiple false synchronization patterns within the range allowed by the number of stages of the backward synchronization protection circuit included in the receiving device 3. A synchronization pattern is selected, and predetermined bits in the selected synchronization pattern are inverted. For example, when the number of stages of the backward synchronization protection circuit is 5, and there are five false synchronization patterns continuously in one packet cycle, one false synchronization pattern is selected and LSB is inverted. Note that the predetermined bit of the false synchronization pattern in the header is not inverted. The bit pattern of the frame including the inverted bit is output to the transmission unit 24.

  Further, the bit inversion unit 23 generates inverted bit information regarding the inverted bit position. For example, when the bit inverting unit 23 inverts the 10th bit excluding the packet synchronization byte of the TS packet # 3, the bit inverting unit 23 generates the inverted bit information of “the 10th bit of the TS packet # 3 excluding the packet synchronization byte”. The inverted bit information generated by the bit inverting unit 23 in this way is output to the header generating unit 21.

  The header generation unit 21 receives the inverted bit information from the bit inverting unit 23, converts the inverted bit information into a flag, and assigns the flag to the header after one frame. Moreover, the header production | generation part 21 produces | generates a header by providing other control information to a header. The header generated in this way is output to the header insertion unit 22.

  The transmission unit 24 receives the bit stream from the bit inverting unit 23, modulates the bit stream into a signal suitable for the retransmission transmission path, and transmits the RF signal.

(Receiver configuration)
Next, the receiving device 3 in the first embodiment will be described. FIG. 6 is a block diagram illustrating a configuration of the receiving device 3 according to the first embodiment. The reception device 3-1 includes a reception unit 31, a packet synchronization establishment unit 32, an inverted bit information detection unit 33, a bit restoration unit 34, and a header removal unit 35.

  When the receiving device 3-1 receives the RF signal from the transmitting device 2-1, the receiving unit 31 receives the RF signal and demodulates it to generate a bit stream. The bit stream generated by the reception unit 31 is output to the packet synchronization establishment unit 32, the inverted bit information detection unit 33, and the bit restoration unit 34.

  The packet synchronization establishment unit 32 inputs a bit stream from the reception unit 31, and the packet synchronization pattern (0x47) in the bit stream is set in advance with a 1504 (= 188 × 8) bit period (one packet period). It is determined whether or not it has been detected continuously for the number of times (the number of stages of the backward synchronization protection circuit). When the packet synchronization establishment unit 32 determines that the preset number of times has been continuously detected, the packet synchronization establishment unit 32 determines that the packet synchronization has been established, and provides information indicating the position of the detected packet synchronization pattern (packet synchronization position information). Generate. The packet synchronization position information generated by the packet synchronization establishment unit 32 in this way is output to the inverted bit information detection unit 33 and the bit restoration unit 34.

  The inverted bit information detection unit 33 inputs a bit stream from the reception unit 31 and also receives packet synchronization position information from the packet synchronization establishment unit 32. Then, the inverted bit information detection unit 33 detects the frame synchronization pattern (0x1A86, 0x0579) in the header in the input bit stream according to the timing of the input packet synchronization position information, and establishes frame synchronization. And the inversion bit information detection part 33 detects inversion bit information by acquiring the flag in a header and converting the acquired flag into inversion bit information. The inverted bit information detected by the inverted bit information detection unit 33 in this manner is output to the bit restoration unit 34.

  The bit restoration unit 34 receives a bit stream from the reception unit 31, packet synchronization position information from the packet synchronization establishment unit 32, and inverted bit information from the inverted bit information detection unit 33. Then, the bit restoration unit 34 establishes frame synchronization in the same manner as the inverted bit information detection unit 33. Then, the bit restoration unit 34 specifies the bit position indicated by the inverted bit information in the bit stream, inverts the bit at the specified bit position again, and restores the original bit. Specifically, the bit restoration unit 34 identifies a bit pattern including an LSB that may have been inverted in the input bit stream by determining a match with a bit pattern obtained by inverting the LSB of the packet synchronization pattern. To do. When the LSB of the specified bit pattern is included in the bit position indicated by the inverted bit information, the LSB is specified as a bit (inverted bit) inverted by the transmission device 2-1. Thereby, the inverted bit can be returned to the original bit. The bit stream whose bits have been restored by the bit restoration unit 34 in this manner is output to the header removal unit 35 as a frame.

  The header removing unit 35 receives the frame from the bit restoring unit 34, removes the header from the frame, takes out the TS, and outputs it.

(Operation)
Next, operations of the transmission device 2-1 and the reception device 3-1 in the first embodiment will be described. FIG. 7 is a flowchart illustrating an outline of a processing procedure performed by the transmission apparatus 2-1 according to the first embodiment. FIG. 8 is a diagram illustrating an example of bit inversion processing performed by the bit inversion unit 23 of the transmission apparatus 2-1. FIG. 9 is a diagram for explaining a configuration example of the header, and FIG. 10 is an example of bit inversion processing when a false synchronization pattern is present in the header by the bit inversion unit 23 of the transmission device 2-1. It is a figure explaining. FIG. 11 is a flowchart illustrating an outline of a processing procedure performed by the reception device 3-1 according to the first embodiment. FIG. 12 is a diagram illustrating an example of bit restoration processing performed by the bit restoration unit 34 of the reception device 3-1. It is.

  In the following description, the bit stream shown in FIG. 8 corresponds to the TS bit stream shown in FIG. 2, and TSPs # 1 to # 3 are shown. In FIG. 8, the order of bit streams to be transmitted is assumed to be from left to right as indicated by arrows in the transmission direction. For convenience, the LSB of byte data of every 8 bits in the bit stream is shown at the left end of the underline. The same applies to FIG. 9, FIG. 10, and FIG. Note that the receiving device 3-1 detects that packet synchronization is established when “0x47” is detected twice in succession in the bit stream at 1504 (= 188 × 8) bit period (one packet period). judge. That is, the number of stages of the backward synchronization protection circuit of the receiving device 3-1 is two.

(Transmission device processing)
First, a processing procedure performed by the transmission apparatus 2-1 according to the first embodiment will be described. As shown in FIG. 8, the first byte of TSP # 1 to # 3 is a packet synchronization pattern, which is “111100010” when LSB is written at the left end. The bit inverting unit 23 of the transmission device 2-1 scans bit by bit in the bit stream whether “111100010” exists in a position other than the header and in a position other than the first byte of each TS packet. Judgment.

  In FIG. 8, a false synchronization pattern “11110000” exists in the 11th to 18th bits of TSP # 2 and the 11th to 18th bits of TSP # 3. Here, when the packet synchronization establishment unit 32 of the reception device 3-1 starts processing from the second byte of TSP # 2, it erroneously determines this position as the packet synchronization position, and pseudo synchronization occurs. Become.

  Referring to FIG. 7, in bit inversion unit 23, a false synchronization pattern exists twice in succession in one packet period at a position other than the first byte of the header or a position other than the first byte of each TSP. It is determined whether or not (step S701). Here, when the false synchronization pattern does not exist twice continuously in one packet cycle in the bit stream, no pseudo synchronization occurs in the reception device 3-1. Therefore, the bit inversion unit 23 does not need to invert the bit. In the example of FIG. 8, the bit reversing unit 23 determines that a false synchronization pattern “11100010” exists in the 11th to 18th bits of TSP # 2, and then 1504 bits later (after one packet cycle). It is determined whether or not a fake synchronization pattern “11100010” exists in the 11th to 18th bits of TSP # 3.

  If a false synchronization pattern exists twice in one packet cycle in the bitstream, pseudo synchronization occurs in the reception device 3-1. Therefore, the bit inverting unit 23 inverts the LSB of a predetermined false synchronization pattern among the plurality of false synchronization patterns (step S702). In the example of FIG. 8, the 18th bit which is the LSB of the false synchronization pattern of TSP # 3 is inverted. In this case, the bit inverting unit 23 inverts the LSB of the bit pattern of TSP # 2, TSP # 3, or both, that is, the 18th bit of TSP # 2, or the 18th bit of TSP # 3, or both. Good. Note that the LSB of the false synchronization pattern in the header is not reversed.

  The bit inverting unit 23 generates inverted bit information (step S703). In the example of FIG. 8, since the bit inversion unit 23 inverts the 18th bit of TSP # 3, it generates inverted bit information “10th bit of TSP # 3 excluding the packet synchronization byte”. When the LSB of the false synchronization pattern of TSP # 2 is inverted, the bit inverting unit 23 generates inverted bit information “10th bit of TSP # 2 excluding the packet synchronization byte”.

  Then, the bit inverting unit 23 scans bit by bit from the bit-inverted position in the bit stream to detect a false synchronization pattern, inverts the LSB, and sequentially performs a series of processes for generating inverted bit information. In the example of FIG. 8, the bit reversing unit 23 inverts the 18th bit of TSP # 3, thereby newly detecting a false synchronization pattern and determining its presence in the 18th to 25th bits of TSP # 3. To do. Next, a false synchronization pattern is detected at the 18th to 25th bits of TSP # 4 after 1504 bits (after one packet period), and the presence thereof is determined. If the bit inverting unit 23 determines that a false synchronization pattern exists twice consecutively, the bit inverting unit 23 inverts the 25th bit of TSP # 3, the 25th bit of TSP # 4, or both, Generate.

  As described above, even if a false synchronization pattern “11100010” newly exists due to the bit inversion process, by performing the same bit inversion process, the occurrence of pseudo synchronization in the reception device 3-1 is avoided. be able to.

  The header generator 21 receives the inverted bit information generated by the bit inverter 23 and converts the inverted bit information into a flag (step S704). In the example of FIG. 8, the header generation unit 21 receives the inverted bit information “10th bit of TSP # 3 excluding the packet synchronization byte” and generates a flag added to the header shown in FIG. 9. Specifically, the flags "0 ... 0", "0 ... 0", "0 ... 0", "0 ... 0010", "0 ... 0", "0 ... 0" are generated. To do. As shown in FIG. 4, 214 bits are allocated to each of the six data slots, and from the left, the flag for data slot # 6 (all 0) and the flag for data slot # 5 (all 0), respectively. , Data slot # 4 flag (all 0s), data slot # 3 flag (2nd bit is 1, otherwise 0), data slot # 2 flag (all 0), data slot # 1 flag ( All are 0).

  The flag corresponding to the 10th bit in the inverted bit information “10th bit of TSP # 3 excluding the packet synchronization byte” is the second block when divided into 7-bit blocks excluding the first byte of TSP # 3. Therefore, it is the second bit of 214 bits. That is, the header generation unit 21 assigns “1” to the second flag among 214-bit flags corresponding to data slot # 3 in which TSP # 3 is stored. Further, “0” is assigned to other flags.

  The header generation unit 21 generates the header by adding the flag converted in this manner to the header after one frame and adding other control information to the header (step S705). For example, if the header of a frame in which TSP # 1 to # 6 are stored in data slots # 1 to # 6 is header # 1, the flag corresponding to TSP # 1 to # 6 is set to header # 2 after one frame. Is granted. The processing procedure shown in FIG. 7 is an example, and the present invention is not limited to this processing procedure.

  On the other hand, even if a new false synchronization pattern exists in the header generated by such flag conversion processing, the bit inversion processing is sequentially performed in TS packets other than the header as described below. By performing the above, it is possible to avoid the occurrence of pseudo synchronization in the reception device 3-1.

  Referring to FIG. 10, it is assumed that there is a false synchronization pattern other than the first byte in the header. The bit inverting unit 23 determines that a false synchronization pattern exists in the 51st to 58th bits of TSP # 6, and false in the 51st to 58th bits of the header # 2 after 1504 bits (after one packet period). Is determined to exist. Then, the bit reversing unit 23 does not perform the bit reversing process on the header # 2, and inverts the LSB (that is, the 58th bit) in the false synchronization pattern of the 51st to 58th bits of TSP # 6. In this case, the bit reversing unit 23 does not perform the bit reversal processing on the headers of all the headers having a length of 188 bytes even if there is a false synchronization pattern other than the first byte. Then, the bit inverting unit 23 generates inverted bit information “50th bit of TSP # 6 excluding the packet synchronization byte”. Further, the header generation unit 21 uses the inverted bit information as the 8th bit of the 214 bits in the data slot # 6 (TSP # 6) corresponding to “the 50th bit of TSP # 6 excluding the packet synchronization byte”. By adding “1” to the flag, it is converted into a flag. In this case, assuming W = 50, V = 8 from 50/7 = 7.1. When a false synchronization pattern newly exists by the 58th bit inversion process of TSP # 6, the bit inversion unit 23 determines whether or not a false pattern exists in a 1504 bit period (one packet period). judge. On the other hand, pseudo-synchronization occurs when a false synchronization pattern exists in the 51st to 58th bits of TSP # 7 after 1504 bits of the false synchronization pattern of header # 2, and therefore 51 of TSP # 7. When a false synchronization pattern exists at the ˜58th bit, the 58th bit of TSP # 7 is inverted to generate inverted bit information “50th bit of TSP # 7 excluding the packet synchronization byte”.

  By such flag conversion processing, even if a false synchronization pattern newly exists in the header, by performing bit inversion processing on TS packets other than the header, pseudo synchronization in the receiving device 3-1 Occurrence can be avoided. Here, the reason why the bit inversion processing is not performed on the header is that the bit inversion processing is performed based on the flag given to the header. This is because not only the processing at −1 but also the restoration processing at the receiving device 3-1 becomes complicated. Therefore, by not performing the bit inversion process on the header, the processing load on the transmission device 2-1 and the reception device 3-1 can be reduced.

(Receiver processing)
Next, a processing procedure performed by the receiving device 3-1 according to the first embodiment will be described. The bit stream shown in FIG. 12 shows the bit stream shown in FIG. 8 that has been bit-inverted by the transmission apparatus 2-1.

  Referring to FIG. 11, the packet synchronization establishment unit 32 of the reception device 3-1 sets “0x47” twice in succession in a bit stream at a 1504 (= 188 × 8) bit period (one packet period). By detecting this, packet synchronization is established (step S1101).

  After establishing frame synchronization, the inverted bit information detection unit 33 acquires a flag in the header and converts the flag into inverted bit information to detect inverted bit information (step S1102). In the example of FIG. 12, header # 2 after one frame including the bit inversion information of TSP # 1 to # 6 is as shown in FIG. 9, and the flag of TSP # 3 (data slot # 3) is 2 bits. The eyes are “1” and the rest are “0”. When this flag is converted into inverted bit information, the inverted bit information becomes “8th to 14th bits of TSP # 3 excluding the packet synchronization byte”. Note that since the header # 2 is received after the TSPs # 1 to # 6, the receiving device 3-1 temporarily accumulates TS packets.

  The bit restoration unit 34 scans the bit stream bit by bit, and detects a bit pattern “01100010” in which only the LSB is different from the synchronization pattern (step S1103). Then, it is determined in which block the LSB of the detected bit pattern is included in 1496 bits excluding the packet synchronization byte divided into 7 bits. In the example of FIG. 12, “01100010” is present in the 11th to 18th bits and the 33th to 40th bits of TSP # 3, and the LSB is the 10th bit and 32th bit of TSP # 3 excluding the packet synchronization byte. Eyes. Therefore, these LSBs are included in the second and fifth blocks, respectively.

  Based on the inverted bit information, the bit restoration unit 34 determines whether or not the LSB that may have been inverted is actually an inverted bit, and identifies the inverted LSB (step S1104). Then, the identified LSB is inverted and restored to the original bit (step S1105). In the example of FIG. 12, the inverted bit information is “8th to 14th bits of TSP # 3 excluding the packet synchronization byte”, and this corresponds to the second block. Therefore, since the LSB of the 10th bit of TSP # 3 is included in the second block, the bit restoration unit 34 inverts the LSB and restores the original bit. On the other hand, the LSB of the 32nd bit of TSP # 3 corresponds to the fifth block, but since there is no inverted bit information “29th to 35th bits of TSP # 3 excluding the packet synchronization byte”, the LSB is transmitted. The device 2-1 determines that the bit is not inverted, and does not perform the inversion process.

  It should be noted that the bitstream detection process in which only the LSB differs from the synchronization pattern is not performed on the bitstream after the bit restoration process, but only on the original bitstream. The above description is intended for the bit stream shown in FIG. 8, but the same processing is performed when the bit stream shown in FIG. 10 is targeted. Further, the processing procedure shown in FIG. 11 is an example, and the present invention is not limited to this processing procedure.

[Rear synchronization protection circuit / When changing the bit-inverted TS packet]
In the example described above, the number of stages of the backward synchronization protection circuit is set to 2 in the reception device 3-1, but according to the protection stage number, e. The amount of flag information can be reduced. Hereinafter, in the case where the number of protection stages is 5, an example in which the TS packet to be bit-inverted is made variable in accordance with the continuous false synchronization pattern will be described. FIG. 13 is a diagram for explaining the bit inversion processing when the number of stages of the backward synchronization protection circuit is 5 in the reception device 3-1.

  When the number of stages of the back synchronization protection circuit of the reception device 3-1 is 5, in the reception device 3-1, up to four times, the false synchronization pattern that exists in a position other than the correct position is the same 1504 bit period ( Even if it exists in the bit stream in one packet cycle), pseudo synchronization does not occur. Therefore, the bit inverting unit 23 of the transmission device 2-1 bit-inverts a predetermined bit of the false synchronization pattern at least at a ratio of one TS packet among five TS packets continuous in one packet cycle. The remaining false sync patterns need not be inverted.

  In the example of FIG. 13, there are 8 consecutive false synchronization patterns in a 1504 bit period from the second packet TSP # 1 to the ninth packet TSP # 7 from the beginning of the frame. In this case, for example, the bit inversion unit 23 of the transmission device 2-1 performs bit inversion on a false synchronization pattern existing in the third TSP # 3 and the eighth TSP # 7. Also, for example, when there is a false synchronization pattern in five consecutive 1504 bit periods from TSP # 1 of the second packet to TSP # 5 of the sixth packet from the beginning of the frame, the bit inverting unit 23 Bit-invert the false sync pattern existing in the fifth TSP # 5. In this way, the number of false synchronization patterns detected in succession among the consecutively detected false synchronization patterns is set in advance so that no false synchronization pattern exists for 5 consecutive times. In accordance with the setting, a false synchronization pattern to be inverted is selected. As a result, the receiving device 3-1 does not receive five false synchronization patterns in succession, so that no pseudo synchronization occurs.

  Thus, the flag is not necessary for all TS packets (data slots). That is, the header flag shown in FIG. 4 requires 214 bits × 6 slots. However, information on all slots is not necessary as a flag, and information on some of the slots may be prepared. As shown in FIG. 14 to be described later, information indicating the slot number in the frame and flag information for the corresponding slot (TS packet) may be prepared in the header.

  FIG. 14 is a diagram illustrating a header configuration when the number of protection stages illustrated in FIG. 13 is five. This header is intended for bit inversion of two data slots in one frame. E.x of 214 × 6 = 1284 bits in the header shown in FIG. The flag is set to (3 + 214) × 2 = 434 bits long e. The slot number is replaced with a flag, and a 140-bit f. private_data is set to 990 bits long f. It is configured in place of private_data. Other information is the same as that shown in FIG. In the example of FIG. 13, there are six TS packets in one frame. Therefore, when the number of protection stages is 5, the maximum number of TS packets that require bit inversion is two in one frame. In response to this, the header shown in FIG. 14 prepares flags for two data slots.

  Thereby, the information amount of the flag can be reduced from 1284 (= 214 × 6) bits to 434 (= (3 + 214) × 2) bits as compared with the header shown in FIG. If the number of data slots in one frame is N and the number of protection stages is L, the number of packets in one frame that require bit inversion is given by the smallest integer M that satisfies N / L ≦ M. That is, the bit pattern bit-inverted by the bit inverting unit 23 is the number of data slots constituting one frame (data lengths in a plurality of data slots constituting one frame) or backward synchronization provided in the receiving device 3-2. It is selected according to the number of stages of the protection circuit. The bit pattern to be detected and to be inverted differs depending on the type of the packet synchronization pattern and the transmission cycle of the packet synchronization pattern, and the position of the bit pattern also differs depending on these. For example, the number of stages of the backward synchronization protection circuit is 3, there are two types of packet synchronization patterns A and B as packet synchronization patterns, and the transmission period is set to packet synchronization pattern B after transmitting packet synchronization pattern A seven times. It is assumed that the transmission is repeated once. In the receiving apparatus 3-2, when the packet synchronization pattern A is received three times in succession, when received in the order of packet synchronization patterns A, A, and B, when received in the order of packet synchronization patterns A, B, and A Alternatively, when packet synchronization patterns B, A, and A are received in this order, packet synchronization is established. Therefore, the bit inversion unit 23 does not have to perform bit inversion processing only for the false synchronization pattern of the packet synchronization pattern B, but also performs bit inversion processing for the false synchronization pattern of the packet synchronization pattern A. Need to do. Specifically, the bit inversion unit 23 performs bit inversion processing on the false synchronization patterns of the packet synchronization patterns A and B so that there is no false synchronization pattern in the above-described order of combination. As described above, the bit inverting unit 23 selects the bit pattern to be inverted according to the type of the packet synchronization pattern and the transmission cycle of the packet synchronization pattern.

[Rear synchronization protection circuit / When fixing bit-inverted TS packet]
Next, a case where a TS packet for bit inversion is fixed will be described. FIG. 15 is a diagram for explaining the bit inversion processing when the number of stages of the backward synchronization protection circuit is 7 in the receiving device 3-1.

  When the number of stages of the backward synchronization protection circuit of the reception device 3-1 is 7, in the reception device 3-1, the false synchronization pattern that exists in a position other than the correct position is the same 1504 bit period ( Even if it exists in the bit stream in one packet cycle), pseudo synchronization does not occur. Therefore, the bit inverting unit 23 of the transmission device 2-1 bit-inverts the false synchronization pattern at least at the ratio of one TS packet out of the seven TS packets continuous in one packet cycle, and the remaining The false synchronization pattern may not be reversed.

  In the example of FIG. 15, as in the example of FIG. 13, there are 8 consecutive false synchronization patterns from the second packet TSP # 1 to the ninth packet TSP # 7. In this case, the bit inverting unit 23 of the transmission device 2-1 sets in advance the bit synchronization inversion of the false synchronization pattern existing in the second TSP # 1, and inverts the bit of the false synchronization pattern. . As a result, the receiver 3-1 does not receive seven false synchronization patterns in succession, so that no pseudo synchronization occurs.

  In the transmission apparatus 2-1, a flag is not necessary for all TS packets (data slots). That is, the header flag shown in FIG. 4 requires 214 bits × 6 slots. However, when the number of stages of the backward synchronization protection circuit is 7, among the 6 TS packets stored in one frame, the false synchronization pattern in one TS packet (TSP # 1) at a fixed position is bit-inverted. In this example, not all flags are necessary. In such an example, a flag for the corresponding TS packet may be prepared in the header.

  FIG. 16 is a diagram illustrating a configuration of a header when the number of protection stages illustrated in FIG. 15 is seven. In this header, one fixed data slot in one frame is targeted for bit inversion, and e.x with 214 × 6 = 1284 bits in the header shown in FIG. Flag, e.g. 214 bits long. It is configured in place of the flag, and further, f. The private_data is set to f. It is configured in place of private_data. Other information is the same as that shown in FIG. In the example of FIG. 15, since there are 6 TS packets in one frame, when the number of protection stages is 7, there is one TS packet that requires bit inversion. In response to this, the header shown in FIG. 16 prepares a flag for one data slot.

  Thereby, the information amount of the flag can be reduced from 1284 (= 214 × 6) bits to 214 bits as compared with the header shown in FIG. Further, compared with the header shown in FIG. 14, the number can be further reduced from 434 bits to 214 bits.

  As described above, according to the first embodiment, in the transmission device 2-1 that multiplexes TS having a packet synchronization pattern of P bits (P ≧ 2) and adds a header to which control information is added, The inversion unit 23 inverts the LSB of the predetermined false synchronization pattern when the false synchronization pattern exists continuously for a predetermined number of times in one packet cycle in the TS packet. Also, the bit inverting unit 23 generates inverted bit information indicating the inverted bit position, and the header generating unit 21 converts the inverted bit information into a flag and adds it to the header. The transmission device 2-1 transmits the data including the inverted LSB and the header to which the flag is added to the reception device 3-1. As a result, the receiving device 3-1 does not continuously detect a false synchronization pattern for a predetermined number of times, and thus can establish packet synchronization at a correct position. Therefore, pseudo-synchronization does not occur, and the probability that pseudo-synchronization occurs can be reduced to zero.

  Also, according to the first embodiment, when the receiving unit 31 receives data and a header in the receiving device 3-1, after the packet synchronization establishing unit 32 establishes packet synchronization, the inverted bit information detecting unit 33 includes the header. The given flag is converted into inverted bit information. Also, the bit restoration unit 34 detects a bit pattern in which only the LSB is different from the synchronization pattern in the data, and when the LSB is included in the bit position indicated by the inverted bit information, the LSB is inverted to restore the original bit. Restored to. Thereby, after the packet synchronization is established, the bit inverted in the transmission device 2-1 can be restored to the original bit and restored.

[Example 2]
Next, Example 2 will be described. In the second embodiment, in a transmission system that performs interleaving and deinterleaving processing, the position of each byte in the header and data that fluctuates due to the rearrangement by the interleaving processing is reflected in the address information, except for the first 1 byte of the header. If a false synchronization pattern exists at a position other than the first byte of the TS packet, the LSB of the predetermined bit pattern is inverted, and information indicating the inverted bit position is generated based on the address information And added to the header after two frames.

(TSMF)
First, TSMF will be described. In the second embodiment, a transmission frame in the TSMF format is used in the cable television transmission system 1 shown in FIG. The transmission apparatus 2 multiplexes a plurality of received TSs in units of TS packets, generates a transmission frame in TSMF format, generates an RF signal using the ITU-T J.83 Annex C system as a modulation system, and receives the transmission apparatus Re-send to 3. The ITU-T J.83 Annex C method will be described later.

  In TSMF, a maximum of 15 independent TSs are time-division multiplexed in units of TS packets, and a header (TSMF header) having the same size of 188 bytes as the TS packet is added. When the transmission path coding method is the ITU-T J.83 Annex C method, the TSMF is a header slot in which a TSMF header of 1 slot length (188 bytes) is stored, and time-division multiplexed TS is in TS packet units. And a data slot stored as a TSMF payload having a length of 52 slots. The size of one data slot is 188 bytes, which is the same size as a TS packet. In TSMF, a 4-bit ID called a relative TS number is assigned to a TS to be transmitted, each TS can be distinguished by a relative TS number, and the maximum number of TSs that can be multiplexed is 15.

  Next, the TSMF header will be described. FIG. 17 is a diagram illustrating a configuration of a TSMF header used in a cable television system. This TSMF header is 188 bytes long in size, a. Packet synchronization pattern (0x47), b. “000” + multiple frame PID (0x002F), c. “0001” + continuity index, d. “000” + frame synchronization pattern (0x1A86 / 0x0579), e. Change instruction, slot allocation method, multiple frame format, f. Valid / invalid of table of g described later + “0”, g. table of ts_id / original_network_id, h. Reception state + “0” + emergency warning instruction, i. Table of relative TS numbers, j. private_data, k. It is constituted by crc.

  Where: a. The packet synchronization pattern (0x47) is the same as the packet synchronization pattern given to the first byte of the TS packet, and is control information assigned exclusively including b to k. g. The table of ts_id / original_network_id is a table associating the relative TS number assigned to each TS with ts_id / original_network_id. h. The reception state + “0” + emergency warning instruction is information for determining the reception state of each TS and whether or not emergency warning broadcasting is being performed. i. The table of relative TS numbers is a table associating the relative TS numbers with the numbers of the data slots in which the TSs of the relative TS numbers are stored. The frame synchronization pattern is 13-bit length control information given to the 36th to 48th bits from the head of the TSMF header, and the value is 0x1A86 or 0x0579, and is used alternately for each frame.

  In such a transmission system 1 that transmits TSMF, the transmission device 2 receives and demodulates a plurality of digital broadcast waves, extracts a plurality of TSs, assigns data slots of the TSMF payload according to the bit rate, A TS is time-division multiplexed and stored in a data slot, a TSMF header is added to generate a TSMF, a bit stream of the TSMF is modulated, and an RF signal is transmitted. The receiving device 3 receives and demodulates the RF signal transmitted from the transmitting device 2, detects the packet synchronization pattern in the TSMF, establishes packet synchronization, establishes frame synchronization by the frame synchronization pattern, and TSMF By referring to the table of ts_id / network_id given to the header and the table of relative TS numbers, TS packets in the data slot are correctly extracted. In this case, in the modulation scheme of ITU-T J.83 Annex C, the transmission rate of one channel excluding error correction codes is 29.162 Mbps, and when transmitting TSMF, the maximum bit rate of TS that can be transmitted in one channel is It is 28.611 Mbps (= 29.162 × 52/53).

(TSMF header)
Next, the TSMF header used in the second embodiment will be described. FIG. 18 is a diagram showing the structure of the TSMF header. In the second embodiment, it is assumed that the receiving device 3 monitors both 0xB8 and 0x47 packet synchronization patterns, and determines that packet synchronization has been established when a packet synchronization pattern is detected at a correct cycle 32 times in succession. To do. That is, the number of stages of the backward synchronization protection circuit is 32.

  The TSMF header shown in FIG. 18 is a header to which the second embodiment is applied, and a 680-bit length j.m. in the TSMF header shown in FIG. The private_data is j−1.x with a length of 232 bits × 2 slots = 464 bits. Flag, and j-2. It is configured in place of private_data. Other information is the same as that shown in FIG. This j-1. The flag is control information obtained by converting inverted bit information indicating the bit position of the LSB when the LSB of the false synchronization pattern is inverted, and 232 bits are assigned to each of the two fixed data slots. ing. In the modulation scheme of ITU-T J.83 Annex C, the period of the packet synchronization pattern is 204 bytes for RS (204, 188) encoding. The flag is 232 (= 203 × 8/7) bits per data slot because there is 1 bit per 7-bit data with respect to 203 bytes excluding the first byte (packet synchronization pattern) of the data slot. .

  When the receiving device 3 detects the packet synchronization pattern 32 times continuously with a 1632 (= 204 × 8) bit period, it establishes packet synchronization. Therefore, the transmitting device 2 is false at a rate of 1 or more per 32 times. It is sufficient to invert the sync pattern. As described with reference to FIGS. 15 and 16 of the first embodiment, the slot number information becomes unnecessary by fixing the data slot for bit inversion. Therefore, in the second embodiment, if the header slot is the first slot in the TSMF, the data stored in the 26th and 52nd slots is fixed as the bit inversion target, and the flags for these two slots are included in the TSMF header. Prepare. Therefore, j-1. The information amount of the flag is 232 × 2 = 464 bits. Since the false synchronization pattern is inverted once every 26 or 27 times, no pseudo synchronization occurs in the receiving device 3.

  As described above, in the second embodiment, as in the first embodiment, there are two types of synchronization patterns: a packet synchronization pattern present in each TS packet and a frame synchronization pattern present in the TSMF header. However, the RF signal of the bit stream transmitted from the transmission device 2 is interleaved in units of bytes. For this reason, in the receiving apparatus 3, frame synchronization cannot be established without demodulating the received RF signal to generate a bit stream and deinterleaving in units of bytes. Since packet synchronization must be established for deinterleaving, it is necessary to establish packet synchronization before establishing frame synchronization. In a second embodiment described below, a technique for preventing pseudo synchronization in packet synchronization will be described. As for frame synchronization, pseudo synchronization is not performed by some other means.

(Configuration of transmitter)
Next, the transmission device 2 according to the second embodiment will be described. FIG. 19 is a block diagram illustrating a configuration of the transmission apparatus 2 according to the second embodiment. The transmission apparatus 2-2 includes a header generation unit 41, a multiplexing unit 42, a packet synchronization byte conversion unit 43, an energy spreading unit 44, an RS encoding unit 45, interleave units 46 and 48, an address information generation unit 47, a bit inversion. A unit 49 and a transmission unit 50 are provided.

  When the transmitter 2-2 receives and demodulates the digital broadcast wave including X TS (X ≦ 15) TS transmitted from the transmitting station 4, and extracts the X TS, the multiplexing unit 42 receives the TS. (1) to TS (X) are input, and the TSMF header is input from the header generation unit 41. Then, the multiplexing unit 42 allocates data slots of the TSMF payload according to the bit rates of TS (1) to TS (X), respectively, and information on the number of slots allocated to each TS and the slot position allocated to each TS packet (slot Allocation information). The slot allocation information generated in this way is output to the header generation unit 41. Further, the multiplexing unit 42 time-division-multiplexes each TS and stores it in a predetermined data slot (allocated data slot) of the TSMF payload, and stores and adds a TSMF header in the header slot to generate TSMF. To do. The TSMF generated in this way is output to the packet synchronization byte conversion unit 43.

  The header generation unit 41 inputs the inverted bit information (information indicating the bit inversion position in the bit stream in the TSMF frame) described in the first embodiment from the bit inversion unit 49 and the slot allocation information from the multiplexing unit 42. To do. Then, the header generation unit 41 converts the inverted bit information into a flag, and assigns the converted flag to j−1 of the TSMF header. Also, the input slot allocation information is assigned to f, g, and i of the TSMF header, and other control information is also assigned to the TSMF header, thereby generating a TSMF header. The TSMF header generated in this way is output to the multiplexing unit 42. This TSMF header is added to the TSMF as a TSMF header after two frames in the multiplexing unit 42.

  The packet synchronization byte conversion unit 43 receives the TSMF from the multiplexing unit 42 and, according to the modulation scheme of ITU-T J.83 Annex C, the packet synchronization pattern (packet synchronization byte) of the TS packet stored in the data slot in the TSMF. ), A predetermined packet synchronization byte is converted. Specifically, the packet synchronization byte conversion unit 43 inverts all bits of the packet synchronization byte in the TS packet for every 8 TS packets, and converts the value of 0x47 into the value of 0xB8. The bit stream of TSMF having the packet synchronization byte converted in this way is output to the energy spreading unit 44.

  The energy spreading unit 44 receives the TSMF bit stream after the packet synchronization byte conversion from the packet synchronization byte conversion unit 43, and between the input bit stream and the PRBS code according to the modulation scheme of ITU-T J.83 Annex C. The energy is diffused by performing an XOR operation with. The bit stream that has been energy-spread in this way is output to the RS encoder 45. The PRBS code is initialized by the position of the inverted packet synchronization byte included in the input bit stream, and is generated by shifting the bit stream data stored in a shift register (not shown).

  The RS encoding unit 45 inputs the energy-diffused bitstream from the energy spreading unit 44, and performs Reed-Solomon (RS) (TS) on the TS packets in the bitstream according to the modulation scheme of ITU-T J.83 Annex C. 204, 188). The bit stream that has been subjected to error correction coding in this way is output to the interleave unit 46 and the address information generation unit 47. Here, the RS encoding unit 45 inputs 188-byte data per header slot and data slot, performs RS encoding, adds 16-byte parity data, and generates 204-byte data. Is output.

  The interleave unit 46 receives the RS-encoded bit stream from the RS encoder 45, and in accordance with the modulation scheme of ITU-T J.83 Annex C, the interleave length I is 12 bytes deep and is interleaved in units of bytes. I do. The bit stream interleaved in this way is output to the bit inverting unit 49.

  FIG. 21A is a block diagram showing a configuration of interleaving unit 46 shown in FIG. The interleave unit 46 includes a first switch for switching in units of bytes, 11 delay units each having a coefficient of 1 to 11, and data in units of bytes from the first switch and each delay unit. A second switch for switching is provided. The first switch performs switching in units of bytes for the input bit stream. Then, the 0th route for outputting the data for each byte as it is without performing the delay process, the delay unit for performing the first delay process, the delay unit for performing the second delay process,..., The eleventh delay Are output to each delay unit. Each delay unit outputs the input byte data after a predetermined delay process. The second switch receives data that has not been subjected to delay processing from the first switch and data that has been subjected to predetermined delay processing from each delay device, and performs switching in units of bytes. In this way, the bit stream output by the interleaving unit 46 shown in FIG. 21A is data that has been interleaved in units of bytes at a depth of the interleave length I = 12 bytes. The configuration shown in FIG. 21A is also applied to the interleave unit 48 shown in FIG.

  Returning to FIG. 19, the address information generation unit 47 inputs the bit stream that has been RS-encoded by the RS encoding unit 45, and the frame number, slot number, and byte for the data of each byte of the bit stream before interleaving. Generate and assign address information consisting of numbers. The address information generated in this way is output to the interleave unit 48.

  The interleave unit 48 inputs the address information from the address information generation unit 47, and in accordance with the modulation scheme of ITU-T J.83 Annex C, each element of the address information is converted at the same timing as the interleave for the bit stream in the interleave unit 46. Interleave. The interleaved address information is output to the bit inverting unit 49.

  The bit inversion unit 49 receives the interleaved bit stream from the interleave unit 46 and also receives the interleaved address information from the interleave unit 48. Then, the bit inversion unit 49 generates a false signal in the input interleaved bit stream other than the header slot (TSMF header) obtained from the address information and other than the position where the original packet synchronization pattern exists. It is determined whether or not a synchronization pattern exists. Here, the address information of the header slot (TSMF header) is all information having slot number = 1, and the address information in which the packet synchronization pattern exists is all information having byte number = 1. Therefore, based on these pieces of information, the position (region) of the bit pattern for determining whether or not a false synchronization pattern exists is determined.

  When the bit inverting unit 49 determines that a false synchronization pattern exists, the bit inverting unit 49 determines how many of the plurality of false synchronization patterns are within a range permitted by the number of stages of the backward synchronization protection circuit included in the reception device 3-2. The false synchronization pattern is selected, and a predetermined bit in the selected synchronization pattern is inverted. In the second embodiment, since the number of stages of the backward synchronization protection circuit is 32, when a false synchronization pattern exists 32 times continuously in a 1632 (= 204 × 8) bit period, one or more false Select a sync pattern and invert LSB. Further, for example, when the number of stages of the backward synchronization protection circuit is 5, and when a false synchronization pattern exists continuously 5 times in a 1632 (= 204 × 8) bit period, one or more false synchronization patterns among them exist. And invert LSB. The bit pattern of the frame including the inverted bit is output to the transmission unit 50. In the second embodiment, the false synchronization pattern to be selected is a false synchronization pattern in the slot number 26 or 52 counted from the header slot, as will be described later.

  In addition, the bit inversion unit 49 generates inverted bit information regarding the inverted bit position. For example, when the bit position where the LSB is inverted is the 10th bit excluding the packet synchronization byte of the TS packet # 3 (slot number 3) with reference to the address information, the bit inverting unit 49 sets the inverted bit information “ 10th bit of slot # 3 (TS packet # 3) excluding the packet synchronization byte ”is output. The inverted bit information generated by the bit inverting unit 49 in this way is output to the header generating unit 41.

  The transmission unit 50 receives the bit stream subjected to the bit inversion processing from the bit inversion unit 49, performs waveform mapping by symbol mapping and roll-off filter according to the modulation scheme of ITU-T J.83 Annex C, and performs frequency conversion. An RF signal is generated and transmitted.

(Receiver configuration)
Next, a receiving apparatus according to the second embodiment will be described. FIG. 20 is a block diagram illustrating a configuration of a receiving device according to the second embodiment. The receiving device 3-2 includes a receiving unit 51, a packet synchronization establishing unit 52, deinterleaving units 53, 59 and 61, RS decoding units 54 and 62, energy despreading units 55 and 63, and packet synchronization byte restoring units 56 and 64. , An inverted bit information detection unit 57, an address information generation unit 58, a bit restoration unit 60, and a separation unit 65.

  When the reception device 3-2 receives the RF signal from the transmission device 2-2, the reception unit 51 receives the RF signal, demodulates the RF signal according to the modulation scheme of ITU-T J.83 Annex C, and generates a bit stream. Is generated. Specifically, the receiving unit 51 performs frequency conversion and waveform shaping by a roll-off filter, and then converts symbols into bits to generate a bit stream. The bit stream generated in this way is output to the packet synchronization establishment unit 52, the deinterleave unit 53, the address information generation unit 58, and the bit restoration unit 60.

  The packet synchronization establishment unit 52 receives the bit stream from the reception unit 51, and sets the packet synchronization pattern (0xB8 and 0x47) in the bit stream for a preset number of times in a 1632 (= 204 × 8) bit cycle ( It is determined whether or not it has been continuously detected. If it is determined that the preset number of times has been continuously detected, it is determined that packet synchronization has been established, and packet synchronization position information is generated. The packet synchronization position information generated in this way is output to the deinterleave units 53 and 61, the address information generation unit 58, and the bit restoration unit 60.

  The deinterleaving unit 53 receives the bit stream from the receiving unit 51 and also receives the packet synchronization position information from the packet synchronization establishment unit 52, and the timing of the packet synchronization position information according to the modulation scheme of ITU-T J.83 Annex C. Thus, deinterleaving is performed in units of bytes with a deinterleaving length I = 12 bytes deep. The bit stream deinterleaved in this way is output to the RS decoding unit 54.

  FIG. 21B is a block diagram showing a configuration of deinterleaving section 53 shown in FIG. The deinterleaving unit 53 includes a first switch that performs byte unit switching, 11 delay units each having a coefficient of 11 to 1, and data in units of bytes from each delay unit and the first switch unit. The second switching device for switching is provided, and the reverse processing of the interleave unit 46 shown in FIG. In this way, the bit stream output by the deinterleave unit 53 shown in FIG. 21B is data that has been deinterleaved in units of bytes with a deinterleave length of I = 12 bytes. The configuration shown in FIG. 21B is also applied to the deinterleave units 59 and 61 shown in FIG.

  The RS decoding unit 54 receives the bit stream deinterleaved from the deinterleaving unit 53 and performs RS (204, 188) decoding according to the modulation scheme of ITU-T J.83 Annex C. The bit stream subjected to RS decoding in this way is output to the energy despreading unit 55. Here, the RS decoding unit 54 inputs data having a length of 204 bytes for each of the header slot and the data slot, performs RS decoding, generates data having a length of 188 bytes, and converts the data into 188 bytes of data. Byte length null data is added, and the same 204 byte data as the input data length is output.

  The energy despreading unit 55 receives a 204-byte bit stream from the RS decoding unit 54 and performs an XOR operation between the input bit stream and the PRBS code in accordance with the modulation scheme of ITU-T J.83 Annex C. By doing so, the energy is despread. The bit stream that has been despread in this way is output to the packet synchronization byte restoration unit 56. The PRBS code is initialized by the position of the inverted packet synchronization byte included in the input bit stream, and is generated by shifting the bit stream data stored in a shift register (not shown).

  The packet synchronization byte restoration unit 56 receives a 204-byte bit stream from the energy despreading unit 55 and inverts the packet synchronization byte of the TS packet in the bit stream according to the modulation scheme of ITU-T J.83 Annex C. The bit pattern 0xB8 is inverted and restored to the original packet synchronization byte 0x47. The bit stream having the packet synchronization byte restored in this way is output to the inverted bit information detection unit 57.

  The inverted bit information detection unit 57 receives a 204-byte bit stream from the packet synchronization byte restoration unit 56, detects a frame synchronization pattern (0x1A86, 0x0579) in the TSMF header in the bit stream, and establishes frame synchronization. Then, the inversion bit information detection unit 57 acquires the flag in the TSMF header and converts the flag into inversion bit information to detect the inversion bit information. Further, the inverted bit information detection unit 57 generates and assigns address information C including a frame number, a slot number, and a byte number to each byte of data in the TSMF. The inversion bit information detected in this way and the generated address information C are output to the bit restoration unit 60.

  The address information generation unit 58 receives the bit stream from the reception unit 51 and also receives the packet synchronization position information from the packet synchronization establishment unit 52. Then, the address information generation unit 58 generates temporary address information A composed of a temporary frame number, a temporary slot number, and a byte number for each byte data of the input bit stream according to the timing of the packet synchronization position information. And grant. The temporary address information A thus generated is output to the bit restoration unit 60.

  The deinterleaving unit 59 receives the provisional address information A from the address information generation unit 58, and at the same timing as the deinterleaving for the bit stream in the deinterleaving unit 53, according to the modulation scheme of ITU-T J.83 Annex C. The individual elements of the address information A are deinterleaved. The deinterleaved temporary address information B is output to the bit inverting unit 60.

  The bit restoration unit 60 receives the temporary address information A from the address information generation unit 58, the temporary address information B from the deinterleave unit 59, and the address information C and the inverted bit information from the inverted bit information detection unit 57, respectively. Then, the bit restoration unit 60 refers to the temporary address information A and B and the address information C based on the inverted bit information, and specifies the position of the inverted bit in the bit stream according to the timing of the packet synchronization position information. Then, the inverted bit is inverted again to restore the original bit. Here, since the order of the byte data in the input bit stream (bit stream before deinterleaving) is rearranged by the interleave unit 46 of the transmission device 2-2, inverted bit information (bit stream after deinterleaving) The bit position indicated by the inverted bit information corresponding to (1) cannot be applied to the bit stream as it is. Therefore, by referring to the temporary address information A and B and the address information C, the inverted bit information (inverted bit information corresponding to the bit stream after deinterleaving) and the bit stream (bit stream before deinterleaving) are associated with each other. Let

  Specifically, the bit restoration unit 60 specifies a bit pattern including an LSB that may be inverted in the input bit stream, and specifies the bit position of the LSB. Then, provisional address information α including the bit position of the LSB that may have been inverted is acquired from the provisional address information A. Then, the timing (position) at which the temporary address information α exists is detected from the temporary address information B obtained by deinterleaving the temporary address information A, and the address information β at the same timing is detected as the address. Obtained from information C. This address information β corresponds to the bit stream after deinterleaving. Therefore, when the bit position indicated by the inverted bit information includes the LSB of the bit pattern in the address information β, the bit restoration unit 60 specifies the LSB as the bit inverted by the transmission device 2-2. Specific examples will be described later. Thereby, the bit inverted by the transmission apparatus 2-2 can be returned to the original bit. The bit stream whose bits have been restored by the bit restoration unit 60 in this way is output to the deinterleaving unit 61.

  The deinterleaving unit 61 inputs the bit stream after the bit restoration from the bit restoration unit 60 and also receives the packet synchronization position information from the packet synchronization establishment unit 52, and performs the de-interleaving unit 61 according to the modulation scheme of ITU-T J.83 Annex C. Deinterleaving is performed at the same timing as deinterleaving for the bitstream in the interleaving unit 53. The bit stream deinterleaved in this way is output to the RS decoding unit 62.

  The RS decoding unit 62 inputs the bit stream after bit restoration from the deinterleave unit 61 and performs RS (204, 188) decoding according to the modulation scheme of ITU-T J.83 Annex C. The bit stream subjected to RS decoding in this way is output to the energy despreading unit 63. Here, the RS decoding unit 62 inputs 204-byte data per header slot and data slot, performs RS decoding, removes 16-byte parity data, and outputs 188-byte data each. To do.

  The energy despreading unit 63 receives the bit stream after bit restoration from the RS decoding unit 62, and performs an XOR operation between the input bit stream and the PRBS code according to the modulation scheme of ITU-T J.83 Annex C. By doing so, the energy is despread. The bit stream that has been despread in this way is output to the packet synchronization byte restoration unit 64. Similar to the energy despreading unit 55, the PRBS code is initialized at the position of the inverted packet synchronization byte included in the input bit stream, and the bit stream data stored in the shift register (not shown) is shifted. Is generated.

  The packet synchronization byte restoration unit 64 inputs the bit stream after the bit restoration from the energy despreading unit 63, and the packet synchronization byte of the TS packet in the bit stream is inverted according to the modulation scheme of ITU-T J.83 Annex C. The bit pattern 0xB8 is inverted and restored to the original packet synchronization byte 0x47. The bit stream having the packet synchronization byte restored in this way is output to the separation unit 65 as TSMF.

  The separation unit 65 receives the TSMF from the packet synchronization byte restoration unit 64, acquires slot allocation information with reference to the TSMF header, and outputs a desired TS by separating it from the TSMF based on the slot allocation information.

(Operation)
Next, operations of the transmission device 2-2 and the reception device 3-2 in the second embodiment will be described. Hereinafter, the operation of the transmission device 2-2 will be described with reference to FIGS. 22 to 26, and the operation of the reception device 3-2 will be described with reference to FIGS. FIG. 22 is a flowchart illustrating an outline of a processing procedure performed by the transmission device 2-2 according to the second embodiment. FIG. 23 is a diagram illustrating processing performed by the transmission device 2-2. FIG. 24 is a diagram illustrating an example of data and address information before and after interleaving. FIG. 25 is a diagram illustrating an example of address information after interleaving. FIG. 26 is a diagram illustrating a configuration example of a TSMF header. FIG. 27 is a flowchart illustrating an outline of a processing procedure performed by the receiving device 3-2 according to the second embodiment. FIG. 28 is a flowchart showing an outline (processing (1)) of a procedure for detecting inverted bit information and generating address information C. FIG. 29 is a flowchart showing an outline of the procedure for generating temporary address information A and B (processing (2)). FIG. 30 is a diagram illustrating an example of address information A and B before and after deinterleaving. FIG. 31 is a flowchart showing an outline of the bit restoration processing procedure (processing (3)). FIG. 32 is a diagram illustrating an example of the bit restoration process.

(Transmission device processing)
First, a processing procedure performed by the transmission apparatus 2-2 according to the second embodiment will be described. As shown in FIG. 23, the transmission apparatus 2-2 multiplexes X TS (1) to TS (X) and retransmits them. First, the multiplexing unit 42 of the transmission device 2-2 assigns and multiplexes the number of slots corresponding to the transmission speed to the X TS (1) to TS (X), adds a TSMF header, and adds a TSMF header. Is generated. Then, the packet synchronization byte conversion unit 43, the energy spreading unit 44, and the RS encoding unit 45 perform respective processes on the TSMF bit stream according to the modulation scheme of ITU-T J.83 Annex C.

  Referring to FIG. 22, address information generation unit 47 generates and assigns address information including a frame number, a slot number, and a byte number to each byte data of a bit stream processed by a predetermined modulation method. (Step S2201).

  In the example of FIG. 24, in the address information before interleaving, the byte number takes a value of 1 to 204, and the byte number of the packet synchronization byte is 1. The slot number takes a value from 1 to 53, and the slot number of the TSMF header is 1. The frame number takes a value from 1 to 256, increments when the slot number returns from 53 to 1, and is set to 1 after 256. The frame number, slot number, and byte number are each represented by 8 bits. For example, the address information of the first byte of data (1) in slot # 1 of frame # 4 is frame number 4, slot number 1, and byte number 1, and the second byte of data in slot # 1 of frame # 4. The address information of (2) is frame number 4, slot number 1, and byte number 2, and the address information of the data (3) of the third byte in slot # 1 of frame # 4 is frame number 4, slot number 1. , Byte number 3. As described above, the address information generation unit 47 generates and assigns each address information to the data of each byte of the bit stream.

  The interleaving unit 46 interleaves the bit stream processed by the predetermined modulation scheme, and the interleaving unit 48 interleaves the address information generated in step S2201 (step S2202). Address information is interleaved for each of frame number, slot number, and byte number information. In the example of FIG. 24, the interleaved address information is arranged in a sequence corresponding to the interleaved bit stream. By interleaving, for example, the address information of data (1 ') to (3') is arranged. Also, the address information consisting of frame number 4, slot number 1 and byte number 1 (address information of (1)) is immediately after the address information consisting of frame number 3, slot number 42 and byte number 204 by interleaving. Are rearranged to the position immediately before the address information consisting of frame number 3, slot number 53, and byte number 2.

  The bit inverting unit 49 generates a false synchronization pattern for the interleaved bit stream other than the header slot (TSMF header) obtained from the address information and other than the position where the original packet synchronization pattern exists. It is determined whether or not there are 32 consecutive times with a 1632 (= 204 × 8) bit period (step S2203). The reason why the number of times is 32 is that the number of stages of the backward synchronization protection circuit of the reception device 3-2 is 32. Here, when it is determined that the false synchronization pattern does not exist 32 times in succession, no pseudo synchronization occurs in the reception device 3-2, so that it is not necessary to invert the bits. Here, it is assumed that there are 32 or more false synchronization patterns continuously in a 1632-bit cycle in the interleaved bitstream. In the example of FIG. 23, it is assumed that in the bit stream after the interleaving, there are 41 consecutive false synchronization packets in the next byte of the packet synchronization byte, that is, the 9th to 16th bits. In this case, the LSB of the false synchronization pattern exists at the 8th bit in the byte next to the packet synchronization byte.

  The bit reversing unit 49 acquires the address information of the false synchronization pattern (step S2204). In the example of FIG. 23, the bit inversion unit 49 acquires address information in 41 false synchronization patterns. Referring to FIG. 24, among the 41 pieces of address information, the address information of the false synchronous address detected for the 40th time is frame number 3, slot number 52, and byte number 2. Also, the address information of the false synchronous address detected for the 39th time is frame number 3, slot number 51, and byte number 2. As shown in FIG. 25, when the address information after interleaving is viewed in a cycle of 204 bytes, it can be seen that the slot number is incremented by 1 with 53 as the maximum value (the number next to 53 is 1). Therefore, it can be seen that the address information of the false synchronization pattern detected continuously in a cycle of 204 bytes has a slot number incremented by one.

  Here, in order to prevent pseudo synchronization in the reception device 3-2, the bit inversion unit 49 needs to bit invert at least one LSB among the false synchronization patterns that are continuous 41 times in a cycle of 204 bytes. . Therefore, the bit inverting unit 49 specifies address information having a predetermined slot number from the address information acquired in step S2204, and specifies a false synchronization pattern indicated by the address information (step S2205). Then, the bit inversion unit 49 inverts the LSB of the specified false synchronization pattern (step S2206).

  In the example of FIGS. 23 and 24, the bit inversion unit 49 identifies address information having a slot number of 26 or 52 from the 41 pieces of acquired address information. Here, address information of frame number 3, slot number 52, and byte number 2 is specified. As described above, when the address information after interleaving is viewed at a cycle of 204 bytes, the slot number is incremented by one. Therefore, while continuously referencing 41 slot numbers, 26 or 52 or both There will be a slot number. That is, since the slot number range is from 1 to 53, there are always 26 or 52 slot numbers among the 32 consecutive slot numbers, and the 53 consecutive slot numbers are the maximum. Will always have both slot numbers 26 and 52. Therefore, by fixing the slot numbers for bit inversion to 26 and 52, no pseudo synchronization occurs in the receiving device 3-2.

  Then, the bit inversion unit 49 specifies a false synchronization pattern for the address information of the specified frame number 3, slot number 52, and byte number 2, and inverts the LSB. That is, the eighth bit is inverted in the bit pattern of frame number 3, slot number 52, and byte number 2.

  In the above example, the predetermined slot numbers are set to 26 and 52. However, the present invention is not limited to this number. If the slot numbers obtained by looping 1 to 53 are continuously counted, Thus, two slot numbers (for example, 25 and 51) that can be divided so that 32 slot numbers cannot be counted may be used as the predetermined slot numbers.

  The bit inverting unit 49 generates inverted bit information (step S2207). In the example of FIGS. 23 and 24, the bit inversion unit 49 inverts the LSBs of the frame number 3, the slot number 52, and the byte number 2, so that the inversion bit information “slot number 52 excluding the packet synchronization byte (TSP # 52) Of the 8th bit ".

  The header generation unit 41 converts the inverted bit information into a flag (step S2208), and adds the converted flag to the TSMF header after two frames, thereby generating a TSMF header (step S2209). In the example of FIGS. 23 and 24, the flag is attached to the TSMF header of frame number 5. If the header generation unit 41 gives a flag to the TSMF header after 2 frames if it is a TSMF header after 2 frames, even if a new false synchronization pattern appears due to the addition of the flag, This is because bit inversion processing can be performed sequentially. What is not added to the TSMF header after one frame is that the area for storing the flag in the TSMF header after one frame has already been subjected to processing such as interleaving, and when a false synchronous pattern appears, the detection and This is because it is difficult to sequentially perform the bit inversion processing.

  In the example of FIGS. 23 and 24, the TSMF header shown in FIG. 26 is generated. Since the inverted bit information is “the eighth bit of slot # 52 (TSP # 52) excluding the packet synchronization byte”, the flag of the 26th slot is “0... 0” as shown in FIG. The flag for the 52nd slot is “0... 10”.

  In steps S2206 to S2209, processing similar to that in steps S702 to S705 of the first embodiment is performed. Even if a false synchronization pattern is newly generated by such bit inversion processing or header generation processing to which a flag is added, reception is performed by sequentially detecting the false synchronization pattern and performing bit inversion processing, etc. Pseudo synchronization can be prevented in the device 3-2. The processing procedure shown in FIG. 22 is an example, and the present invention is not limited to this processing procedure.

(Receiver processing)
Next, a processing procedure performed by the receiving device 3-2 according to the second embodiment will be described. Referring to FIG. 27, after receiving section 51 of receiving apparatus 3-2 receives the RF signal and generates a bit stream, packet synchronization establishing section 52 includes 1632 (= 204 × 8) bits in the bit stream. The packet synchronization is established by detecting the packet synchronization pattern (0xB8 and 0x47) continuously 32 times in a cycle (step S2701).

  Then, the receiving device 3-2 performs the process (1) of step S2702, the process (2) of step S2703, and the process (3) of step S2704 according to the timing of the packet synchronization position information. Process (1) establishes frame synchronization with the de-interleaved bit stream, obtains a flag from the TSMF header, converts the flag into inverted bit information, detects the inverted bit information, and after de-interleaving This is a process of generating address information C for the bitstream. Process (2) is a process of generating temporary address information A before deinterleaving and a process of generating temporary address information B after deinterleaving. The process (3) refers to the tentative address information A, the tentative address information B, and the address information C based on the inverted bit information, thereby inverting the bits inverted in the transmission device 2-2. It is a process to restore bits.

  The receiving device 3-2 uses the deinterleaving unit 61, the RS decoding unit 62, the energy despreading unit 63, and the packet synchronization byte according to the timing of the packet synchronization position information with respect to the bit stream in which the inverted bits are restored as described above. The restoration unit 64 performs deinterleaving, RS decoding, energy despreading, and packet synchronization byte conversion, respectively, to generate a TSMF. Then, the separation unit 65 of the reception device 3-2 refers to the table of ts_id / network_id and the table of relative TS numbers in the TSMF header and separates and outputs the desired TS.

(Inverted bit information, address information C / processing (1))
Next, the process (1) shown in FIG. 27 will be described in detail. Process (1) is a process for acquiring a flag and detecting inverted bit information, and a process for generating address information C for the de-interleaved bit stream.

  Referring to FIG. 28, the reception device 3-2 performs deinterleaving, RS decoding, energy despreading, and the like on the bitstream subjected to bit inversion processing by the transmission device 2-2 without restoring the original bits. Perform packet synchronous byte recovery. Then, the inverted bit information detection unit 57 detects the frame synchronization pattern and establishes frame synchronization (step S2801). Here, since the bit inverted by the transmitter 2-2 does not exist in the TSMF header, the information in the TSMF header is correctly error-corrected in the RS decoding unit 54 and can be extracted in the inverted bit information detection unit 57. . Since data other than the TSMF header may be bit-inverted, the inverted bit is determined to be an error in the RS decoding unit 54.

  The inverted bit information detection unit 57 detects the inverted bit information by acquiring the flag given to the TSMF header after frame synchronization is established, and converting this flag into inverted bit information (step S2802). In the example of FIGS. 23 and 24, the TSMF header of frame number 99 is as shown in FIG. 26, the flags of the 26th slot are all “0”, and the flag of the 52nd slot is “1” in the second bit. And the rest is “0”. When this flag is converted into inverted bit information, the inverted bit information becomes “8th to 14th bits of slot # 52 (TSP # 52) excluding the packet synchronization byte”. Since the transmission device 2-2 adds a flag to the TSMF header after two frames, in the reception device 3-2, the flag acquired from a certain TSMF header is information about the data slot two frames before. Represents. That is, since the TSMF header with the frame number 99 is the header of the data slot with the frame number 97, the receiving device 3-2 temporarily accumulates the data stored in each data slot.

  After the frame synchronization is established, the inverted bit information detection unit 57 generates and assigns address information C including a frame number, a slot number, and a byte number to each byte data in the bit stream (step S2803). Here, the byte number takes a value from 1 to 204, and the byte number of the packet synchronization byte is 1. The slot number takes a value from 1 to 53, and the TSMF header is slot number 1. Here, since frame synchronization has already been established, the slot number of the TSMF header can be set to 1. The frame number takes a value from 1 to 256, increments when the slot number returns from 53 to 1, and is set to 1 after 256. The frame number, slot number, and byte number are each 8 bits long. Although this frame number may not match the frame number in the transmission apparatus 2-2, it does not necessarily need to match. As described above, the inversion bit information detection unit 57 detects the inversion bit information and generates the address information C.

(Temporary address information A, B / Process (2))
Next, the process (2) shown in FIG. 27 will be described in detail. Process (2) is a process of generating temporary address information A before deinterleaving and a process of generating temporary address information B after deinterleaving.

  Referring to FIG. 29, address information generation unit 58 uses the temporary frame number, temporary slot number, and byte number for each byte of data in the bit stream after establishment of packet synchronization (bit stream before deinterleaving). The temporary address information A is generated and assigned (step S2901). Here, the temporary byte number takes a value of 1 to 204, and the byte number of the packet synchronization byte is 1. The temporary slot number takes a value from 1 to 53, and is incremented when the temporary byte number returns from 204 to 1. The next 53 is 1. The temporary frame number takes a value of 1 to 256, and is incremented when the temporary slot number returns from 53 to 1, and is set to 1 after 256. The temporary frame number, temporary slot number, and byte number are each 8 bits long.

  In the example of FIG. 30, in the temporary address information A before deinterleaving, the temporary address information of the data (1) of the first byte of the temporary frame # 3 and the temporary slot # 43 is the temporary frame number 3, Temporary slot number 43, byte number 1, and address information of data (2) of the second byte of temporary frame # 3 and temporary slot # 43 are temporary frame number 3, temporary slot number 43, and byte. Number 2. As described above, the address information generation unit 58 generates and assigns each address information to the data of each byte of the bit stream after the packet synchronization.

  The deinterleaving unit 59 deinterleaves the temporary address information A at the same timing as the deinterleaving of the bit stream in the process (1), and generates the temporary address information B (step S2902). In this case, referring to FIG. 21B, one byte of data processed in deinterleaver 53 and temporary address information A corresponding to the one byte of data processed in deinterleaver 59 Are processed at the same timing and pass through the same path.

  In the example of FIG. 30, the temporary address information B after deinterleaving is an array corresponding to the deinterleaved bitstream. For example, temporary address information (temporary address information corresponding to (2)) consisting of temporary frame number 3, temporary slot number 43, and byte number 2 is rearranged to the position (2 ′) by deinterleaving. Immediately after the temporary address information (temporary address information corresponding to (1 ′)) including the temporary frame number 3, the temporary slot number 42, and the byte number 1, and the temporary frame number 3, Rearranged to the position immediately before the temporary address information (temporary address information corresponding to (3 ′)) including the slot number 44 and the byte number 3.

  In this way, the address information generation unit 58 generates temporary address information A before deinterleaving, and the deinterleaving unit 59 deinterleaves temporary address information A, and outputs temporary address information B after deinterleaving. Generate.

(Bit restoration / processing (3))
Next, the process (3) shown in FIG. 27 will be described in detail. The process (3) is a process for reversing the inverted bit to restore the original bit by referring to the temporary address information A, the temporary address information B, and the address information C based on the inverted bit information.

  Referring to FIG. 31, the bit restoration unit 60 scans the bit stream bit by bit, and detects a bit pattern “01100010” in which only the LSB is different from the synchronization pattern (step S3101). Then, the temporary address information α of the detected bit pattern is acquired from the temporary address information A (step S3102). In the example of FIG. 32, the bit restoration unit 60 detects the bit pattern “01100010” by scanning the input bit stream BS1 (bit stream after the packet synchronization is established), provisional frame number 3, provisional slot Temporary address information α consisting of number 43 and byte number 2 is acquired. Therefore, the eighth bit of the bit pattern indicated by the temporary address information α is an LSB that may have been inverted.

  The bit restoration unit 60 detects the input timing of the temporary address information α existing in the temporary address information B obtained by deinterleaving the temporary address information A (step S3103). In the example of FIG. 32, the input timing of the temporary address information α is t1 when it is associated with the bit stream BS2 after deinterleaving BS1.

  The bit restoration unit 60 acquires the address information β having the same input timing as the temporary address information α from the address information C (step S3104). The address information C is input to the bit restoration unit 60 at the same timing as the temporary address information B so that the correspondence with the temporary address information B can be determined. That is, in the bit restoration unit 60, the temporary address information B input from the deinterleave unit 59 and the address information C input from the inverted bit information detection unit 57 are both information after deinterleaving. It is assumed that data corresponding to each byte in the bit stream before deinterleaving input from 51 is supported. In the example of FIG. 32, the address information β at the same timing t2 as the timing t1 of the temporary address information α composed of the temporary frame number 3, the temporary slot number 43, and the byte number 2 in the temporary address information B is the address information. In C, the frame number is 97, the slot number is 52, and the byte number is 2. That is, the bit restoration unit 60 acquires the address information β (frame number 97, slot number 52, byte number 2) at the same timing (t1 = t2) as the temporary address information α from the address information C.

  The bit restoration unit 60 identifies an LSB that may have been inverted from the acquired address information β (step S3105). In the example of FIG. 32, the bit restoration unit 60 converts the LSB that may have been inverted from the address information β including the frame number 97, the slot number 52, and the byte number 2 into the frame number 97, the slot number 52, and the byte number 2. To the 8th bit.

  In this way, the bit restoration unit 60 converts the LSB of the temporary address information α in the bit stream before deinterleaving into the LSB of the address information β in the bit stream after deinterleaving. As a result, whether or not the LSB that may have been inverted in the bitstream before deinterleaving is an inverted bit is determined based on the address information β in the bitstream after deinterleaving and the bitstream (transmission after deinterleaving). This can be performed based on the inverted bit information reflecting the address information in the bit stream before interleaving in the device 2-2.

  Based on the inverted bit information, the bit restoration unit 60 determines whether or not the LSB that may have been inverted is an actually inverted bit, and identifies the inverted LSB (step S3106). Then, the identified LSB is inverted and restored to the original bit (step S3107). In the example of FIG. 32, the LSB that may have been inverted is the eighth bit of frame number 97, slot number 52, and byte number 2, and since the frame number is 97, it is stored in the data slot of frame number 97. It is necessary to refer to the inverted bit information for the data. The inverted bit information for the data stored in the data slot of frame number 97 is obtained from the TSMF header of frame number 99. Therefore, the bit restoration unit 60 converts the flag given to the TSMF header of the frame number 99 into the inverted bit information “8th to 14th bits excluding the packet synchronization byte of the slot number 52”, and based on the inverted bit information Then, it is determined whether or not the LSB (frame number 97, slot number 52, byte number 2 8th bit) that may have been inverted is actually the inverted bit. In this case, since the LSB that may have been inverted is included in the inverted bit information, it is determined that the LSB is actually the inverted bit, and this LSB (frame number 97, slot number 52, byte number 2 8) is determined. Bit) is specified as the inverted LSB. Here, the eighth bit of frame number 97, slot number 52, and byte number 2 is equal to the eighth bit of slot number 52 excluding the packet synchronization byte. Therefore, the bit restoration unit 60 corresponds to the LSB (the eighth bit of frame number 97, slot number 52, byte number 2) in the bit stream after deinterleaving, and the LSB (provisional frame number) in the bit stream before deinterleaving. 3, the eighth bit of the temporary slot number 43 and byte number 2) is inverted and restored to the original bits.

  On the other hand, the bit restoration unit 60 identifies the LSB that may have been inverted in Steps S3101 to S3105. However, in Step S3106, the LSB that may have been inverted is not actually an inverted bit. If it is determined, that is, if the LSB that may be inverted is not included in the inverted bit information, the inversion process is not performed.

  In this way, the bit restoration unit 60 inverts the bit inverted by the transmission device 2-2 and restores the original bit. The processing procedures shown in FIGS. 27, 28, 29, and 31 are examples, and the present invention is not limited to these processing procedures.

  As described above, according to the second embodiment, in the transmission apparatus 2-2 that multiplexes TS having a packet synchronization pattern of P bits (P ≧ 2) and adds a header to which control information is added and transmits the address, The information generation unit 47 and the interleave unit 48 interleave address information for the bitstream, and generate address information after interleaving. Then, when a false synchronization pattern exists at a position other than the header and other than the first 1 byte of the data, the bit reversing unit 49 inverts the LSB of the predetermined false synchronization pattern, and the inverted bit Inverted bit information indicating the position is generated based on the interleaved address information and is added to the TSMF header after 2TSMF. Then, the transmission device 2-2 transmits data including the inverted LSB, and after two frames, transmits a TSMF header to which a flag indicating the inverted bit position is added. As a result, the receiving device 3-2 does not continuously detect a false synchronization pattern for a predetermined number of times, and can establish packet synchronization at a correct position. Therefore, pseudo-synchronization does not occur, and the probability that pseudo-synchronization occurs can be reduced to zero.

  Also, according to the second embodiment, in the receiving device 3-2, when the receiving unit 51 receives the data and the TSMF header, after the packet synchronization establishing unit 52 establishes packet synchronization, the inverted bit information detecting unit 57 The stream is deinterleaved, the flag added to the TSMF header is converted into inverted bit information, and the address information C of the bitstream after deinterleaving is generated. Further, the address information generation unit 58 generates temporary address information A in the bitstream before deinterleaving, and the deinterleaving unit 59 deinterleaves the temporary address information A to generate temporary address information B. I made it. Also, the bit restoration unit 60 detects a bit pattern in which only the LSB is different from the synchronization pattern, and determines whether the LSB is an inverted bit based on the inverted bit information and the provisional address information A and B and the address information. The determination was made with reference to C, and the LSB determined to be an inverted bit was inverted and restored to the original bit. Thereby, after the packet synchronization is established, the bit inverted in the transmission device 2-2 can be restored to the original bit and restored.

[Modification]
The first and second embodiments are examples for explaining the gist of the present invention, and various modifications described below can be considered without departing from the gist of the present invention.

(Modification 1)
In the first embodiment, the bit inversion unit 23 inverts the LSB of the false synchronization pattern and generates the inverted bit information of the LSB. Further, the header generation unit 21 converts the inverted bit information into a flag, and adds the flag to the header after one frame. On the other hand, in the first modification, in addition to the bit inversion processing, the bit inversion unit 23 performs the data slot immediately before the header, that is, the last data slot in the frame immediately before the frame to which the header is attached, And, the LSB is inverted for all the false synchronization patterns existing in the data slot immediately after the header. Then, inverted bit information of the inverted LSB is generated. The header generation unit 21 converts the inverted bit information generated by the bit inverting unit 23 into a flag, and uses the flag for the same frame (the frame used when the inverted bit information corresponding to the flag is generated). Add to header.

  As a result, even if a false synchronization pattern is present due to the flag added to the header, there is no false synchronization pattern in the data slots before and after the header. not exist. This is because for the data slots before and after the header, the LSB of the false synchronization pattern existing there has already been inverted by the bit inverting unit 23. Therefore, in the receiving device 3-1, even if a false synchronization pattern is present by adding a flag to the header, pseudo synchronization does not occur, and the probability of occurrence of pseudo synchronization is set to 0. Can do. Also, the receiving device 3-1 detects the inverted bit information for each bit stream of the received RF signal, and restores the bits using the data stored in the header and data slot of the same frame. Thereby, since it is not necessary to accumulate the bit stream of the received RF signal, the circuit scale can be reduced as compared with the first embodiment, and the delay time is also shortened.

(Modification 2)
In the second embodiment, the header generation unit 41 adds a flag obtained by converting the inverted bit information to the TSMF header after two frames, and the bit inversion unit 49 determines the number of stages of the backward synchronization protection circuit of the reception device 3-2. Therefore, when a false synchronization pattern is detected 32 times or more consecutively, a false synchronization pattern with slot numbers 26 and 52 is selected and its LSB is inverted. On the other hand, in the second modification, the bit inversion unit 49 adds all the false synchronizations in the slot numbers 2 and 53 regardless of the number of false synchronization patterns that exist continuously in addition to the bit inversion process. Invert the LSB of the pattern. Then, inverted bit information of the inverted LSB is generated. The header generation unit 41 converts the inverted bit information generated by the bit inverting unit 49 into a flag, and uses the flag for the same frame (the frame used when the inverted bit information corresponding to the flag is generated). It is added to the TSMF header.

  As a result, even if a false synchronization pattern newly exists as a result of the header generation unit 41 giving the flag to the TSMF header of the same frame, the bit inversion unit 49 Since the LSB of the false synchronization pattern is inverted, the false synchronization pattern does not continue twice. This is because data in units of bytes in the flag in the TSMF header (data in units of bytes in the flag stored in the header slot of the slot number 1) is interleaved into data of bytes before and after the slot number 2 and This is because the data of the slot number 53 exists, and the 1-byte data of the flag and the 1-byte data of the slot numbers 2 and 53 are consecutively arranged. In this case, if the number of stages of the backward synchronization protection circuit of the reception device 3-2 is 2 or more, pseudo synchronization does not occur.

  Therefore, in the receiving device 3-2, with the flag added to the TSMF header, pseudo synchronization does not occur, and the probability that pseudo synchronization occurs can be reduced to zero. Further, the reception device 3-2 detects inverted bit information for each bit stream of the received RF signal using data stored in the TSMF header and the data slot of the same frame, and restores the bits. Thereby, since it is not necessary to accumulate the bit stream of the received RF signal, the circuit scale can be reduced as compared with the second embodiment, and the delay time is also shortened.

  This will be described with reference to FIG. For example, in the data surrounded by the symbol * in FIG. 25, it is assumed that a flag is stored at the position of 1 byte of frame number 4, slot number 1, and byte number 14 (since this 1 byte has a slot number of 1). , Data constituting the TSMF header). By storing the flag in the TSMF header, there is a possibility that a false synchronization pattern having LSB exists in the data of the byte or the subsequent byte. Here, it is assumed that a false synchronization pattern having LSB exists in one byte of frame number 4, slot number 1, and byte number 14 due to the storage of the flag. At this time, if there is no false synchronization pattern before 204 bytes and after 204 bytes, pseudo synchronization does not occur. That is, if there is a false synchronization pattern having LSB in one byte of frame number 3, slot number 53, byte number 14, and one byte of frame number 4, slot number 2, byte number 14, the receiving device 3 Regardless of the number of -2 backward synchronization protection circuits, all the LSBs may be inverted. That is, the bit inversion unit 49 may invert the LSBs of all the false synchronization patterns in the slot numbers 2 and 53 regardless of the number of false synchronization patterns that exist continuously. Thus, the false synchronization pattern does not exist twice consecutively before and after the flag.

  As described above, in the transmission apparatus 2-2, by setting a fixed slot number for bit inversion in advance, there is a false synchronization pattern continuously for at least 204-byte period or more than the number of stages of the backward synchronization protection circuit. There is nothing. Therefore, if the receiving device 3-2 has two or more stages of backward synchronization protection circuits, pseudo synchronization does not occur.

(Modification 3)
In the first and second embodiments, the flag corresponds to a block obtained by dividing the flag by 7 bits in the data length obtained by removing the packet synchronization pattern from the data length of the TS packet stored in the data slot. Prepared for each TS packet. On the other hand, in the third modification, a flag is prepared for each frame. That is, in the data length obtained by removing the packet synchronization pattern from the data length of all TS packets stored in the data slot in one frame, it corresponds to each block divided into 7 bits so that it is prepare.

  For example, in the case of the first embodiment, 214 bits must be prepared for each TS packet. Of the 214 bits, 213 bits are allocated for every 7 bits of data, while the remaining 1 bit is allocated for 5 bits counted from the end of the data. The remaining 1 bit is allocated to only 5 bits instead of 7 bits of data, and since 2 bits are insufficient, the allocation efficiency is insufficient, and the number of TS packets corresponding to the flag As the number increases, the allocation efficiency decreases significantly. Therefore, in the third modification, a flag is prepared for each frame in order to absorb the shortage of 2 bits generated for each 1 TS packet. As a result, the number of bits of the flag can be reduced.

DESCRIPTION OF SYMBOLS 1 Transmission system 2 Transmission apparatus 3 Reception apparatus 4 Transmitting station 21, 41 Header generation part 22 Header insertion part 23, 49 Bit inversion part 24, 50 Transmission part 31, 51 Reception part 32, 52 Packet synchronization establishment part 33, 57 Inversion bit Information detection unit 34, 60 Bit recovery unit 35 Header removal unit 42 Multiplexing unit 43 Packet synchronization byte conversion unit 44 Energy spreading unit 45 RS encoding unit 46, 48 Interleave unit 47, 58 Address information generation unit 53, 59, 61 Interleave unit 54, 62 RS decoding unit 55, 63 Energy despreading unit 56, 64 Packet synchronization byte restoration unit 65 Separation unit

Claims (13)

Digital data including a synchronization pattern is multiplexed and stored in a plurality of data slots, control information including a synchronization pattern is added to a header and stored in a header slot, and a bit stream of a frame including the header slot and the plurality of data slots In the transmission device that transmits
Bit inversion that determines whether the same bit pattern as the synchronization pattern exists in a position other than the synchronization pattern in the bit stream, and inverts a predetermined bit in the bit pattern if the same bit pattern exists And
Generating header information indicating the inverted bit position, and adding the flag information to generate a header;
A transmission device comprising: The transmission apparatus according to claim 1,
The bit length of the synchronization pattern is P (P ≧ 2),
The predetermined bit inverted by the bit inverting unit is the last bit in the bit pattern,
When the bit stream from which the synchronization pattern has been removed is divided into consecutive P-1 bit blocks, the flag information generated by the header generation unit indicates whether the inverted bit exists in the block. A transmission apparatus characterized in that a 1-bit flag indicating such is used as information assigned to each block. The transmission device according to claim 1 or 2,
The bit inverting unit detects the synchronization pattern provided in a receiving device that receives the bitstream when a plurality of bit patterns that are the same as the synchronization pattern exist in positions other than the synchronization pattern in the bitstream. A transmitting apparatus comprising: selecting a predetermined number of bit patterns from the plurality of bit patterns according to the number of stages of a backward synchronization protection circuit that establishes synchronization; and inverting predetermined bits in the selected bit pattern. The transmission device according to claim 1 or 2,
The bit reversing unit, when there are a plurality of bit patterns that are the same as the synchronization pattern in positions other than the synchronization pattern in the bit stream, the plurality of the bit patterns according to the type of the synchronization pattern and the transmission cycle of the synchronization pattern. A transmitting apparatus comprising: selecting a predetermined number of bit patterns from a bit pattern, and inverting predetermined bits in the selected bit pattern. In the transmission device according to any one of claims 1 to 4,
The bit inversion unit selects a bit pattern at a predetermined position from the plurality of bit patterns when the same bit pattern as the synchronization pattern exists in a position other than the synchronization pattern in the bit stream, and the selected bit A transmission apparatus characterized by inverting predetermined bits in a pattern. In the transmission device according to any one of claims 1 to 5,
The header generation unit generates flag information indicating the inverted bit position in a predetermined frame, and adds the flag information to a header of a frame immediately after the predetermined frame. Transmitter device. In the transmission device according to any one of claims 1 to 5,
The bit inversion unit, when inverting the predetermined bit, at least all of the same bit pattern as the synchronization pattern in the digital data stored in the data slot immediately after the header slot and the data immediately before the header slot Invert the predetermined bits for all of the same bit pattern as the synchronization pattern in the digital data stored in the slot,
The transmission apparatus characterized in that the header generation unit generates flag information indicating the inverted bit position in a predetermined frame, and adds the flag information to a header of the predetermined frame. Digital data including a synchronization pattern is multiplexed and stored in a plurality of data slots, control information including a synchronization pattern is added to a header and stored in a header slot, and a bit stream of a frame including the header slot and the plurality of data slots In the transmission device that transmits
A first interleaving unit that performs interleaving in units of bytes with a predetermined interleave length on the bitstream;
An address information generator for generating address information for specifying the byte length data for each byte length data constituting the bitstream;
A second interleave unit that performs interleaving in units of bytes at the same timing and the same predetermined interleave length as the first interleave unit for the address information;
It is determined whether or not the same bit pattern as the synchronization pattern exists at a position other than the synchronization pattern in the bit stream interleaved by the first interleaving unit, and when the same bit pattern exists, the bit pattern A bit inversion unit for inverting a predetermined bit in
Flag information reflecting address information interleaved by the second interleave unit, generating flag information indicating the inverted bit position, and adding the flag information to generate a header;
A transmission device comprising: The transmission device according to claim 8, wherein
The header generation unit is flag information reflecting the address information interleaved by the second interleaving unit, generates flag information indicating the inverted bit position in a predetermined frame, and the flag information A transmission apparatus characterized in that it is added to a header of a frame two frames after the predetermined frame. The transmission device according to claim 8, wherein
The address information is composed of a frame number, a slot number in a header slot and a data slot constituting the frame, and a byte number in byte-length data constituting the slot,
The bit inverting unit, at the time of inverting the predetermined bit, at least the address information before and after the address information in which the flag information in the header exists among the address information interleaved by the second interleave unit In the digital data corresponding to the slot number constituting the address information, the predetermined bits for all of the same bit pattern as the synchronization pattern are inverted,
The header generation unit is flag information reflecting the address information interleaved by the second interleaving unit, generates flag information indicating the inverted bit position in a predetermined frame, and the flag information A transmission apparatus, characterized by being added to a header of the predetermined frame. In the transmission device according to any one of claims 1 to 10,
The bit length of the synchronization pattern is P (P ≧ 2),
The flag information generated by the header generation unit includes the inverted bit in the block when the bit stream from which the synchronization pattern has been removed is divided into blocks of P-1 bits that are continuous in the one frame. A transmission apparatus characterized in that a 1-bit flag indicating whether or not exists is information assigned to each block in the one frame. A predetermined bit is inverted within the same bit pattern as the synchronization pattern of the digital data including the synchronization pattern, flag information indicating the inverted position is added to the header, and the digital data after the predetermined bit is inverted is multiplexed In a receiving device that is stored in a plurality of data slots, the header to which the flag information is added is stored in a header slot, and receives a bit stream of a frame including the header slot and a plurality of data slots,
A synchronization establishment unit that detects the synchronization pattern and establishes synchronization from the received bitstream;
After the synchronization is established, the inverted bit position is specified from flag information included in a header stored in a header slot in the received bitstream, and the specified bit position is determined for the received bitstream. A bit restoration unit that inverts the bits of the original and restores the original bits;
A receiving apparatus comprising:   A transmission system comprising the transmission device according to any one of claims 1 to 11 and the reception device according to claim 12.

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