JPH11214967A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay circuit capable of adjusting delay times with respect to the rise and fall of an input signal after it is manufactured. SOLUTION: This circuit includes plural switchable resistance elements, which are connected in parallel, consists of a delay element which delays an input signal via plural resistance elements and gets an output signal and a delay time controlling part 10 which selectively sends a switching control signal to plural resistance elements and controls delay time of the rise or fall of the input signal respectively by controlling ON/OFF of the resistance elements with a control signal from the part 10 and changing the resistance value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit and, more particularly, to a delay circuit capable of adjusting a delay time for rising and falling of an input signal after manufacturing.

[0002]

2. Description of the Related Art As shown in FIG. 7A, a delay element used for adjusting the skew (timing and phase shift) of an internal signal in a conventional semiconductor integrated circuit has a capacitor connected to the output of an inverter. A method in which a delay is obtained by changing the information transmission time to the next stage by adding or switching a capacitive element. As shown in FIG.
And the delay is obtained by the resistance value of the FET. As shown in FIG. 7 (C), by cascading the FETs, the drive capability of the inverter is reduced and the load on the preceding stage is reduced. In some cases, the weight is increased to delay the information transmission time to the next stage to obtain a delay.

However, all of the above three circuits cannot always realize the delay value at the time of design due to the manufacturing variation of the delay element and the like, and it is difficult to adjust the delay time after the manufacturing. No consideration is given to the adjustment of the delay time for the rise and fall of the input signal.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a delay circuit capable of adjusting a delay time after manufacturing and a delay time for rising and falling of an input signal in view of the above-mentioned problems of the prior art. To provide.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention includes a plurality of switchable resistance elements connected in parallel, and delays an input signal via the plurality of resistance elements. A delay element that obtains an output signal; and a delay time control section that selectively sends a switching control signal to the plurality of resistance elements. The control signal from the delay time control section turns on / off the resistance element. By controlling and changing the resistance value, the delay time of the rise and fall of the input signal can be controlled separately.

An arbitrary resistance element is turned ON or OFF by a control signal from the delay time control unit. When the input signal IN is input in this state, as the delay time between the input signal IN and the output OUT, the resistance elements R1, n + 1, R1, each having an arbitrary switchable resistance value with respect to the rise of the input.
n + 2,... R1,2n and R2,1, R2,2,.
Among the n, a delay due to the resistance value of the ON-state resistance element is obtained, and with respect to the fall, R1,1, R1,2... R1, n and R2, n + 1, R2, n + 2,. Among them, the delay time due to the resistance value of the ON resistance element can be obtained.

Therefore, by turning ON / OFF the resistance elements connected in parallel by the delay time control unit, the resistance value of the resistance elements connected in parallel is adjusted, and an arbitrary delay is provided for the rise and fall of the input signal. You can get time.

[0008]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an electric circuit diagram showing the configuration of the first embodiment. As shown in FIG. 1, the variable delay circuit according to the first embodiment of the present invention includes two delay elements L1, H1 and L2, H2.
It is shaped like a series connection.

A P-channel FET P1 and an N-channel F
The CMOS gate of ET N1 is connected to the input terminal IN,
The source of the P-channel FET P1 is a positive power supply terminal, and the drain of the P-channel FET P1 is a delay element L1 (resistance elements R1,1, R1,2... R1) composed of a switchable P-channel FET connected in parallel. , n). The source of N-channel FET N1 is connected to the negative power supply terminal, and the drain of N-channel FET N1 is connected in parallel to a switchable N-channel FE.
T delay element H1 (resistance elements R1, n + 1, R1, n
+2,... R1, 2n). The drains of delay elements L1 and H1 are both connected to the CMOS gates of P-channel FET P2 and N-channel FET N2.

The drain of the P-channel FET P2 is connected to a delay element H2 (resistance elements R2,1, R2,2,... R) composed of switchable N-channel FETs connected in parallel.
2, n) and the source of P-channel FET P2 is connected to the positive power supply terminal. The drain of the N-channel FET N2 is connected to the source of a delay element L2 (consisting of resistance elements R2, n + 1, R2, n + 2,... R2, 2n) composed of a switchable P-channel FET connected in parallel, and an N-channel FET. The source of FET N2 is connected to the negative power supply terminal. The drains of the delay elements L2 and H2 are connected to the output terminal OUT.

Control signals HDLYi and LDLYi (1 ≦ i ≦ n) for setting delay times for the rise and fall of the input signal IN from the delay time control unit are transmitted to each delay element L.
1, H1, L2 and H2 are output. Control signal at rising
HDLYi is connected to each resistance element R1, n + i, and the signal HLYi
Each of the control signals whose DLYi is inverted by the inverter 12 is connected to each resistance element R2, i. Further, each of the control signals LDLYi at the time of the falling is connected to the resistance element R2, n + i, and each of the control signals obtained by making the signal LDLYi out of phase by the inverter 12 is connected to each of the resistance elements R1, Ri.

When the input signal IN rises, an N-channel FET N1 and an N-channel FET connected in parallel
The delay time at the rise of the input signal is controlled by H1, the P-channel FET P2 and the P-channel FET H2 connected in parallel, and the P-channel FET P1 and the P-channel FET connected in parallel with respect to the fall of the input signal IN The delay time when the input signal falls is controlled by L1, N-channel FET N2 and N-channel FET L2 connected in parallel. It is possible to set up to 2 ⁿ -1 maximum delay amounts for the rising and falling edges of the input signal IN, respectively.

Next, the delay time control in the first embodiment will be described.

First, when setting the delay time with respect to the rise of the input signal IN, the delay time control section sets the delay time with respect to the rise, so that the control signal is controlled.
Any selected signal in HDLY becomes High / Low, and FETs H1 and H2 connected to each signal are turned on.
/ OFF, F is determined by the resistance value of the FET in the ON state.
Since each of ET H1 and H2 has a maximum of 2 ⁿ -1 resistance values, it is possible to control a maximum of 2 ⁿ -1 delay amounts with respect to the rising edge of the input. Here, at most 2 ⁿ -1
The street means that each of the n resistance elements is ON / OFF.
From 2 ⁿ possible combinations,
This is a number obtained by subtracting one pattern when all elements are OFF.

When the delay time for the fall of the input signal IN is set, the delay time for the fall is set by the delay time control unit so that the control signal can be set.
An arbitrary selected signal in LDLY becomes High / Low, and the FETs L1 and L2 connected to each signal are turned on.
/ OFF, F is determined by the resistance value of the FET in the ON state.
Since ET L1 and L2 each have a maximum of 2 ⁿ -1 resistance values, it is possible to control a maximum of 2 ⁿ -1 delay amounts with respect to the falling edge of the input.

Further, by setting the two at the same time, it is possible to simultaneously control the delay time for the rise and fall of the input signal IN.

Next, a second embodiment of the present invention will be described.

FIG. 2 is an electric circuit diagram showing the configuration of the second embodiment, FIGS. 3A and 3B are diagrams each showing a modification of a partial configuration of the second embodiment, and FIG. 4A. (B) is a figure which shows the modification of some structure of 2nd Embodiment, respectively.

In the present embodiment, the FETs connected in parallel in the first embodiment of FIG. 1 are replaced with other switchable resistance elements. P-channel FET resistance elements R1,1 to R1, n and R2,1 to R2, n, and N-channel FET resistance elements R1, n + 1 to R1,2n and R2,
n + 1 to R2,2n, and each resistance element is P
As an example using a channel FET, a plurality of P-channel FETs are connected in series as shown in FIG. 3A, or a plurality of P-channel FETs are connected in parallel as shown in FIG. 3B. N
The same applies to the case of a channel FET.

As in the first embodiment shown in FIG.
Up to 2 ⁿ each for rising and falling of N
One delay amount can be controlled.

Further, as shown in FIG. 4A, the FETs connected in parallel are directly connected without passing through the CMOS gate P1 or N1.
Configuration connected to the positive power supply side or negative power supply side, or FIG.
As shown in FIG. 3B, a maximum of ^2.sup.n- 1 types of delay can be obtained by a configuration in which a CMOS gate is used and a CMOS gate is not used.

Next, a third embodiment of the present invention will be described.

FIG. 5 is an electric circuit diagram showing a configuration of the third embodiment, and FIG. 6 is an electric circuit diagram showing a configuration of a modification of the third embodiment.

The second embodiment differs from the second embodiment in that the control signals to the FETs H1 and H2 and the FETs L1 and L2 are reversed in phase (FIG. 2). Each of the resistors is controlled by a phase signal, and the resistance elements in the FETs H1 and H2 and the FETs L1 and L2 can be constituted by only N-channel FETs or only P-channel FETs.

The relative rise and fall of the input signal IN is in this embodiment, the maximum 2 ⁿ -1 kinds in the previous paragraph, it is possible to control a delay of up to 2 ⁿ -1 kinds later, as in this embodiment In the case of two columns, the maximum (2 ⁿ
-1) × (2 ⁿ -1) delay controls are possible.

FIG. 6 is a diagram showing switching between FETs H1 and H2.
The FETs used for switching and the switches L1 and L2
FETs used for switching are of the same channel
By removing the number of control signals.
However, also in this embodiment, a maximum of 2 ⁿ-1 delay control
Is possible.

Although the embodiment in which two stages of delay elements are connected in series has been described above, the present invention is not limited to two stages, but can be implemented sufficiently with only one stage or three or more stages. Is easily considered by those skilled in the art.

[0029]

According to the present invention, the delay value can be changed only when the input signal rises, the delay value can be changed only when the input signal falls,
Alternatively, it is possible to simultaneously change the two delay values when the input signal rises and falls.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a configuration of a first embodiment.

FIG. 2 is an electric circuit diagram showing a configuration of a second embodiment.

FIGS. 3A and 3B each show a modification of a partial configuration of the second embodiment; FIGS.

FIGS. 4A and 4B each show a modification of a partial configuration of the second embodiment; FIGS.

FIG. 5 is an electric circuit diagram showing a configuration of a third embodiment.

FIG. 6 is an electric circuit diagram showing a configuration of a modification of the third embodiment.

FIGS. 7A, 7B, and 7C are electric circuit diagrams each showing a configuration of a conventional technique;

[Explanation of symbols]

 10, 11 delay time control unit 12 inverter H delay element when input signal rises L delay element when input signal falls R resistance element such as switchable FET

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 11, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

[0005]

In order to solve the above-mentioned problems, the present invention comprises a plurality of switchable resistance elements connected in parallel, and delays an input signal via these resistance elements. Output rising delay element and / or
Is connected in multiple stages of falling delay elements in series.
Te provided, and set the delay time rise, with respect to the falling
Forward and reverse two switches from the delay time control unit for the constant
Rise delay of upstream and downstream by ring control signal
Said plurality of resistive elements and / or preceding elements included in the element
By selectively controlling the ON / OFF of each of the plurality of resistive elements included in the falling delay element at the subsequent stage and changing the resistance value, the rising and falling of the input signal can be achieved.
This is a variable delay circuit that controls the delay time of the falling edge.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

[0029]

According to the present invention, a plurality of stages of delay elements are
Since it can be controlled by one signal, only one delay time control unit is required.
Often, a plurality of delay elements are connected in series to change the delay value only when the input signal rises, to change the delay value only when the input signal falls, or to change two delay values when the input signal rises and falls simultaneously. It is possible.

Claims (6)

[Claims] 1. A delay element including a plurality of switchable resistance elements connected in parallel, delaying an input signal via the plurality of resistance elements to obtain an output signal, and a switching control signal to the plurality of resistance elements. And a delay time control section for selectively transmitting the input signal, and controlling the ON / OFF of the resistance element by a control signal from the delay time control section to change the resistance value, thereby delaying the rise of the input signal. A variable delay circuit for controlling time. 2. A delay element including a plurality of switchable resistance elements connected in parallel, delaying an input signal via the plurality of resistance elements to obtain an output signal, and a switching control signal to the plurality of resistance elements. And a delay time control unit that selectively sends out the falling edge of the input signal by controlling ON / OFF of the resistance element by a control signal from the delay time control unit and changing the resistance value. A variable delay circuit for controlling a delay time. 3. A delay element including a plurality of switchable resistance elements connected in parallel, and delaying an input signal via the plurality of resistance elements to obtain an output signal; and a switching control signal applied to the plurality of resistance elements. And a delay time control unit that selectively sends out the input signal. The control signal from the delay time control unit controls ON / OFF of the resistance element to change the resistance value, thereby causing the rise and rise of the input signal. A variable delay circuit for controlling a falling delay time. 4. The variable delay circuit according to claim 3, wherein the control signals from the delay time control section are in opposite phases in controlling the rising and falling of the input signal. 5. The variable delay circuit according to claim 1, wherein two or more delay elements are connected in series. 6. The variable delay circuit according to claim 1, wherein the plurality of switchable resistance elements connected in parallel comprise field effect transistors.