JPH11212896A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the burden of a data processor communicating data through the serial bus based on IEEE1394 standard. SOLUTION: A filter circuit 7a in a data processor 10a receives a response packet from an IEEE1394 bus 30, reads tLabel of the header and alloccates a processing to respective control circuits 1a, 2a and 3a containing MPU 1a. When the processing of MPU 1a is not required, the response packet is directly transferred to other control circuits 2a and 3a and therefore the burden of MPU 1a is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus used in a system for transmitting and receiving data in packet units via a serial bus conforming to the IEEE 1394 standard.

[0002]

2. Description of the Related Art Conventionally, a video capture board, an RS232C bus, and the like are separately required to capture image data and audio data by a data processing device such as a personal computer and to control AV equipment. Could not do.

[0003] In recent years, standards suitable for data communication in the multimedia age have been proposed.
The EE1394 High Performance Serial Bus Standard (hereinafter referred to as the IEEE 1394 Standard) "has provided an environment for freely performing high-speed and large-capacity communication.

A data transfer mode conforming to the IEEE 1394 standard includes an "asynchronous (asynchronous transfer) mode".
And "isochronous transfer mode (real-time transfer mode)", and both transfer data in packet units.

In the isochronous transfer mode, 125 μs
This mode guarantees transmission and reception of a fixed amount of packets every time, and is suitable for applications such as video and audio because high-speed processing is possible. The asynchronous mode has a lower priority than the isochronous transfer mode, and is suitable for normal file transfer and the like.

FIG. 2 shows the format of a packet in the above-mentioned asynchronous mode. This packet format is a packet composed of a 32-bit data string as shown in FIG. 2, and is composed of a header section 200 and a data section 300 like a normal packet.

In this format, the destination ID in the header section 200 is a number (ID) for identifying a destination device, and the source ID is a number (ID) for identifying a source device. Has become.

Further, a transaction label (tLabel)
Is a unique tag assigned to each unresolved transaction transmitted from the device, and is a number for associating a request packet with a response packet. Here, 6-bit data is used.

Further, a transaction code (tCode)
Is a code that specifies the format of the packet and the type of transaction that must be performed.
This code indicates the type of the packet, and indicates whether the transaction is read, write, or lock, and whether the transaction is a request packet or a response packet.

Rt indicates a retry code, and pri
Indicates priority. All of these are indispensable in the asynchronous packet format,
The description of the present invention is omitted because it is not important.

Each transaction can be identified as unique by the combination of the source ID of the requesting device, the destination ID of the responding device, and tLabel.

A case where the above-mentioned asynchronous type packets are mutually transmitted and received between devices connected by the IEEE 1394 bus will be described with reference to the system shown in FIG. 3 as an example.

In this system, as shown in FIG. 3, a plurality of data processing devices 110a and 110b
The data processing devices 110a and 110b are connected to the printers 120a and 120b.
b are connected to each other.

In each of the data processing devices 110a and 110b, MPUs 101a and 101b for performing data processing, hard disks 104a and 104b for recording data,
Hard disk controllers 103a and 103b for controlling the hard disks 104a and 104b, and printer controllers 102a and 102b for controlling the printers 120a and 120b are provided, respectively.

In the above system, when two data processing apparatuses 110a and 110b communicate with each other, a side requesting a process and a side executing the process are distinguished.

Data processing device 110a requesting processing
The MPU 101a in the device selects the data processing device 110b requesting the processing by the destination ID, specifies its own device by the source ID, specifies the transaction by the tCode, and writes the desired number to the tLabel to specify the number. And other header elements
Set rt (retry code) and pri (priority) according to the conditions and generate a request packet.

The request packet is put on the IEEE 1394 bus 130 by the MPU 101a, and is received by the MPU 101b in the data processing device 110b on the processing side.

After receiving the request packet, the data processing device 110b executes a process according to the content of the request packet, generates a response packet,
Via the 394 bus 130, the generated response packet is returned to the data processor 110a on the transmission side.

For example, one data processing device 110a
Transmits a read request packet for reading data stored in the hard disk 104b in the other data processing device 110b, the corresponding data processing device 1
When 10b receives the request packet, it reads the data in the hard disk 104b according to the instruction,
The result is returned as a response packet.

Data processing device 110b requested to process
If the side generates a response packet, there is an agreement that the number to be added to the tLabel of the response packet should be the same as the number of the tLabel of the request packet that requested the response packet, thereby receiving the response packet. When the data processing device 110a receives the response packet, the response packet is associated with the request packet, and the content thereof can be specified.

Then, the data processing device 110a, which has received the response packet, analyzes the content in association with the request packet by the MPU 101a, and transfers the content to the printer controller 102a when printing processing is to be performed.
The printer controller 102a transmits the print data to the print controller 105a in the printer 120a.
Print by a. On the other hand, in the case of data to be recorded, the data is transferred to the disk controller 103a and recorded on the hard disk 104a.

Thus, in the prior art system, M
The PU 101a analyzes the contents of the response packet and sends the response to the printer controller 102a or the disk controller 1a.
03a, etc., the MPU 10
1a also needs to perform some processing other than the response packet to be processed, and when the traffic increases, M
The load on the PU 101a was heavy.

[0023]

In the above conventional system, the second MPU 101b reads all the contents of the received request packet, and if the transaction of the request packet is to be processed by the MPU itself, the second MPU 101b itself. Processing must be performed, and if not, it must be transferred to a control circuit (printer controller or disk controller in the above example) that should perform the processing.

Therefore, when there are many request packets that do not require the processing of the MPU itself, there is a problem that the MPU is unnecessarily burdened and the processing speed of the data processing device is reduced.

The present invention has been made to solve the above-mentioned disadvantages of the prior art, and its object is to provide IEEE139
An object of the present invention is to provide a technique for reducing the load on the MPU of the data processing device connected to the four buses and increasing the processing speed.

[0026]

According to the first aspect of the present invention,
A data processing device that has a control circuit including an arithmetic circuit, sends request data to a serial data bus that performs data transmission in packet units, and processes response data returned according to the request data by the control circuit. There is provided a filter circuit that receives the response data and sorts response data to be processed by the arithmetic circuit and response data to be processed by a control circuit other than the arithmetic circuit, and a control circuit other than the arithmetic circuit is provided. The response data to be processed is configured to be transferred to a control circuit corresponding to the content without passing through the arithmetic circuit.

According to a second aspect of the present invention, in the data processing apparatus according to the first aspect, the request data and the response data are associated with each other by assigning the same number to data at a predetermined position in the packet. In this case, the number is previously associated with a specific control circuit, and the number associated with the control circuit to be processed with the response data returned in response to the request data is assigned. Have been.

According to a third aspect of the present invention, in the data processing apparatus according to any one of the first to second aspects, the number is associated with a specific control circuit by the arithmetic circuit. It is configured to be.

According to a fourth aspect of the present invention, in the data processing apparatus according to any one of the first to third aspects, the control circuit includes a control circuit of a peripheral device.

According to a fifth aspect of the present invention, there is provided the data processing device according to any one of the first to fourth aspects, wherein the structure of the request data and the structure of the response data conform to the IEEE 1394 standard. I have.

The invention according to claim 6 is the data processing device according to claim 5, wherein the number is tLa in a packet.
It is configured to be given to the position in bel.

According to a seventh aspect of the present invention, in the data processing apparatus according to any one of the first to sixth aspects, the arithmetic circuit is an MPU that controls the data processing apparatus.

The present invention is configured as described above. The data processing device transmits a request data packet (hereinafter, referred to as a request packet) and responds to the request data packet (hereinafter, referred to as a response packet). )), The filter circuit receives the response packet. If the response packet is to be processed by an arithmetic circuit such as an MPU, the response packet is output from the filter circuit to the arithmetic circuit and processed by other control circuits. If so, the filter circuit is configured to transfer the contents of the response packet to the control circuit that should perform the processing.

For this reason, the arithmetic circuit does not need to perform the above-mentioned distribution work at all.
As compared with the conventional case where the operation circuit such as U performs the operation, the load on the operation circuit is reduced and the processing speed of the operation circuit is improved.

In the IEEE 1394 standard, a request packet and a response packet are associated with each other by assigning the same number to a predetermined position (tLabel) in the packet. By associating that number with a control circuit that should process the response packet in advance, the above-described sorting process can be performed only by referring to that number.

[0036]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a system based on the IEEE 1394 standard.

The system shown in FIG. 1 includes a plurality of data processing devices (here, two data processing devices 10a and 10b).
Just show. ) And a printer (here, two printers 2)
Only 0a and 20b are shown. ) And an IEEE 1394 bus 30 which is a serial data bus.

In each of the data processing devices 10a and 10b,
MPUs 1a and 1b as arithmetic circuits, printer controllers 2a and 2b and disk controllers 3a and 3b as control circuits, and hard disks 4a and 4b are provided, respectively. Each controller 2a, 2b, 3a,
3b is connected to its own MPUs 1a and 1b, respectively, and is configured to be able to input and output data to and from the MPUs 1a and 1b.

In each of the data processing devices 10a and 10b,
Other circuits such as a storage circuit (not shown) are also provided, and each of the MPUs 1a and 1b can perform data processing such as numerical calculation and image processing using the circuits.

Each of the printers 20a and 20b has a print controller 5a, 5b and a corresponding one of the print controllers 5a, 5b.
b are provided with printing units 6a and 6b, respectively, and the print controllers 5a and 5b and the above-described printer controllers 2a and 2b are connected to the respective printers 20a and 20b.
outside of b, interconnected by a cable,
It is configured to input and output data necessary for printing.

When data processing is performed and the result is printed, each of the MPUs 1a and 1b first transmits data to be printed to the printer controllers 2a and 2b.
Printer controller 2a, 2b and print controller 5
a, 5b, and communicates with the print controllers 5a, 5b.
5b controls the printing units 6a and 6b, and prints the data processing result on a printing medium such as paper.

The hard disks 4a and 4b are connected to the disk controllers 3a and 3b, respectively. When the MPUs 1a and 1b perform data processing, the hard disks 4a and 4b of the own device are transmitted via the disk controllers 3a and 3b. It is configured to be able to input and output data processing results and data necessary for processing between the server and the server.

Further, in each of the data processing devices 10a and 10b, filter circuits 7a and 7b are provided, respectively, and the filter circuits 7a and 7b are connected to the IEEE 1394 bus 3 respectively.
0 and the MPUs 1a and 1b of the own device.
1a and 1b are configured to be able to transmit and receive data bidirectionally to and from the IEEE 1394 bus 30 via their own filter circuits 7a and 7b.

In communication using the IEEE 1394 bus 30,
It is determined that data transmission and reception are performed in packet units. For example, when one data processing device 10a sets the other data processing device 10b as a transmission destination and transmits a request packet, the MPU 1a as the transmission source A destination ID specifying the data processing device 10b of the transmission destination is selected, a source ID specifying the own device as a transmission source is selected, and a response is made in response to the request packet received by the data processing device 10b of the transmission destination. Set a specific tLabel to recognize the response packet and generate a request packet.

In this case, when each of the MPUs 1a and 1b receives the response packet, it knows in advance what processing to perform on the response packet. Here, it is assumed that the processing contents can be classified into the following four processings A to D.

Process A: A case where the data processing in the MPU is not required even if the response packet is received, and the content of the request packet is written as it is to the hard disk built in the own device.

Process B: When the response packet is received and the data processing in the MPU is not required, and the content of the request packet is printed as it is by the printer connected to the own device.

Process C: A case other than processes A and B in which data processing by the MPU is not required even if a response packet is received.

Process D: When data processing of the received response packet is performed by the MPU, and then processing such as recording on a hard disk or outputting to a printer is performed. This process D is a process performed in all cases that do not correspond to the above processes A to C.

When transmitting a request packet, each of the MPUs 1a and 1b attaches a tLabel corresponding to the processing of a response packet for the request packet. Specifically, four types of processing A to D are provided. If there is a process, the upper two bits of tLabel are appended with “00” for process A, “01” for process B, and “10” for process C. In the case of the processing D, "11" is added.

Accordingly, when tLabel is 6 bits, any one of “000000” to “001111” is added to the processing A, and similarly, “010000” to “01” is applied to the processing B.
011111 ”, and“ 100,000 ”to“ 1 ”in process C.
01111 ”, and“ 110000 ”to“ 11 ”in the process D.
1111 ".

When actually transmitting the request packet, the header is determined by setting tCode and rt (retry code) and pri (priority) which are other elements of the header, and the header is determined together with necessary data. After generating the packet, IE
The data is transmitted to the EE1394 bus 30.

The destination data processing device 10b receives the request packet via the filter circuit 7b,
A process corresponding to the content is executed. For example, if the received request packet is for reading specified data from the hard disk 4b, a read command is issued to the disk controller 3b to execute the processing.

When returning the data as a response packet, the data processing device 1 which is the transmission destination
0a, a source ID for specifying the data processing device 10b that is the reply source, and other t
Elements such as Code, rt, pri, etc. are attached, and a response packet is generated with the same tLabel as the tLabel of the request packet, and transmitted to the IEEE1394 bus 30.

In the data processing device 10a at the reply destination, the filter circuit 7a receives a response packet from the IEEE 1394 bus 30, unlike the prior art.

The filter circuit 7a is directly connected to its own printer controller 2a and disk controller 3 and a. When a response packet is received, its tLabel is analyzed, and only when the processing D requires processing by the MPU 1a. , Outputs the contents of the response packet to the MPU 1a, and does not output it to the MPU 1a in other cases.
Indicates the processing A, it is directly transferred to its own disk controller 3a, and if it indicates the processing B, it is directly transferred to its own printer controller 2a.

Then, the disk controller 3a or the printer controller 2a, which has received the contents of the response packet, writes the data on the hard disk 4a, or transmits the response packet to the printer 20a for printing. MPU1a will not be involved at all.

On the other hand, if it is determined that it indicates the processing D, the contents of the response packet are output to the MPU 1a, and after the necessary data processing is performed by the MPU 1a, the result is transmitted to the printer controller 2a. It is output to the disk controller 3a and the like.

As described above, in the present embodiment, the processing content of the response packet corresponding to the request packet is predicted, and the tLabel of the request packet is assigned according to the processing content of the response packet. Therefore, since the response packet can be classified by tLabel, it is possible to transfer the response packet to the data processing device that executes the processing by a simple filter circuit.

Therefore, compared with the prior art in which the MPU sorts the response packets, the load on the MPU is significantly reduced, and the processing capability of the entire data processing device is improved.

In the above embodiment, a printer and a built-in hard disk have been described as examples of peripheral devices.
It goes without saying that peripheral devices are not limited to this.
Further, the association between tLabel and processing is not limited to the one shown in the above embodiment.

[0062]

As described above, according to the present invention, M
The load on an arithmetic circuit such as a PU can be reduced, and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention.

FIG. 2 is a diagram for explaining a format of a packet in an asynchronous mode;

FIG. 3 is a diagram showing a configuration of a conventional data transmission / reception system conforming to the IEEE 1394 standard.

[Explanation of symbols]

1a, 1b... Arithmetic circuits 2a, 2b, 3a, 3b.
... Control circuit 7a, 7b ... Filter circuit 10
a, 10b Data processing device 30 Serial data bus (IEEE 1394 bus)

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] March 16, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus used in a system for transmitting and receiving data in packet units via a serial bus conforming to the IEEE 1394 standard.

[0002]

2. Description of the Related Art Conventionally, a video capture board, an RS232C bus, and the like are separately required to capture image data and audio data by a data processing device such as a personal computer and to control AV equipment. Could not do.

[0003] In recent years, standards suitable for data communication in the multimedia age have been proposed.
The EE1394 High Performance Serial Bus Standard (hereinafter referred to as the IEEE 1394 Standard) "has provided an environment for freely performing high-speed and large-capacity communication.

A data transfer mode conforming to the IEEE 1394 standard includes an "asynchronous (asynchronous transfer) mode".
And "isochronous transfer mode (real-time transfer mode)", and both transfer data in packet units.

In the isochronous transfer mode, 125 μs
This mode guarantees transmission and reception of a fixed amount of packets every time, and is suitable for applications such as video and audio because high-speed processing is possible. The asynchronous mode has a lower priority than the isochronous transfer mode, and is suitable for normal file transfer and the like.

FIG. 2 shows the format of a packet in the above-mentioned asynchronous mode. This packet format is a packet composed of a 32-bit data string as shown in FIG. 2, and is composed of a header section 200 and a data section 300 like a normal packet.

In this format, the destination ID in the header section 200 is a number (ID) for identifying a destination device, and the source ID is a number (ID) for identifying a source device. Has become.

Further, a transaction label (tLabel)
Is a unique tag assigned to each unresolved transaction transmitted from the device, and is a number for associating a request packet with a response packet. Here, 6-bit data is used.

Further, a transaction code (tCode)
Is a code that specifies the format of the packet and the type of transaction that must be performed.
This code indicates the type of the packet, and indicates whether the transaction is read, write, or lock, and whether the transaction is a request packet or a response packet.

Rt indicates a retry code, and pri
Indicates priority. All of these are indispensable in the asynchronous packet format,
The description of the present invention is omitted because it is not important.

Each transaction can be identified as unique by the combination of the source ID of the requesting device, the destination ID of the responding device, and tLabel.

A case where the above-mentioned asynchronous type packets are mutually transmitted and received between devices connected by the IEEE 1394 bus will be described with reference to the system shown in FIG. 3 as an example.

In this system, as shown in FIG. 3, a plurality of data processing devices 110a and 110b
The data processing devices 110a and 110b are connected to the printers 120a and 120b.
b are connected to each other.

In each of the data processing devices 110a and 110b, MPUs 101a and 101b for performing data processing, hard disks 104a and 104b for recording data,
Hard disk controllers 103a and 103b for controlling the hard disks 104a and 104b, and printer controllers 102a and 102b for controlling the printers 120a and 120b are provided, respectively.

In the above system, when two data processing apparatuses 110a and 110b communicate with each other, a side requesting a process and a side executing the process are distinguished.

Data processing device 110a requesting processing
The MPU 101a in the device selects the data processing device 110b requesting the processing by the destination ID, specifies its own device by the source ID, specifies the transaction by the tCode, and writes the desired number to the tLabel to specify the number. And other header elements
Set rt (retry code) and pri (priority) according to the conditions and generate a request packet.

The request packet is put on the IEEE 1394 bus 130 by the MPU 101a, and is received by the MPU 101b in the data processing device 110b on the processing side.

After receiving the request packet, the data processing device 110b executes a process according to the content of the request packet, generates a response packet,
Via the 394 bus 130, the generated response packet is returned to the data processor 110a on the transmission side.

For example, one data processing device 110a
Transmits a read request packet for reading data stored in the hard disk 104b in the other data processing device 110b, the corresponding data processing device 1
When 10b receives the request packet, it reads the data in the hard disk 104b according to the instruction,
The result is returned as a response packet.

Data processing device 110b requested to process
If the side generates a response packet, there is an agreement that the number to be added to the tLabel of the response packet should be the same as the number of the tLabel of the request packet that requested the response packet, thereby receiving the response packet. When the data processing device 110a receives the response packet, the response packet is associated with the request packet, and the content thereof can be specified.

Then, the data processing device 110a, which has received the response packet, analyzes the content in association with the request packet by the MPU 101a, and transfers the content to the printer controller 102a when printing processing is to be performed.
The printer controller 102a transmits the print data to the print controller 105a in the printer 120a.
Print by a. On the other hand, in the case of data to be recorded, the data is transferred to the disk controller 103a and recorded on the hard disk 104a.

Thus, in the prior art system, M
The PU 101a analyzes the contents of the response packet and sends the response to the printer controller 102a or the disk controller 1a.
03a, etc., the MPU 10
1a also needs to perform some processing other than the response packet to be processed, and when the traffic increases, M
The load on the PU 101a was heavy.

[0023]

In the above conventional system, the second MPU 101b reads all the contents of the received request packet, and if the transaction of the request packet is to be processed by the MPU itself, the second MPU 101b itself. Processing must be performed, and if not, it must be transferred to a control circuit (printer controller or disk controller in the above example) that should perform the processing.

Therefore, when there are many request packets that do not require the processing of the MPU itself, there is a problem that the MPU is unnecessarily burdened and the processing speed of the data processing device is reduced.

The present invention has been made to solve the above-mentioned disadvantages of the prior art, and its object is to provide IEEE139
An object of the present invention is to provide a technique for reducing the load on the MPU of the data processing device connected to the four buses and increasing the processing speed.

[0026]

According to a first aspect of the present invention, there is provided a serial data bus having an arithmetic circuit and a control circuit and transmitting data in units of packets. After receiving the response data, the response data returned according to the content of the request data is received, and the response data is
A data processing device configured to be assigned to a control circuit that performs processing, a filter circuit to which the response data is input is provided, and when the response data is returned as the response data, a control circuit that performs the processing. A number is previously written in the request data at the time of transmission, and when the response data in which the number is described is input, the filter circuit should process the response data with reference to the number. The control circuit is configured to correspond to a control circuit and to distribute the response data to a control circuit to be processed without passing through the arithmetic circuit. The invention according to claim 2 is the data processing device according to claim 1, wherein, when the number described in the received response data indicates the arithmetic circuit, the filter circuit includes the response data. To the arithmetic circuit. The invention according to claim 3 is the data processing device according to any one of claims 1 and 2, wherein the control circuit includes a control circuit of a peripheral device. The invention according to claim 4 is the invention according to claim 1.
4. The data processing device according to claim 3, wherein a structure of the request data and a structure of the response data conform to an IEEE 1394 standard. The invention according to claim 5 is the data processing device according to claim 4, wherein the number is assigned to a position in a tLabel in a packet constituting request data.

According to the present invention, the data processing device transmits a request data packet (hereinafter, referred to as a request packet) and responds to the request data packet (hereinafter, referred to as a response packet). )), The filter circuit receives the response packet. If the response packet is to be processed by an arithmetic circuit such as an MPU, the response packet is output from the filter circuit to the arithmetic circuit and processed by other control circuits. If so, the filter circuit is configured to transfer the contents of the response packet to the control circuit that should perform the processing.

For this reason, the arithmetic circuit does not need to perform the above-mentioned distribution work at all, and such a distribution is performed by the MP.
As compared with the conventional case where the operation circuit such as U performs the operation, the load on the operation circuit is reduced and the processing speed of the operation circuit is improved.

In the IEEE 1394 standard, a request packet and a response packet are associated with each other by assigning the same number to a predetermined position (tLabel) in the packet. By associating that number with a control circuit that should process the response packet in advance, the above-described sorting process can be performed only by referring to that number.

[0030]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a system based on the IEEE 1394 standard. 1 includes a plurality of data processing devices (here, only two data processing devices 10a and 10b are shown) and a printer (here, two data processing devices 10a and 10b).
Only two printers 20a and 20b are shown. ) And an IEEE 1394 bus 30 which is a serial data bus.

In each of the data processing devices 10a and 10b,
MPUs 1a and 1b as arithmetic circuits, printer controllers 2a and 2b and disk controllers 3a and 3b as control circuits, and hard disks 4a and 4b are provided, respectively. Each controller 2a, 2b, 3a,
3b is connected to its own MPUs 1a and 1b, respectively, and is configured to be able to input and output data to and from the MPUs 1a and 1b.

In each of the data processing devices 10a and 10b,
Other circuits such as a storage circuit (not shown) are also provided, and each of the MPUs 1a and 1b can perform data processing such as numerical calculation and image processing using the circuits.

Each of the printers 20a and 20b has a print controller 5a, 5b and a print controller 5a, 5b.
b are provided with printing units 6a and 6b, respectively, and the print controllers 5a and 5b and the above-described printer controllers 2a and 2b are connected to the respective printers 20a and 20b.
outside of b, interconnected by a cable,
It is configured to input and output data necessary for printing.

When performing data processing and printing the result, each of the MPUs 1a and 1b first transmits data to be printed to the printer controllers 2a and 2b.
Printer controller 2a, 2b and print controller 5
a, 5b, and communicates with the print controllers 5a, 5b.
5b controls the printing units 6a and 6b, and prints the data processing result on a printing medium such as paper.

The hard disks 4a and 4b are connected to the disk controllers 3a and 3b, respectively. When the MPUs 1a and 1b perform data processing, the hard disks 4a and 4b of the own device are transmitted via the disk controllers 3a and 3b. It is configured to be able to input and output data processing results and data necessary for processing between the server and the server.

Further, in each of the data processing devices 10a and 10b, filter circuits 7a and 7b are provided, respectively, and the filter circuits 7a and 7b are connected to the IEEE 1394 bus 3 respectively.
0 and the MPUs 1a and 1b of the own device.
1a and 1b are configured to be able to transmit and receive data bidirectionally to and from the IEEE 1394 bus 30 via their own filter circuits 7a and 7b.

In communication using the IEEE 1394 bus 30,
It is determined that data transmission and reception are performed in packet units. For example, when one data processing device 10a sets the other data processing device 10b as a transmission destination and transmits a request packet, the MPU 1a as the transmission source A destination ID specifying the data processing device 10b of the transmission destination is selected, a source ID specifying the own device as a transmission source is selected, and a response is made in response to the request packet received by the data processing device 10b of the transmission destination. Set a specific tLabel to recognize the response packet and generate a request packet.

In this case, when each of the MPUs 1a and 1b receives the response packet, it knows in advance the contents of the processing to be performed on the response packet. Here, it is assumed that the processing contents can be classified into the following four processings A to D.

Process A: A case where the data processing by the MPU is not required even if the response packet is received, and the content of the request packet is written as it is to the hard disk built in the own device.

Process B: When the response packet is received and the data processing by the MPU is not required, and the content of the request packet is printed by the printer connected to the own device as it is.

Process C: A case other than processes A and B in which data processing by the MPU is not required even if a response packet is received.

Process D: When data processing of the received response packet is performed by the MPU, and then processing such as recording on a hard disk or outputting to a printer is performed. This process D is a process performed in all cases that do not correspond to the above processes A to C.

When transmitting a request packet, each of the MPUs 1a and 1b attaches a tLabel corresponding to the processing of a response packet to the request packet. Specifically, four types of processing A to D are provided. If there is a process, the upper two bits of tLabel are appended with “00” for process A, “01” for process B, and “10” for process C. In the case of the processing D, "11" is added.

Therefore, when tLabel is 6 bits, any one of "000000" to "001111" is added to the processing A, and similarly, "010000" to "0110" is applied to the processing B.
011111 ”, and“ 100,000 ”to“ 1 ”in process C.
01111 ”, and“ 110000 ”to“ 11 ”in the process D.
1111 ".

When actually transmitting a request packet, the header is determined by setting tCode and rt (retry code) and pri (priority), which are other elements of the header, and determine the header together with necessary data. After generating the packet, IE
The data is transmitted to the EE1394 bus 30.

The destination data processing device 10b receives the request packet via the filter circuit 7b,
A process corresponding to the content is executed. For example, if the received request packet is for reading specified data from the hard disk 4b, a read command is issued to the disk controller 3b to execute the processing.

When returning the data as a response packet, the data processing device 1 which is the transmission destination
0a, a source ID for specifying the data processing device 10b that is the reply source, and other t
Elements such as Code, rt, pri, etc. are attached, and a response packet is generated with the same tLabel as the tLabel of the request packet, and transmitted to the IEEE1394 bus 30.

In the data processing device 10a at the reply destination, unlike the prior art, the filter circuit 7a receives the response packet from the IEEE 1394 bus 30.

The filter circuit 7a is directly connected to its own printer controller 2a and disk controller 3 and a. When a response packet is received, its tLabel is analyzed, and only when the processing D requires processing by the MPU 1a. , Outputs the contents of the response packet to the MPU 1a, and does not output it to the MPU 1a in other cases.
Indicates the processing A, it is directly transferred to its own disk controller 3a, and if it indicates the processing B, it is directly transferred to its own printer controller 2a.

The disk controller 3a or the printer controller 2a that has received the contents of the response packet writes the data on the hard disk 4a or transmits the data to the printer 20a for printing. MPU1a will not be involved at all.

On the other hand, if it is determined that the packet indicates the process D, the contents of the response packet are output to the MPU 1a. After the necessary data processing is performed by the MPU 1a, the result is transmitted to the printer controller 2a or the like. It is output to the disk controller 3a and the like.

As described above, in the present embodiment, the processing contents of the response packet corresponding to the request packet are predicted, and the tLabel of the request packet is added according to the processing contents of the response packet. Therefore, since the response packet can be classified by tLabel, it is possible to transfer the response packet to the data processing device that executes the processing by a simple filter circuit.

Therefore, as compared with the prior art in which the MPU sorts the response packets, the load on the MPU is significantly reduced, and the processing performance of the data processing apparatus as a whole is improved.

In the above embodiment, a printer and a built-in hard disk have been described as examples of peripheral devices.
It goes without saying that peripheral devices are not limited to this.
Further, the association between tLabel and processing is not limited to the one shown in the above embodiment.

[0055]

As described above, according to the present invention, M
The load on an arithmetic circuit such as a PU can be reduced, and the processing speed can be improved.

Continued on the front page (72) Inventor Shoko Oda 3-6-12 Kitaaoyama, Minato-ku, Tokyo Fuji Aoyama Building Texas Instruments Japan Limited

Claims (7)

[Claims] A control circuit including an arithmetic circuit, for transmitting request data to a serial data bus for transmitting data in packet units, and processing the response data returned according to the request data by the control circuit; A data processing device, comprising: a filter circuit that receives the response data and sorts response data to be processed by the arithmetic circuit and response data to be processed by a control circuit other than the arithmetic circuit; A data processing device configured to transfer response data to be processed by the control circuit to a control circuit corresponding to the content without passing through the arithmetic circuit. 2. When the request data and the response data are associated with the same number assigned to data at a predetermined position in a packet, the number is previously associated with a specific control circuit. 2. The data processing apparatus according to claim 1, wherein the response data returned in response to the request data is assigned a number corresponding to a control circuit to be processed. 3. The data processing apparatus according to claim 1, wherein the number is associated with a specific control circuit by the arithmetic circuit. 4. The data processing device according to claim 1, wherein said control circuit includes a control circuit for a peripheral device. 5. The data processing apparatus according to claim 1, wherein the structure of the request data and the structure of the response data conform to the IEEE 1394 standard. 6. The data processing apparatus according to claim 5, wherein said number is assigned to a position within tLabel in the packet. 7. The data processing device according to claim 6, wherein the arithmetic circuit is an MPU that controls the data processing device.