JPH11205149A - Digital/analog converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DAC capable of preventing the situation of simultaneously selecting plural voltages, accurately selecting the voltage-and reducing power consumption. SOLUTION: Synchronized with loading signals, voltage selection signals D1-D6 are outputted from a data register DR2 and supplied to a decoder circuit DA1. However, inverted loading signals inverted by an inverter IN11 are supplied to the AND circuits AND1-AND64 of the decoder circuit DA1 and output is not performed from any AND circuits AND1-AND64 while the loading signals are at a high level. Thus, the switching control signals of the high level are prevented from being simultaneously supplied from the plural AND circuits AND1-AND64 to switching elements SW1-SW64. When the loading signals are returned to a low level, one of the AND circuits AND1-AND64 is turned ON, the corresponding one switching element SW is turned ON and the voltage (v) applied to one terminal of the switching element SW is selected and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter (hereinafter, referred to as DAC), and more particularly to a digital-to-analog converter suitable for a portion for selecting and outputting a liquid crystal driving voltage in a liquid crystal display panel.

[0002]

2. Description of the Related Art DACs are widely used to receive a selection signal of a plurality of bits in the form of a digital signal and to select and output a gradation voltage in the form of an analog signal. For example, in a CD (Compact Disc) reproducing apparatus, a DAC is used in a portion for selecting and outputting a corresponding voltage based on a digital signal recorded on a CD.

In a liquid crystal display panel, a DAC is used as a source driver for driving a liquid crystal.
FIG. 5 shows the configuration of the liquid crystal drive module. LCD screen 16
Is, for example, a thin film transistor (Thin Film Transistor,
In the TFT type, the gate of the TFT is turned on and off.
The gate driver 14 performs the off control, and the source driver 15 controls the voltage level supplied to the source of the TFT.

A gate driver 14 receives a horizontal synchronizing signal, a vertical synchronizing signal, and a clock from the screen synchronizing control circuit 12 for synchronizing the screen, and turns on the gates of the TFTs in order to scan the liquid crystal screen. The source driver 15 includes R, G, and B signals from the video signal processing circuit 11 to which a digital signal for determining a gradation voltage of an image output is input, a clock output from the screen synchronization control circuit 12, and a gradation voltage. The grayscale voltages V1 to V9 as analog signals generated by the generation circuit 13 are input, and any one of, for example, 64 grayscale voltages v1 to v64 as described later is selected and output to the source of the TFT.

FIG. 6 shows a configuration of the source driver 15. R and R as 6-bit digital signals output from the video signal processing circuit 11 are stored in the data register DR1.
The G and B signals and the clock output from the screen synchronization control circuit 12 are input, and the R, G and B signals are held. Then, a voltage selection signal as a digital signal of 6 bits is output from the data register DR1 in synchronization with the clock. The data register DR2 holds the voltage selection signal output from the data register DR1,
The signals are output to the DACs 1 to 309 in synchronization with the load signal.

The 64-segment resistor SR has a series resistor connected in series between a terminal to which the gray scale voltage V1 is input and a terminal to which the gray scale voltage V9 is input, and has nine stages of gray scale voltages V1. To V9 are input and 64 levels of gradation voltages v1 to v
Divide into 64. DACs 1 to 309 apply these voltages v1 to v
64, any one voltage v to be selected by a given voltage selection signal as a digital signal is output as an analog signal. The output voltage is amplified by output buffers OB1 to OB309 provided for each of the DAC1 to DAC309, and then is amplified.
The electric charge is applied to the source of the TFT disposed above and is accumulated in the capacitance of the liquid crystal pixel.

FIG. 7 shows a more detailed configuration of the conventional DAC1, data register DR2, 64-divided resistor SR, and output buffer OB1. Here, DAC1 includes a decoder circuit 1 and a switching circuit SW1. As described above, the 6-bit voltage selection signals D1 to D6 are output from the data register DR2 in synchronization with the load signal and supplied to the decoder circuit 1.

[0008] The decoder circuit 1 includes an inverting circuit RC and an AND circuit.
It has circuits AND1a to AND circuit AND64a. The inverting circuit RC generates signals / D1 to / D6 obtained by inverting the voltage selecting signals D1 to D6, respectively, and a total of twelve voltage selecting signals D1 to D6 and inverted voltage selecting signals / D1 to / D1.
/ D6. Then, the signals D1 to D6 and / D
1 to / D6 are each AND circuit AND1a
To AND64a. The 64-segment resistor SR is
As described above, the resistors R0 to R64 are connected in series between the power supply voltage VDD and the ground terminal Vss. Here, assuming that the power supply voltage VDD is the gradation voltage V1, the ground voltage Vss corresponds to the gradation voltage V9, and continuous voltages V2 to V8 are applied between them. Then, resistance-divided gradation voltages v1 to v64 are output from between the resistors R0 and R1, R1 and R2,..., R63 and R64, and applied to one ends of the switches SW1 to SW64. Switch SW1
The other end of SW64 is commonly connected to the input terminal of the output buffer OB1.

A conventional DAC having such a configuration is as follows.
It works as follows. The voltage selection signals D1 to D6 are held in the data register DR2, and when the load signals are input, they are output to the decoder circuit 1 in synchronization with this timing. In the decoder circuit 1, the voltage selection signals D1 to D6
Generates inverted signals D / 1 to / D6 from the signals D1 to D6.
6, six signals out of / D1 to / D6 are input to AND circuits AND1a to AND64a. Then, a switching control signal is output from one AND circuit, and a corresponding switch SW is turned on. After one of the voltages v is output as an analog signal via the switch SW and amplified by the output buffer OB1, Is output.

[0010]

However, the conventional DAC
Had the following problems. As shown in FIG.
Since the source driver 15 is disposed on one side of the liquid crystal screen 16, it tends to be mounted on a substrate that is elongated in one direction. Then, as shown in FIG.
9 is elongated in the vertical direction in the figure.

Therefore, the data register DR shown in FIG.
AND circuit AND1 from the output terminal of the inverting circuit RC
The lengths of the signal lines connected to the input terminals of “a” to “AND64a” largely differ depending on the respective AND circuits AND1a to AND64a. Therefore, the signals D1 to D64 and / D1 to / D64 are ANDed due to the difference in signal line length.
The delay time required to reach each of the circuits AND1a to AND64a differs.

Therefore, as shown in FIG.
When the load signal changes to a high level at the time when, for example, the switch SW1 is turned on, the SW64 selected in the previous cycle may be turned on at the same time until the time T2. That is, there is a period in which a plurality of AND circuits are simultaneously selected in the decoder circuit 1 and a plurality of switches SW are simultaneously turned on.
When such a phenomenon occurs, as shown in FIG.
Between the time T1 and T2, an intermediate potential between the voltages v1 and v64 is output. As a result, a voltage different from the selected original voltage v1 is output, and there is a problem that the liquid crystal panel cannot be normally driven. Further, by simultaneously turning on a plurality of switches SW,
When wasted power is consumed and a current that exceeds the current supply capability of the gray scale voltage input to the IC flows, the gray scale voltage fluctuates, causing a problem of image quality failure called crosstalk. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to prevent a situation in which a plurality of voltages are selected at the same time, to select a correct voltage, and to reduce a power consumption. The purpose is to provide.

[0014]

A DAC according to the present invention is a converter that receives a voltage selection signal, selects and outputs a corresponding voltage, and receives and holds the voltage selection signal.
A data register that outputs the voltage selection signal held when a load signal is input, and a different voltage is applied to one end of the data register, the other end is connected to a common output terminal, and a switching control signal is given to turn on / off. A plurality of switching elements to be controlled, the voltage selection signal output from the data register is given, performs a decoding process, outputs the switching control signal, and turns on one of the switching elements. A decoder circuit for outputting a voltage applied to one end of the switching element from the output terminal, wherein the decoder circuit outputs the switching control signal after a predetermined period of time from the input of the load signal. As a result, there is no period in which two or more of the switching elements are simultaneously turned on. It is characterized.

Here, the decoder circuit includes the same number of logic circuits as the number of the switching elements.
A predetermined number of the voltage selection signals of the voltage selection signal and the load signal are input, and the switching control signal is output to the corresponding switching element to perform on / off control. The switching control signal may not be output from any of the logic circuits until a predetermined period elapses after the input.

In addition, a plurality of resistors connected in series are further provided between the first power supply terminal to which the first voltage is applied and the second power supply terminal to which the second voltage is applied, The one end of each of the switching elements may be applied with a different voltage obtained by dividing a voltage difference between the first voltage and the second voltage by the resistor.

The DAC of the present invention is provided with a data register for receiving and holding a voltage selection signal and outputting the held voltage selection signal when a load signal is input, and a plurality of voltages and the voltage selection signal. And a decoder and a switching circuit for selecting and outputting any one of the voltages, wherein the decoder and the switching circuit are connected to one end to which any of the voltages are applied and a common output terminal. A plurality of switching elements connected in series between the end and the same number of switches as the number of voltages, the switch sections each including a predetermined number of voltage control signals of the voltage selection signal and the load signal; And given
Off is controlled, and after a predetermined period has elapsed after the load signal is input, all the switching elements included in any one of the switch units are turned on, and the voltage applied to the one end is reduced. By outputting from the output terminal, there is no period during which all of the switching elements included in at least two of the switching units are simultaneously turned on.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a DAC according to an embodiment of the present invention will be described with reference to the drawings. This embodiment is characterized in that a signal for preventing two or more voltages from being selected at the same time is input to a decoder circuit in synchronization with a timing to be selected.

DAC according to a first embodiment of the present invention
Has a configuration as shown in FIG. After the load signal input to the data register DR2 is inverted by the inverter IN11 as compared with the DAC shown in FIG.
64 is different. The same elements as those shown in FIG. 7 are denoted by the same reference numerals and description thereof will be omitted.

FIG. 3 shows a more specific circuit configuration example of the inverting circuit RC and the AND circuits AND1 to AND64 in the decoder circuit DA1. Voltage selection signals D1 to D6,
Inverted signals / D1 to / D6 generated by inverting circuit RC
Of these, D1, D2, D3, D
4, D5, and D6 signals are input, the / D1, D2, D3, D4, D5, and D6 signals are input to the AND circuit AND2, and D (not shown) is input to the AND circuit AND3.
1, / D2, D3, D4, D5, D6 signals are input,
The AND circuit AND4 has / D1, / D2, D3, D4,
D5 and D6 signals are input,..., AND circuit AND64
/ D1, / D2, / D3, / D4, / D5, / D6
A signal is input. Then, all the AND circuits AND1 to A
The inversion load signal is input to ND64. As described above, the AND circuits AND1 to AND64 have the voltage selection signals D1 to D6 and the inverted / D1 to / D inverted by the inverting circuit.
Six of the six signals are input, and a total of seven signals including an inverted load signal are input. Such a D
The operation in AC will be described with reference to the time chart of FIG.

When the load signal is input to the data register DR2, the held voltage selection signals D1 to D6 are output to the decoder circuit DA1. The signals / D1 to / D6 inverted by the inversion circuit RC are generated, and the voltage selection signal D
1 to D6 and 6 of / D1 to / D6 are AND circuits A
Input to ND1 to AND64. Further, the inverted load signal generated by the inverter IN11 is input to each of the AND circuits AND1 to AND64. FIG.
When the load signal changes to the high level from the time T1 to the time T2, the inverted load signal changed to the low level is input to all the AND circuits AND1 to AND64.
4 outputs only a low-level non-conduction control signal. Therefore, from the time point T1 to the time point T2, all the switching switches SW1 to SW64 are turned off. As a result, the wiring length from the output terminals of the data register DR2 and the inverting circuit RC to the input terminals of the AND circuits AND1 to AND64 is long, and a signal delay occurs, so that the switch 64 is still in the ON state at time T1. However, it is forcibly turned off from time T1 to T2.

When the load signal changes from the time T2 to a low level, the inverted load signal changes to a high level, so that one of the AND circuits AND1 to AND64 is selected, and the high-level conduction control signal is output. Is output. Thereby, the corresponding one switch SW
Is turned on, the selected gradation voltage v is output, amplified by the output buffer OB1, and output.

As described above, according to the present embodiment, all the selections are made so that two or more switches SW are not simultaneously turned on by using the load signal and two or more voltages are simultaneously selected. Are provided in a period T1 to T2. Thereby, the voltage selection signals D1 to D6, /
Even if a delay occurs in the inputs of D1 to / D6, it is possible to accurately select the voltage. In addition, wasteful power consumption due to simultaneous turning on of a plurality of switches SW can be prevented at the same time.

Here, as a signal for inhibiting simultaneous selection, a signal obtained by inverting the load signal is used, but another signal synchronized with the timing at which the decoder circuit DA1 takes in the voltage selection signals D1 to D6 is used. Has the same effect. However, since a general DAC always has a load signal that defines the timing of reading the selection signal, a circuit for generating a new signal is unnecessary by using this signal, and the length of the load signal period is adjusted. Even in this case, the circuit can be easily changed, and the circuit configuration can be simplified.

In the case of the liquid crystal driving IC, the load signal has a clock frequency of 40M between one clock and several clocks.
Hz, and one cycle, the level becomes high for 25 nsec. In contrast, one cycle in which one voltage is selected takes about 2 cycles.
0 μs. Therefore, even if none of the voltages is selected during the period when the load signal is at the high level, there is no hindrance to the operation of the liquid crystal panel and the like.

Next, D according to the second embodiment of the present invention will be described.
AC will be described. In this embodiment, the decoding operation of the decoder circuit DA1 in the first embodiment and the operation of the switch circuit SWC1 that performs switching based on the decoded and output switching control signal are combined into one circuit. FIG. 4 shows a configuration in this case.

Analog switches ASW11 to ASW formed by connecting drains and sources of P-channel type MOS transistors and N-channel type MOS transistors
17 are connected in series, and one end thereof has a gray scale voltage v1 generated by being divided by series resistors R0 to R64.
To v64, and the other end is connected to the input terminal of the output buffer OB1. Similarly, the analog switch elements ASW21 to ASW27 are connected in series, one end receives the voltage v2, and the other end is connected in common to the input terminal of the output buffer OB1,..., The analog switch elements ASW641 to ASW647 are connected in series. The voltage v64 is applied to one end, and the other end is commonly connected to the input terminal of the output buffer OB1.

Analog switches ASW11 to ASW17
Are connected to the gate of the P-channel MOS transistor and the gate of the N-channel MOS transistor, respectively.
And / D1, D2 and / D2, D3 and / D3, D4 and / D4, D5 and / D5, D6 and / D6, LOAD
And / LOAD signal are input. Analog switch A
P-channel MOS of each of SW22 to ASW27
The analog switches ASW12 to ASW12 are connected to the gate of the transistor and the gate of the N-channel MOS transistor, respectively.
Similar to SW17, only the analog switch ASW21 switches between the signal D1 and the signal / D1. Although not shown, the gates of the P-channel MOS transistors and the gates of the N-channel MOS transistors of the analog switches ASW31, ASW33 to ASW37 are not shown, but are not shown.
Analog switch ASW32 is similar to ASW17.
, The signal D2 and the signal / D2 are interchanged. Then, the analog switches ASW641 to ASW647
The gates of the channel type MOS transistor and the N-channel type MOS transistor have / D1 and D1,
/ D2 and D2, / D3 and D3, / D4 and D4, /
D5 and D5, / D6 and D6, LOAD and / LOA
The D signal is input.

As described above, in any column, the analog switch SWj7 to which the load signal LOAD and the inverted load signal / LOAD are input to the gate is connected in series. Therefore, in this embodiment, as in the first embodiment, while the load signal is at the high level,
Since all the analog switches SW17 to SW647 are turned off, none of the voltages v1 to v64 is selected, and a situation in which two or more voltages are simultaneously selected is avoided. Then, when the load signal LOAD changes to a low level, the voltage selection signals D1 to D6 and the inversion signals / D1 to / D6 cause the analog switches SWj1 to SWj in one row to be in one row.
7 (j is an integer of 1 to 64) are all turned on, the voltage v applied to one end of the analog switch SWj1 is selected, applied to the output buffer OB1 as an analog signal, and output after being amplified. .

Therefore, according to the present embodiment, as in the first embodiment, no voltage is selected while the load signal is at the high level, so that two or more voltages are selected at the same time. Therefore, it is possible to select an accurate voltage, and it is possible to prevent wasteful power consumption caused by turning on a plurality of switches SW at the same time.

The above embodiment is merely an example, and does not limit the present invention. For example, the configurations of the circuits illustrated in FIGS. 1, 3, and 4 are examples, and various modifications are possible. In each of the above embodiments, the case where a DAC is used in a portion for selecting a voltage for driving a liquid crystal is described as an example. However, the DAC of the present invention can be used for other applications. For example, the present invention can be applied to not only an image but also a part in which a digital signal in a sound reproducing apparatus is provided as a selection signal and a gray scale voltage is selected as an analog signal.

[0032]

As described above, according to the DAC of the present invention, a period in which no voltage is selected is provided for a predetermined period in synchronization with the timing of reading the voltage selection signal from the data register. Are not selected at the same time, it is possible to select an accurate voltage and to prevent wasteful power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a DAC according to a first embodiment of the present invention.

FIG. 2 shows a load signal and a switch SW1 in the DAC.
4 is a time chart showing a relationship between the ON state and the period in which the SW 64 is on.

FIG. 3 is a circuit diagram showing a detailed configuration of a decoder circuit in the DAC.

FIG. 4 is a circuit diagram showing a configuration of a DAC according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a liquid crystal display panel to which the present invention can be applied.

FIG. 6 is a block diagram showing a configuration of a source driver in the liquid crystal display panel.

FIG. 7 is a circuit diagram showing a configuration of a conventional DAC in the source driver.

FIG. 8 shows a load signal and a switch SW1 in the DAC.
4 is a time chart showing a relationship between the ON state and the period in which the SW 64 is on.

[Explanation of symbols]

 DR2 Data register D1 to D6, / D1 to / D6 Voltage selection signal IN1 to IN6, IN11 Inverter RC Inverting circuit AND1 to AND64 AND circuit R0 to R64 Series resistor SR 64 divider SWC1 Switching circuit SW1 to SW64 Switch OB1 Output buffer ASW11 ~ ASW647 Analog switch

Claims (5)

[Claims] 1. A digital-to-analog converter which receives a voltage selection signal, selects and outputs a corresponding voltage, receives and holds a voltage selection signal, and holds the voltage when a load signal is input. A data register for outputting a selection signal, a plurality of switching elements each having one end applied with a different voltage, the other end connected to a common output terminal, and being provided with a switching control signal and being controlled on / off; Given the voltage selection signal output from the data register, performs a decoding process, outputs the switching control signal, turns on one of the switching elements, the voltage applied to one end of the switching element And a decoder circuit for outputting the load signal from the output terminal, wherein the decoder circuit receives the load signal and After the inter periodically has elapsed, by outputting the switching control signal, a digital-to-analog converter, wherein the switching element is so there is no time to turn on at the same time two or more. 2. The decoder circuit according to claim 1, wherein the logic circuit includes the same number of logic circuits as the number of the switching elements. The logic circuit receives a predetermined number of the voltage selection signals from the voltage selection signals and the load signals, and the logic circuits correspond thereto. Outputting the switching control signal to the switching element to perform on / off control; and performing the switching control from any of the logic circuits until a predetermined period elapses after the load signal is input. 2. The digital-to-analog converter according to claim 1, wherein no signal is output. 3. A method according to claim 1, wherein a first power supply terminal to which a first voltage is applied and a second power supply terminal to which a second voltage is applied are provided.
The semiconductor device further includes a plurality of resistors connected in series, and the one end of each of the switching elements is applied with a different voltage obtained by dividing a voltage difference between the first voltage and the second voltage by the resistor. 3. The digital-to-analog converter according to claim 1, wherein: 4. A digital-to-analog converter that receives a voltage selection signal, selects and outputs a corresponding voltage, receives and holds a voltage selection signal, and holds the voltage when a load signal is input. A data register that outputs a selection signal; and a decoder and a switching circuit that receive a plurality of voltages and the voltage selection signal, and select and output one of the voltages. A switch unit in which a plurality of switching elements are connected in series between one end to which any of the voltages is applied and the other end connected to a common output terminal has the same number as the number of the voltages, and the switch The units are each supplied with a predetermined number of voltage control signals of the voltage selection signals and the load signal, and are controlled to be turned on and off. After a predetermined period of time has elapsed from the input of the signal, all the switching elements included in any one of the switch units are turned on and the voltage applied to the one end is output from the output terminal, so that at least A digital-to-analog converter wherein there is no period during which all of the switching elements included in the two switching units are simultaneously turned on. 5. A method according to claim 1, wherein a first power supply terminal to which the first voltage is applied and a second power supply terminal to which the second voltage is applied are provided.
The switch unit further includes a plurality of resistors connected in series, and the one end of each of the switch units receives a different voltage obtained by dividing a voltage difference between the first voltage and the second voltage by the resistor. The digital-to-analog converter according to claim 4, wherein: