JPH11204937A - Manufacture of substrate - Google Patents
Manufacture of substrateInfo
- Publication number
- JPH11204937A JPH11204937A JP2264498A JP2264498A JPH11204937A JP H11204937 A JPH11204937 A JP H11204937A JP 2264498 A JP2264498 A JP 2264498A JP 2264498 A JP2264498 A JP 2264498A JP H11204937 A JPH11204937 A JP H11204937A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- wiring pattern
- hole
- resist ink
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置に用いら
れるサブストレ−トの製造方法に関する。The present invention relates to a method for manufacturing a substrate used in a semiconductor device.
【０００２】[0002]
【従来の技術】半導体装置は高密度化、小型化を図る一
つの手段として、半導体チップを搭載するとともに外部
接続端子を設けるのにサブストレ−トが使用される。サ
ブストレ−トは配線パタ−ンを両面に設けるとともに、
穿設したスル−ホ−ル内に導電層を設け、該導電層を介
して前記両面の配線パタ−ンを適宜に電気的に接続して
いるもので、必要によっては多層にて用いられる。2. Description of the Related Art As a means for increasing the density and reducing the size of a semiconductor device, a substrate is used for mounting a semiconductor chip and providing external connection terminals. As for the sub-straight, wiring patterns are provided on both sides.
A conductive layer is provided in the perforated through hole, and the wiring patterns on both surfaces are appropriately electrically connected via the conductive layer. If necessary, the wiring pattern may be used in multiple layers.
【０００３】従来のサブストレ−トの製造においては、
銅箔を貼着した基板にスル−ホ−ルを穿設し、前記スル
ホ−ル内にめっきにより導電層を形成してから、前記導
電層の保護等のためにスル−ホ−ルにレジストインクを
充填し、その後、フォトレジストフィルムを基板に貼着
し、該フォトレジストフィルムに配線パタ−ンを焼付け
現像して、エッチングし配線パタ−ンを形成している。In the production of a conventional substrate,
A through hole is formed in a substrate to which a copper foil is adhered, a conductive layer is formed in the through hole by plating, and then a resist is formed on the through hole to protect the conductive layer. After filling the ink, a photoresist film is adhered to the substrate, a wiring pattern is baked on the photoresist film, developed, and etched to form a wiring pattern.
【０００４】[0004]
【この発明が解決しようとする課題】前記の方法では、
スル−ホ−ルに充填したレジストインクが基板の板面側
にはみ出すことが多々あり、その後、基板に配線パタ−
ンを形成するためにフォトレジストフィルムを貼着する
際に、密着不良を生じる。フォトレジストフィルムの密
着不良は、次いで形成する配線パタ−ンに形状劣化をも
たらし、サブストレ−トの信頼を損ない、また欠陥品と
なり製品歩留りが低下する。SUMMARY OF THE INVENTION In the above method,
The resist ink filled in the through-hole often protrudes to the plate surface side of the substrate, and then the wiring pattern is printed on the substrate.
Adhesion failure occurs when a photoresist film is adhered to form a pattern. Poor adhesion of the photoresist film causes a deterioration in the shape of the wiring pattern to be subsequently formed, impairs the reliability of the substrate, and results in a defective product, which lowers the product yield.
【０００５】また、従来の方法ではレジストインクを前
記スル−ホ−ルに充填後、薬液処理が必要となりレジス
トインクが侵されることがあり、引いては当該スル−ホ
−ルに形成している導電層が劣化し寿命が短くなる問
題、それに生産性が高まらない問題がある。In the conventional method, after the resist ink is filled in the through-hole, a chemical treatment is required and the resist ink may be eroded, so that the through-hole is formed. There is a problem that the conductive layer is deteriorated and the life is shortened, and there is a problem that productivity is not increased.
【０００６】本発明は配線パタ−ンを形状よく形成して
信頼性が高く、かつ製品歩留りよく、また、スル−ホ−
ルに充填しているレジストインクに不純物が付着して侵
されるようなことがなく長寿命化でき、さらに生産性の
高くサブストレ−トを得ることを目的とする。According to the present invention, a wiring pattern is formed in a good shape, so that the reliability is high, the product yield is good, and the wiring pattern is formed.
It is an object of the present invention to obtain a substrate that can be extended in life without causing impurities to adhere to and resist the resist ink filling the nozzle, and that has high productivity.
【０００７】[0007]
【課題を解決するための手段】本発明の要旨は、基板の
両面に配線パタ−ンを設け、基板に穿設したスル−ホ−
ルに導電層を設けたサブストレ−トの製造方法におい
て、基板に穿設したスル−ホ−ル内に導電層を形成し、
前記基板の板面にフォトレジストフィルムを設け、当該
フォトレジストフィルムに配線パタ−ンを焼付け現像
し、エッチングして配線パタ−ンを形成し、前記スル−
ホ−ルにレジストインクを充填することを特徴とするサ
ブストレ−トの製造方法にある。他の要旨は、前記スル
−ホ−ルにレジストインクを充填し次いで配線パタ−ン
にソルダ−レジストを塗布するところにある。SUMMARY OF THE INVENTION The gist of the present invention is to provide a wiring pattern on both surfaces of a substrate and to form a through hole on the substrate.
In a method of manufacturing a substrate in which a conductive layer is provided on a substrate, a conductive layer is formed in a through hole formed in a substrate.
A photoresist film is provided on the plate surface of the substrate, a wiring pattern is baked on the photoresist film, developed, and etched to form a wiring pattern.
A method for manufacturing a substrate, comprising filling a hole with a resist ink. Another object is to fill the through hole with a resist ink and then apply a solder resist to the wiring pattern.
【０００８】[0008]
【発明の実施の形態】本発明の１実施例について図面を
参照して説明する。図面において、１は基板で、例えば
ガラス繊維等をベ−スとしてＢＴ（ビスマレイミドトリ
アジン）レジン、エポキシ、又はポリイミド等を含浸さ
せた基板である。該基板１には両面に金属箔２例えば銅
箔が貼着されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings. In the drawings, reference numeral 1 denotes a substrate, for example, a substrate impregnated with BT (bismaleimide triazine) resin, epoxy, or polyimide based on glass fiber or the like. A metal foil 2, for example, a copper foil, is adhered to both sides of the substrate 1.
【０００９】３は前記基板１に穿設したスル−ホ−ル
で、レ−ザ−或はドリル等で形成される。該スル−ホ−
ル３の内壁面には図１の（ｂ）に示すように導電層４、
例えば銅めっきが無電解めっき、電解めっき等により形
成される。また、前記導電層４を形成する前に、めっき
付けをよくするためにスル−ホ−ル３の内壁面を溶すデ
スミア処理を施してもよい。Reference numeral 3 denotes a through hole formed in the substrate 1, which is formed by a laser or a drill. The sulfo-
As shown in FIG. 1B, the conductive layer 4
For example, copper plating is formed by electroless plating, electrolytic plating, or the like. Before the formation of the conductive layer 4, desmearing for melting the inner wall surface of the through-hole 3 may be performed to improve plating.
【００１０】次いで、基板１にフォトレジストフィルム
５を図１の（ｃ）のように貼着し、該フォトレジストフ
ィルム５に配線パタ−ンを焼付け、現像してフォトレジ
スト配線パタ−ン６を図１の（ｄ）のように形成する。Next, a photoresist film 5 is adhered to the substrate 1 as shown in FIG. 1C, and a wiring pattern is baked on the photoresist film 5 and developed to form a photoresist wiring pattern 6. It is formed as shown in FIG.
【００１１】続いて、エッチングを行って基板１に配線
パタ−ン７を図１の（ｅ）のように形成する。該配線パ
タ−ン７を形成した後、残存フォトレジストフィルムは
除去する。Subsequently, a wiring pattern 7 is formed on the substrate 1 by etching as shown in FIG. After the formation of the wiring pattern 7, the remaining photoresist film is removed.
【００１２】前記配線パタ−ン７を形成した後、スル−
ホ−ル３に前記導電層４の保護や該空所に湿気分等を滞
留させないようにレジストインク８を図１の（ｇ）に示
すように充填し、サブストレ−ト１０を製造する。該レ
ジストインク８は、その後、前記配線パタ−ン７上に塗
布するソルダ−レジストと同種のものを使用するのが生
産性を高める上から望ましい。After the wiring pattern 7 is formed, a through hole is formed.
The hole 3 is filled with a resist ink 8 as shown in FIG. 1 (g) so as to protect the conductive layer 4 and prevent moisture or the like from staying in the space, thereby producing a substrate 10. The resist ink 8 is preferably of the same type as the solder resist applied on the wiring pattern 7 from the viewpoint of improving productivity.
【００１３】また、その後、ソルダ−レジスト９を配線
パタ−ン７上の必要な箇所に塗布して、サブストレ−ト
１０を製造することができる。Thereafter, a solder resist 9 is applied to a necessary portion on the wiring pattern 7 to manufacture the substrate 10.
【００１４】この実施例では配線パタ−ン７を基板１の
両面に設けたサブストレ−ト１０について述べたが、本
発明はこれに限らず前記配線パタ−ンの上に絶縁材を介
在し更に配線パタ−ンを形成する多層配線サブストレ−
トの製造にも適用できる。In this embodiment, a description has been given of the substrate 10 in which the wiring pattern 7 is provided on both surfaces of the substrate 1. However, the present invention is not limited to this, and an insulating material is interposed on the wiring pattern. Multi-layer wiring substrate for forming wiring pattern
It can also be applied to the manufacture of
【００１５】[0015]
【発明の効果】本発明ではスル−ホ−ルにレジストイン
クを充填する前に、基板に配線パタ−ンを形成しフォト
レジストフィルムを貼着をするので、基板はきれいで当
該フォトレジストフィルムが貼着不良なく均一に密着
し、焼付け現像して形成されるフォレジスト配線パタ−
ンの形状精度がすぐれる。また、エッチングして形成さ
れる配線パタ−ンは当然形状がすぐれ、信頼性の高いサ
ブストレ−トが製品歩留りよく製造される。According to the present invention, before filling the through hole with the resist ink, the wiring pattern is formed on the substrate and the photoresist film is adhered to the substrate. A photoresist wiring pattern formed by uniform adhesion without sticking defects and baking development
The shape accuracy of the component is excellent. In addition, the wiring pattern formed by etching naturally has an excellent shape, and a highly reliable substrate can be manufactured with a high product yield.
【００１６】また、本発明ではスル−ホ−ルにレジスト
インクを充填後すぐソルダ−レジストを配線パタ−ン上
に塗布できるので、前記レジストインクへ不純物の付着
が防止され、当該レジストインクが侵されず導電層の劣
化がなく寿命が長くなるとともに、生産性がすぐれる。Further, according to the present invention, since the solder resist can be applied onto the wiring pattern immediately after the through-hole is filled with the resist ink, adhesion of impurities to the resist ink is prevented, and the resist ink is impregnated. In addition, the conductive layer is not deteriorated, the life is extended, and the productivity is excellent.
【図１】本発明の１実施例におけるサブストレ−トの製
造過程を示す図。FIG. 1 is a view showing a manufacturing process of a substrate in one embodiment of the present invention.
１ 基板 ２ 金属箔 ３ スル−ホ−ル ４ 導電層 ５ フォトレジストフィルム ６ フォトレジスト配線パタ−ン ７ 配線パタ−ン ８ レジストインク ９ ソルダ−レジスト １０ サブストレ−ト DESCRIPTION OF SYMBOLS 1 Substrate 2 Metal foil 3 Through hole 4 Conductive layer 5 Photoresist film 6 Photoresist wiring pattern 7 Wiring pattern 8 Resist ink 9 Solder resist 10 Substraight
Claims (3)
もに、穿設したスル−ホ−ルに導電層を設けたサブスト
レ−トの製造方法において、基板にスル−ホ−ルを穿設
し、前記スル−ホ−ル内に導電層を形成し、前記基板の
板面にフォトレジストフィルムを設け、当該フォトレジ
ストフィルムに配線パタ−ンを焼付け現像し、エッチン
グして配線パタ−ンを形成し、前記スル−ホ−ルにレジ
ストインクを充填することを特徴とするサブストレ−ト
の製造方法。In a method for manufacturing a substrate in which a wiring pattern is provided on both surfaces of a substrate and a conductive layer is provided on the perforated through hole, a through hole is perforated in the substrate. Forming a conductive layer in the through hole, providing a photoresist film on the surface of the substrate, baking and developing a wiring pattern on the photoresist film, and etching to form a wiring pattern; And a resist ink is filled in the through hole.
もに、穿設したスル−ホ−ルに導電層を設けたサブスト
レ−トの製造方法において、基板にスル−ホ−ルを穿設
し、前記スル−ホ−ル内に導電層を形成し、前記基板の
板面にフォトレジストフィルムを設け、当該フォトレジ
ストフィルムに配線パタ−ンを焼付け現像し、エッチン
グして配線パタ−ンを形成し、前記スル−ホ−ルにレジ
ストインクを充填し、前記配線パタ−ンにソルダ−レジ
ストを塗布することを特徴とするサブストレ−トの製造
方法。2. A method for manufacturing a substrate in which a wiring pattern is provided on both surfaces of a substrate and a conductive layer is provided on the perforated through hole. Forming a conductive layer in the through hole, providing a photoresist film on the surface of the substrate, baking and developing a wiring pattern on the photoresist film, and etching to form a wiring pattern; And filling the through hole with a resist ink and applying a solder resist to the wiring pattern.
塗布するソルダ−レジストが同質のレジストであること
を特徴とする請求項２記載のサブストレ−トの製造方
法。3. The method of claim 2, wherein the resist ink and the solder resist applied on the wiring pattern are of the same quality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264498A JPH11204937A (en) | 1998-01-19 | 1998-01-19 | Manufacture of substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264498A JPH11204937A (en) | 1998-01-19 | 1998-01-19 | Manufacture of substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11204937A true JPH11204937A (en) | 1999-07-30 |
Family
ID=12088567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2264498A Pending JPH11204937A (en) | 1998-01-19 | 1998-01-19 | Manufacture of substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11204937A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100511085B1 (en) * | 2001-08-10 | 2005-08-30 | (주)알티즌하이텍 | Print template fabricating system and fabricating method thereof |
-
1998
- 1998-01-19 JP JP2264498A patent/JPH11204937A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100511085B1 (en) * | 2001-08-10 | 2005-08-30 | (주)알티즌하이텍 | Print template fabricating system and fabricating method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Effective date: 20051019 Free format text: JAPANESE INTERMEDIATE CODE: A971007 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20051025 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060328 |