JPH11204803A - Manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a structure which can keep internal resistance low, if a high withstand voltage is provided. SOLUTION: A manufacturing material comprises step of selectively forming a first inorg. film (Si3 N4 film 6') on a control electrode leading layer (p<+> diffused layer 5) distant from an active region part connected to a control electrode layer (p<+> diffused layer 5), forming an n<-> type epitaxially grown single crystal layer 7 (first single crystal layer) on the active region part by the selective epitaxial growth and step of selectively forming a second inorg. film (Si3 N4 film 8) just above the single crystal layer 7 surface, and forming a single crystal layer (n<-> type epitaxially grown single crystal layer 9) on other part than the active region part. In this condition, the thickness t2 +t3 of a peripheral high- resistance Si layer concerning the withstand voltage is approximately twice the thickness t2 of the central active region part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static induction transistor (Stati-type transistor) having a buried gate structure.
The present invention relates to a method for manufacturing a semiconductor device in which a control electrode typified by c Induction Transistor (hereinafter, referred to as SIT) is embedded in a single crystal.

[0002]

2. Description of the Related Art Conventionally, in the case of manufacturing a semiconductor device of this kind, for example, an SIT, the procedure shown in FIG.
(H) are performed in accordance with the respective steps as shown in the side sectional views.

That is, first, as shown in FIG. 2A, the N ⁺ drain ohmic layer 2 of the first conductivity type is first used.
3, an N ⁻ drain ohmic layer 24 having a second conductivity type opposite to the first conductivity type is stacked on the semiconductor substrate.
As shown in FIG. 3B, a thermal oxide film 3 ′ made of a SiO ₂ film is formed on the surface on the N ⁺ drain ohmic layer 23 side, and the N ⁻ drain ohmic layer 24 on the opposite side is formed.
A patterned SiO ₂ film 14 is formed on the surface.

[0004] Next, as shown in FIG. 2 (c), N ^-
A stripe-shaped or mesh-shaped selective opening is formed on the surface of the drain ohmic layer 24 by a usual photolithography technique, and an impurity of the first conductivity type is diffused to form a P ⁺ diffusion layer (buried gate layer) as a control electrode layer. )
15 and P connected to it as a control electrode lead layer
^{+ A} diffusion layer (gate electrode layer) 15 'is formed.

Further, as shown in FIG. 2D, an N-type semiconductor single crystal is epitaxially grown on these control electrodes to form an N-type epitaxially grown single crystal layer 17 serving as a source layer, thereby embedding the control electrodes. it then, as shown in FIG. (e), the thermal oxide film 1 by the SiO ₂ film
8 is formed.

[0006] Subsequently, as shown in FIG.
After removing the thermal oxide film 18 by ordinary thermal oxidation and photolithography to partially open the control electrode layer, N
Only the opening is selectively removed by etching at a depth substantially equal to the thickness of the type epitaxial growth single crystal layer 17 to expose a local portion (P ⁺ diffusion layer 15 ′) of the control electrode portion.

Further, as shown in FIG. 2G, an N ⁺ source ohmic layer 19 is formed on the N-type epitaxially grown single crystal layer 17 by selective opening and impurity diffusion by thermal oxidation and photolithography. After that, a mesa etch groove V 'for forming a gate-drain PN junction structure is formed by selective etching,
Obtain the basic structure of

[0008] Finally, by forming an electrode metal film on each part by vacuum evaporation or sputtering using high-purity aluminum and separating each electrode metal film by photolithography, as shown in FIG. To
A structure having a drain electrode metal layer 21 on the N ⁺ drain ohmic layer 23 side, and a gate electrode metal layer 22 around the mesa etch groove V ′ and a source electrode metal layer 20 on the N ⁺ source ohmic layer 19 on the opposite side. As S
Complete IT. In this SIT, as shown in FIG. 2 (h), the outer peripheral portion A and the active region portion B have the same thickness t4 as the thickness of the semiconductor layer involved in the withstand voltage.

[0009]

In the above-mentioned SIT manufacturing method, the thickness of the semiconductor layer involved in the withstand voltage is the same in both the outer peripheral portion and the active region portion. Increasing the thickness in the hope of realization has a structural disadvantage that the internal resistance increases in proportion to the thickness.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a technical problem of the present invention is to provide a method of manufacturing a semiconductor device having a structure capable of maintaining a low internal resistance even when a withstand voltage is increased. It is in.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device having a structure in which a control electrode layer is embedded in a single crystal, wherein the control electrode layer is located at a position distant from an active region connected to the control electrode layer. Forming a first single crystal layer in the active region portion by selectively performing epitaxial growth after selectively forming a first inorganic film in the located control electrode lead portion; and forming a first single crystal layer in the active region portion. Selectively forming a second inorganic film immediately above the active region on the surface and then performing epitaxial growth to form a second single crystal layer in a portion other than the active region. Is obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings. FIG.
4A to 4I are side sectional views showing a procedure for manufacturing a buried gate type N-channel high power SIT according to an embodiment of the present invention for each process.

First, as shown in FIG. 1A, an N ⁺ silicon substrate of a first conductivity type having a ringer-doped plane orientation (111) having a specific resistance ρ of 0.002 Ωcm or less and a thickness of 300 μm is used. Source electrode layer) 1
As shown in FIG. 3B, SiC is used as a growth raw material.
An n-type epitaxially grown single crystal layer (source layer) 2 having a thickness of t1 is formed by epitaxial growth at 1200 ° C. using H ₂ as a carrier gas while using l ₄ . The N-type epitaxially grown single crystal layer 2 here is
The specific resistance is 4 Ωcm, and the thickness t ₁ is set to 20 μm.

Next, as shown in FIG. 1 (c), the substrate in the previous step of FIG. 1 (b) is subjected to thermal oxidation in a wet O ₂ atmosphere at a temperature condition of 1100 ° C. for 15 minutes.
After forming a thermal oxide film 3 of a SiO ₂ film on the entire surface of the monocrystalline epitaxial growth single crystal layer 2, a negative type photoresist is spin-coated with a thickness of about 1 μm on the thermal oxide film 3 and preheated to form a gap. 2μm, pitch 10μ
A negative photoresist layer 4 is formed as an m-stripe resist pattern.

Further, as shown in FIG. 1 (d), the substrate in the previous step of FIG. 1 (c) is etched with a normal SiO ₂ etching solution (6-4 barfured hydrofluoric acid; 6-4BHF). The thermal oxide film 3 is selectively opened with a width of 2 μm, and P ² -type impurity diffusion is performed on the opening with a width of 2 μm using BCl ₃ as a diffusion source, thereby forming a P ⁺ diffusion layer (buried gate layer) as a control electrode layer. 5 and P connected to it as a control electrode lead-out layer
⁺ Diffusion layer (gate electrode layer) 5 'is formed. Here, the diffusion temperature was 1100 ° C., and a general open-tube gas diffusion source diffusion was used as the diffusion method.

Subsequently, as shown in FIG.
The substrate in the previous step of FIG. 4D is subjected to Si ₃ N ₄ on the N-type epitaxial growth single crystal layer 2 side at a temperature of 750 ° C. using SiH ₂ Cl ₂ and NH ₃ as source gases by an LP-CVD apparatus. After the entire surface of the film is formed, only the outer peripheral portion on the gate electrode layer 5 'is formed by the usual photolithography technique.
The i ₃ N ₄ film 6 ′ is left. In addition, Si ₃ N ₄
At the time of selective etching of the film, an SiO ₂ film (source gas SiH ₄ ,
Temperature condition of 350 ° C.) and H ₃ as an etching solution.
Processing was performed at a temperature of 180 ° C. using PO ₄ (hot phosphoric acid).

As shown in FIG. 1 (f), an N-type epitaxially grown single crystal excluding the Si ₃ N ₄ film 6 'using SiCl ₄ as a raw material is formed on the substrate in the previous step of FIG. 1 (e). The surface on the layer 2 side is epitaxially grown to form an N ⁻ -type epitaxially grown single crystal layer (drain layer) 7. The N ^- type epitaxially grown single crystal layer 7
Has a specific resistance ρ of 70 to 100 [Ωcm] and a thickness t
₂ is set to 50 μm. The feature of this process is
The point is that the N ⁻ -type epitaxially grown single crystal layer 7 is not grown on the Si ₃ N ₄ film 6 ′, but is grown on the other active region, and selectively epitaxially grown.

That is, the steps up to this point are the control electrode layer (P
⁺ A control electrode lead layer (P ⁺ diffusion layer 5 ′) located at a position away from the active region connected to the diffusion layer 5);
After selectively forming the inorganic film (Si ₃ N ₄ film 6 ′)
Epitaxial growth is selectively performed to form a first region in the active region.
(N ^- type epitaxially grown single crystal layer 7).

Furthermore, as shown in FIG. 1 (g), to the substrate of the previous step in FIG (f), N ^- -type epitaxial growth above the active area corresponding portions directly above on the single crystal layer 7 Then, a Si ₃ N ₄ film 8 is formed in the same manner as the above.

Subsequently, as shown in FIG.
With respect to the substrate in the previous step of FIG. 8G, the specific resistance ρ of the portion other than the Si ₃ N ₄ film 8 on the N ⁻ -type epitaxially grown single crystal layer 7 is 70 as in the case of FIG. ~ 100 [Ω
cm] and a thickness t ₃ of 50 μm, and an N ⁻ -type epitaxially grown single crystal layer (drain layer) 9 is selectively grown by epitaxial growth.

That is, in the steps so far, the second inorganic film (Si ₃ N ₄ film 8) is selected just above the active region on the surface of the first single crystal layer (N ⁻ -type epitaxially grown single crystal layer 7). Then, the second single crystal layer (N ⁻ -type epitaxially grown single crystal layer 9) is formed in a portion other than the active region by epitaxial growth. In this state, the thickness t of the high-resistance silicon layer at the outer peripheral portion which is involved in the withstand voltage.
₂ + t ₃ is about 2 times larger than the thickness t ₂ of the central active region.
Double it.

Further, as shown in FIG. 1 (i), the substrate in the previous step of FIG. 1 (h) is immersed in hot phosphoric acid on the entire surface and the Si ₃ N ₄ film 6 ′ and the Si ₃ N ₄ After removing the membrane 8,
After forming a SiO ₂ film by the same thermal oxidation as described above, an N ⁺ ohmic diffusion layer (drain ohmic layer) 10 is selectively formed by diffusion using a normal photolithography technique. A mesa etch groove V for completing the drain-to-drain PN junction is formed by selective etching to obtain a basic structure of SIT. The mesa-etch groove V is formed by a mixed solution of hydrofluoric acid and nitric acid (HF: HNO ₃ =
1: 5 vol. %) To completely reach the N ⁺ silicon substrate 1.

Finally, as shown in FIG. 1 (j), high purity aluminum of 99.999% or more or aluminum containing 1% silicon is used for the substrate in the previous step of FIG. 1 (i). By forming an electrode metal film in each part with a thickness of 2 to 3 μm by vacuum evaporation or sputtering and separating each electrode metal film by a photolithography method, the source electrode metal layer 11 is formed on the N ⁺ silicon layer 1 side.
The SIT is completed as a structure having the gate electrode metal layer 13 around the mesa etch groove V and the drain electrode metal layer 12 on the N ⁺ ohmic diffusion layer 10 on the opposite side.

Incidentally, an organic or inorganic passivation film such as a junction coating resin or lead glass is formed on the silicon surface of the outer peripheral portion A including the mesa-etch groove V, which is used for manufacturing a general power semiconductor device. This is the same operation as in the case of

The SIT manufacturing process has been described above. Compared with the conventional method described with reference to FIGS. 2A to 2H, the SIT obtained by the conventional method is shown in FIG. As described above, the peripheral portion A involved in the withstand voltage and the active region portion B involved in the operation were the same in thickness t ₄ , but in the case of the SIT obtained here, the thickness of the active region portion B was reduced to the outer peripheral portion. In this structure, when the withstand voltage is set to be the same, the value of the internal resistance R _on is reduced to about a half and the loss is improved with this structure.

In the case of the SIT having the structure obtained in one embodiment,
Specific examples of the characteristics include a gate-drain withstand voltage V _GD of 1700 V and a gate-source withstand voltage V _GS of 15
0V, source-drain blocking voltage V _DSX is 1700
V, the internal resistance R _on is 0.6Ω. In contrast, in the case of the SIT having the structure obtained by the conventional method, the value of the internal resistance R _on is 1 even if other characteristics are the same. .
It becomes as high as 0 to 1.2 [Ω].

In the embodiment, the case of manufacturing a buried gate type N-channel high power SIT has been described.
The present invention can be applied to other semiconductor devices such as a surface gate type or P-channel SIT, and not only SIT but also a power semiconductor device such as a bipolar transistor (BJT), a MOS type FET, or a thyristor. However, in any of the semiconductor devices, as shown in FIG. 1 (j), the thickness (t ₂ + t ₃ ) of the semiconductor layer in the outer peripheral portion A involved in the withstand voltage is increased to affect the internal resistance. It may be structured to reduce the thickness t ₂ in the active area B, for a high voltage resistance low resistance.

[0028]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the thickness of the semiconductor layer in the outer peripheral portion A involved in the withstand voltage is increased, and the thickness of the active region involved in the internal resistance is increased. Since the thickness is reduced, a structure that can maintain a low internal resistance even when the withstand voltage is increased is realized.

[Brief description of the drawings]

FIGS. 1A to 1J are side sectional views showing a procedure for manufacturing a buried-gate N-channel high-power SIT according to an embodiment of the present invention for each process.

FIGS. 2A to 2H are side sectional views showing a procedure for manufacturing a conventional SIT for each process.

[Explanation of symbols]

1 N ⁺ silicon substrate 2, 17 N-type epitaxial single crystal layers 3, 18 thermal oxide film 4 negative photoresist film 5,5 ', 15,15' P ⁺ diffusion layer 6 ', 8 Si ₃ N ₄ film 7, 9 N ⁻ -type epitaxially grown single crystal layer 10 N ⁺ -type ohmic diffusion layer 11, 20 Source electrode metal film 12, 21 Drain electrode metal film 13, 22 Gate electrode metal film 14 SiO ₂ film 19 N ⁺ Source ohmic layer 23 N ⁺ Drain ohmic layer 24 N ^- drain layer A peripheral portion B active area V, V 'mesa etch grooves

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device having a structure in which a control electrode layer is embedded in a single crystal, wherein a control electrode lead layer located away from an active region connected to the control electrode layer has A step of selectively performing epitaxial growth after selectively forming the first inorganic film to form a first single-crystal layer in the active region, and a step of immediately above the active region on the surface of the first single-crystal layer. Forming a second single-crystal layer in a portion other than the active region portion by selectively forming a second inorganic film and then performing epitaxial growth.