JPH11204752A - Capacitor comprising lower electrode having irregular surface and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure surface resistance capable of functioning as a resistance layer, by a method wherein a lower electrode having an irregular surface, and an upper electrode comprising a dielectric film and a plurality of conductive films having different concentrations of impurities are sequentially formed on a semiconductor substrate. SOLUTION: A HSG silicon layer 64 is formed in order to increase a surface area on a surface of a lower electrode 62, and a dielectric layer 65 is formed on the upper part. Upper electrodes 68, 70 are formed on the dielectric layer 66. A lower layer coming into contact with a dielectric film 66 is formed of a doped conductive film at high concentration since a thickness of a depletion layer formed between the upper electrode and the dielectric film is reduced to increase capacitance, and further of a doped conductive film at low concentration as rising toward the upper layer since it is used as a resistance layer of a circumferential circuit region. Accordingly, it is possible to secure surface resistance functioning sufficiently as a resistance layer in the circumferential region. In other words, capacitance is increased without using a complicated structure and secure the sufficient surface resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor for a semiconductor memory device and a method of manufacturing the same, and more particularly, to a capacitor having an increased capacitance and a specific resistance having a lower electrode having an uneven surface and a method of manufacturing the same.

[0002]

2. Description of the Related Art Recently, a process of increasing the surface area of an electrode by growing a so-called hemi-spherical grain (HSG) on the surface of a lower electrode in order to easily increase the effective area of a capacitor. Has been developed and is receiving attention. The method of forming the HSG includes:
This is a method of increasing the surface area of the electrode using a kind of surface movement mechanism, that is, surface movement of silicon. This technique changes the amorphous silicon of a certain thickness to crystalline silicon, thereby causing surface bending and increasing the surface area.

A method of manufacturing a capacitor using a conventional HSG silicon layer will be briefly described with reference to FIG.

Referring to FIG. 1A, a lower electrode connected to an active region of a transistor (not shown) is formed on a semiconductor substrate 10 on which a lower structure such as a transistor (not shown) and an interlayer insulating film 12 are formed. Forming conductive layer 14 is formed. In order to further increase the surface area, the lower electrode conductive layer 14 may be formed, for example, in a cylindrical shape, and the forming method is well known. Next, a blank HSG, that is, an HS deposited regardless of the quality of the lower film, is formed on the resultant having the lower electrode conductive layer 14 formed thereon using a predetermined method.
A G silicon layer 16 is formed.

Referring to FIG. 1B, in order to prevent a short circuit from occurring between adjacent cells due to the HSG silicon layer 16, an insulation is provided on the resultant to cover the cylinder. Form a film. Next, when the insulating film is anisotropically etched, spacers 18 are formed on the inner and outer walls of the cylinder as shown. Subsequently, the spacer 18
Formed as a mask between adjacent cells by using
Etch the SG silicon layer. Thereafter, when the spacer is removed, a cylindrical lower electrode having an uneven surface is completed.

When the surface of the lower electrode of the capacitor is deformed in a concavo-convex manner by the above-mentioned conventional method, the surface area of the lower electrode is increased, and the cell capacitance is increased.

However, since the dielectric film and the upper electrode to be deposited later are also deposited along the bending, the surface where the upper electrode is in contact with the dielectric film also becomes uneven. Therefore, when a positive voltage is applied to the upper electrode having such an uneven surface, an electric field concentration phenomenon in which the electric field is concentrated occurs as compared with the case where the surface is flat, and the electric field received by the electrons in the upper electrode is large. Become.

Therefore, according to the following equation 1, the depletion layer generated in the upper electrode becomes thicker. Increasing the thickness of the depletion layer reduces the capacitance due to the depletion layer according to Equation 2, and eventually,
This results in a reduction in the overall capacitance as shown in equation 3.

[0009]

(Equation 1)

[0010]

(Equation 2)

[0011]

(Equation 3)

In the above formulas 1, 2, and 3, C _tot
Is the total capacitance, C ₀ is the capacitance due to the dielectric film, C _d is the capacitance due to the depletion layer, X _d is the thickness of the depletion layer, ε ₀ is the dielectric constant of the dielectric film, ε _si is the dielectric constant of silicon, and A is the capacitor. effective area, V _G is the applied voltage,
q is the electron charge quantity, N _a are respectively the number of impurities.

As a method for solving the problem that the capacitance decreases when a positive voltage is applied to the upper electrode, a method of increasing the impurity concentration of the upper electrode to reduce the thickness of the depletion layer is known. is there. However, this method will reduce the resistance of the upper electrode.

Therefore, the role of the upper electrode used as a resistive layer in the peripheral circuit region in a normal semiconductor memory element as a resistive layer is hindered.

The resistive layer used for the memory element is used for a circuit in a peripheral circuit area, but is mainly used for a voltage generator and an RC delay, and requires a resistance value of about several kΩ at the maximum. . In short, the resistance layer should have a certain level or more of sheet resistance. Generally, sheet resistance tends to be inversely proportional to thickness and proportional to specific resistance.

Accordingly, when the impurity concentration of the upper electrode is increased, the specific resistance of the upper electrode is reduced as shown in FIG. 2 to have a sheet resistance below a desired level.

FIG. 2 is a graph showing the relationship between the impurity concentration and the specific resistance. Curve A shows the case of boron and curve B shows the case of phosphorus.

That is, the impurity concentration of the upper electrode of the capacitor should be determined within a range that can simultaneously satisfy two contradictory objectives of reducing the thickness of the depletion layer and increasing the sheet resistance to a certain level or more. is there.

As a method for satisfying the above-mentioned object, a high-concentration upper electrode is formed to reduce a depletion layer, thereby ensuring a certain level of capacitance when a positive voltage is applied, and used as a resistance layer when patterning the upper electrode. There is a method of securing the sheet resistance to a certain level or more by reducing the thickness of the portion. However, this method has a disadvantage in that it must be directly limited by the limitations of the patterning technology, so that only an effect at the level of the development of the patterning technology can be obtained.

[0020]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a lower electrode having an uneven surface and to serve as a resistance layer while securing a cell capacitance at a certain level or more. An object of the present invention is to provide a capacitor of a semiconductor memory device having an upper electrode having a sheet resistance.

Another object of the present invention is to provide a method suitable for manufacturing the capacitor.

[0022]

According to the present invention, there is provided a semiconductor memory device having a capacitor formed on a semiconductor substrate and having a lower electrode having an uneven surface, and a capacitor formed on a surface of the lower electrode. And an upper electrode formed on the dielectric film and formed of a plurality of conductive films having different impurity concentrations.

The lower electrode comprises a conductive film pattern of polysilicon doped with impurities, and a hemispherical grain silicon (HSG silicon) layer formed on the surface of the conductive film pattern.

The impurity concentration of the upper electrode composed of the plurality of conductive films decreases from the lowermost conductive film formed on the dielectric film to the uppermost conductive film.

The upper electrode is formed on the upper electrode, and a first conductive film doped with an impurity at a concentration capable of minimizing a thickness of a depletion layer formed between the upper electrode and the dielectric film;
A second conductive film formed on the first conductive film and doped with an impurity at a concentration capable of maintaining a resistance value suitable for the upper electrode to function as a resistance layer in a peripheral circuit region.

The first conductive film has an impurity of 1 × 10 ²⁰ atoms.
/ cm ² or more, and the second conductive film is 1 ×
Desirably, the doping is less than 10 ²⁰ atoms / cm ² .

At this time, the impurity is P or As, and the thickness of the first conductive film is 50-500.
Å is desirable.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor memory device, comprising: forming a lower electrode of a capacitor having an uneven surface on a semiconductor substrate; Forming an upper electrode comprising a plurality of conductive films having different impurity concentrations on the dielectric film.

The step of forming the lower electrode includes the steps of: forming a conductive film pattern defined on a cell-by-cell basis on the semiconductor substrate; and forming a hemisphere on the surface of the conductive film pattern by using surface movement of silicon. Forming an HSG silicon layer having a grain shape to form an uneven surface.

The step of forming the upper electrode may include forming an impurity on the entire surface of the resultant structure on which the dielectric layer is formed with a concentration that can minimize the thickness of a depletion layer formed between the dielectric layer and the dielectric layer. And a step of forming a second conductive film doped with an impurity at a lower concentration than the first conductive film.

Preferably, the concentration of the impurity in the second conductive film is a concentration that can maintain a resistance value suitable for the upper electrode to function as a resistance layer in a peripheral circuit region.

The impurity concentration of the first conductive film is 1 × 10
Preferably, the concentration is ²⁰ atoms / cm ² or more, and the impurity concentration of the second conductive film is less than 1 × 10 ²⁰ atoms / cm ² .

Further, the impurity is P or As, and the thickness of the first conductive film is 50 ° to 500 °.
It is desirable that

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to the attached drawings. In the following embodiments, a capacitor over bit line (COB) structure will be referred to for describing the present invention.
However, the present invention can be applied to any structure other than the COB structure as long as the capacitor has an uneven lower electrode.

FIG. 3 is a cross-sectional view illustrating a semiconductor memory device having a capacitor having an uneven lower electrode according to an embodiment of the present invention.

Referring to FIG. 3, a hemispherical crystal, ie, HS, is formed on the surface of the lower electrode 62 to increase the surface area.
A G silicon layer 64 is formed. A dielectric film 66 is formed thereon. Upper electrodes 68 and 70 are formed on the resultant structure on which the dielectric film is formed.
The upper electrode includes a first polysilicon film 68 doped with impurities at a high concentration, for example, 1 × 10 ²⁰ atoms / cm ² or more;
The upper electrode is composed of a second polysilicon film 70 doped with an impurity capable of maintaining a predetermined resistance value, for example, an impurity of less than 1 × 10 ²⁰ atoms / cm ² . At this time, the first
The thickness of the polysilicon film 68 is desirably 50 ° to 500 °.

The upper electrode may be formed as a two-layer structure as shown, or a multilayer structure having three or more layers. At this time, the dielectric film 6
The lower layer in contact with 6 is formed of a heavily doped conductive film in order to reduce the thickness of the depletion layer formed between the upper electrode and the dielectric film and increase the capacitance.
Then, in order to use it as a resistive layer in the peripheral circuit region, a conductive film doped with a lower concentration toward the upper layer is formed.

In FIG. 3, reference numerals 40 to 58 are
2 shows a structure formed below a capacitor. Specifically, 40 is a semiconductor substrate, 42 is a field oxide film, 44 is a gate insulating film, 46 is a gate electrode, 47 is an insulating film, 48 is a spacer, 50 and 52 are pad electrodes, 54
Denotes a first interlayer insulating film, 56 denotes a bit line, and 58 denotes a second interlayer insulating film.

Next, a method of manufacturing a semiconductor memory device having a capacitor having an uneven lower electrode according to an embodiment of the present invention will be described with reference to FIGS. 4A to 5D.

Referring to FIG. 4A, the semiconductor substrate 40
A field oxide film 42 for separating an active region and an inactive region is formed thereon by using a usual method. An oxide film, a conductive film, and an oxide film are sequentially stacked on the semiconductor substrate 40, and then patterned to form a gate pattern including a gate insulating film 44, a gate electrode 46, and an insulating film 47. Next, a spacer 48 is formed on the side wall of the gate pattern by, for example, depositing an oxide film on the entire surface of the resultant structure and performing etch back. Then, after depositing an impurity-doped polysilicon film on the entire surface of the resultant product, the polysilicon film is patterned to connect the bit line to the active region of the semiconductor substrate and the lower electrode to the active region of the semiconductor substrate. The pad electrodes 50 and 52 are formed.

Referring to FIG. 4B, the pad electrode 5
An insulating material, for example, a silicon oxide film is deposited on the entire surface of the resultant structure having the layers 0 and 52 to form an interlayer insulating film 54.
Next, a contact hole exposing a part of the pad electrode 50 connected to the bit line is formed by patterning the interlayer insulating film 54. Subsequently, a bit line 56 connected to the pad electrode 50 is formed by depositing a polysilicon layer doped with impurities on the entire surface of the resultant structure and patterning the deposited polysilicon layer. The bit lines 56 are formed in a direction perpendicular to the word lines.

Next, an insulating material, for example, a silicon oxide film is deposited on the entire surface of the resultant structure to form an interlayer insulating film 58.
Next, by patterning the interlayer insulating film 58, the pad electrode 52 connected to the lower electrode of the capacitor is formed.
Is formed to expose a part of the contact hole.

Referring to FIG. 5C, an impurity-doped polysilicon film is deposited on the entire surface of the resultant structure in which the contact hole 60 is formed, and then the polysilicon film is patterned by a photolithography process. By
A lower electrode pattern 62 is formed. Next, contamination and a native oxide film on the surface of the semiconductor substrate are removed through a wet cleaning and etching process. Subsequently, irregular crystal grains, that is, an HSG silicon layer 64 is formed on the surface of the lower electrode pattern 62 by using a conventional method to increase the surface area of the lower electrode.
The HSG silicon layer 64 is formed of, for example, silane (SiH ₄ ) and disilane (S) in a high vacuum chamber of 10 ⁻⁶ torr or less.
i ₂ H ₆ ) gas, and the height is about 100 to
1000 ° is desirable.

Referring to FIG. 5D, the semiconductor substrate on which the HSG silicon layer 64 is formed is again wet-etched to remove contaminants and natural oxide films on the surface, and then a dielectric material is applied to the entire surface of the resultant structure. The dielectric film 66 of the capacitor is formed by vapor deposition.

Next, a conductive film is deposited on the resultant having the dielectric film 66 formed thereon to form plate electrodes 68 and 70. At this time, impurities such as phosphorus or arsenic are 1 × 1
A first polysilicon film 68 doped with a high concentration of 0 ²⁰ atoms / cm ² or more is deposited to a thickness of about 50 to 500 Å, preferably 200 Å. Next, a concentration at which the upper electrode can maintain a predetermined resistance value, for example, 1 × 10
The second polysilicon film 70 doped with an impurity at a concentration of less than ²⁰ atoms / cm ² is continuously deposited to form an upper electrode made of a double polysilicon film.

In this case, since the lower region of the upper electrode in contact with the dielectric film is heavily doped with impurities, the depletion layer becomes thinner and the capacitance of the capacitor increases. Since the impurity is formed at a lower concentration in the upper region of the upper electrode than in the region that comes into contact with the dielectric film, the region functions sufficiently as a resistance layer in the peripheral circuit region.

[0047]

According to the above-described capacitor having the uneven lower electrode and the method of manufacturing the same according to the present invention, when forming the upper electrode of the capacitor, a polysilicon film doped with a high concentration of impurities is deposited first. Thereafter, a polysilicon film having a lower concentration is deposited to form a double polysilicon film. As a result, since the upper electrode is heavily doped at the portion where the dielectric film and the upper electrode are in contact, the depletion layer becomes thinner and the capacitance of the capacitor increases. In this case, since a low-concentration polysilicon film is formed, it is possible to secure a sheet resistance that can sufficiently serve as a resistance layer in the peripheral circuit region. That is, the capacitance of the capacitor can be increased and a sufficient sheet resistance can be ensured without using a complicated structure and process.

Although the present invention has been described in detail above, it is apparent that the present invention is not limited to the above embodiments, and that many modifications can be made by those skilled in the art within the technical idea to which the present invention belongs.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method of manufacturing a capacitor using a conventional HSG silicon layer.

FIG. 2 is a graph showing a relationship between an impurity concentration of an upper electrode and a specific resistance.

FIG. 3 is a cross-sectional view illustrating a semiconductor memory device including a capacitor having an uneven lower electrode according to an embodiment of the present invention;

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device having a lower electrode having an uneven surface according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step subsequent to FIG. 4;

[Explanation of symbols]

 Reference Signs List 40 semiconductor substrate 42 field oxide film 44 gate insulating film 46 gate electrode 47 insulating film 48 spacer 50, 52 pad electrode 54 first interlayer insulating film 56 bit line 58 second interlayer insulating film 62 ... lower electrode 64 ... HSG silicon layer 66 ... dielectric film 68 ... first polysilicon film (upper electrode) 70 ... second polysilicon film (upper electrode)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Park Yui Asahi No. 703, Building No. 301, Lin Gwang-dong, 1115, Gesan-dong, Dong'an-gu, Anyang-si, Gyeonggi-do, Republic of Korea

Claims (14)

[Claims] A lower electrode having an uneven surface formed on a semiconductor substrate; a dielectric film formed on a surface of the lower electrode; and a different impurity concentration formed on the dielectric film. And a top electrode comprising a plurality of conductive films. 2. The semiconductor device according to claim 1, wherein the lower electrode includes a conductive film pattern made of polysilicon doped with impurities and a silicon layer having hemispherical grains formed on a surface of the conductive film pattern. The capacitor of a semiconductor memory device according to claim 1, wherein 3. An upper electrode comprising a plurality of conductive films,
2. The capacitor according to claim 1, wherein the impurity concentration decreases from the lowermost conductive film formed on the dielectric film to the uppermost conductive film. 4. A first conductive film formed on the upper electrode and doped with an impurity at a concentration capable of minimizing a thickness of a depletion layer formed between the upper electrode and the dielectric film. A second conductive film formed on the first conductive film and doped with an impurity at a concentration that allows the upper electrode to maintain a resistance value suitable for functioning as a resistance layer in a peripheral circuit region. 2. The capacitor of claim 1, wherein the capacitor is a semiconductor memory device. 5. The first conductive film has an impurity of 1 × 10 ^20.
5. The capacitor according to claim 4, wherein the second conductive film is doped to an atom / cm ² or more, and the second conductive film is doped to an impurity less than 1 × 10 ²⁰ atoms / cm ² . 6. The capacitor of claim 5, wherein the impurity is P or As. 7. The thickness of the first conductive film is between 50 ° and 50 °.
6. The capacitor of claim 5, wherein the angle is 0 [deg.]. 8. A step of forming a lower electrode of a capacitor having an uneven surface on a semiconductor substrate, a step of forming a dielectric film on a surface of the lower electrode, and a step of forming an impurity concentration on the dielectric film. Forming an upper electrode composed of a plurality of conductive films different from each other. 9. The step of forming the lower electrode includes forming a conductive film pattern defined for each cell on the semiconductor substrate, and having a hemispherical grain on a surface of the conductive film pattern. 9. The method according to claim 8, further comprising: forming a silicon layer to form an uneven surface. 10. The step of forming the upper electrode is performed on the entire surface of the resultant structure on which the dielectric layer is formed with a concentration that can minimize a thickness of a depletion layer formed between the dielectric layer and the dielectric layer. 9. The method according to claim 8, further comprising: forming a first conductive film doped with an impurity; and forming a second conductive film doped with an impurity at a lower concentration than the first conductive film. Of manufacturing a capacitor of a semiconductor memory device. 11. The impurity concentration of the second conductive film is a concentration capable of maintaining a resistance value suitable for the upper electrode to function as a resistive layer in a peripheral circuit region. Of manufacturing a capacitor of a semiconductor memory device. 12. The impurity concentration of the first conductive film is 1
× is 10 ²⁰ atoms / cm ² or more, the concentration of impurities of the second conductive film, manufacturing a capacitor of a semiconductor memory device according to claim 11, wherein less than 1 × 10 ²⁰ atoms / cm ² Method. 13. The method according to claim 11, wherein the impurity is P or As. 14. The first conductive film has a thickness of 50 ° to 50 °.
The method of claim 11, wherein the angle is 0 °.