JPH11204609A - Measurement of ohmic contact resistance in field effect transistor having heterojunction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor having a heterojunction, which is capable of finding an ohmic contact resistance. SOLUTION: In a field effect transistor having a heterojunction, the fixed width of each of ohmic electrodes 6 and 7 in a field effect transistor (a) to be measured, a test field effect transistor is prepared which has the same width of a recess etching part as a width Lrecess of a recess etching part 5 of the transistor (a) and which has a width of each of parts of n<+> -GaAs layers 3 and 4 which are not provided thereon with ohmic electrodes and corresponds to twice a width L of each of parts of n<+> -GaAs layers 3 and 4 which are not provided thereon with the ohmic electrodes 6 and 7, as well as a test field effect transistor which has a width of each of parts of n<+> -GaAs layers which are not provided thereon with ohmic electrodes and corresponds to the width L of each of the parts of n<+> -GaAs layers 3 and 4 which are not provided thereon with the ohmic electrodes 6 and 7 and which has the same width of a recess etching part as the width Lrecess of a recess etching part 5 of the transistor (a) and corresponds to twice of the width Lrecess. The resistive values between the ohmic electrodes of the three field effect transistors are measured. A relation among ohmic contact resistances is derived from the three transistors, and the ohmic contact resistances are found from the measured values and these relations.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect transistor having a heterojunction having a recess between ohmic contact layers on which an ohmic electrode is formed, and relates to an ohmic contact resistance, that is, the entirety from the ohmic electrode to the element isolation region. It relates to a method for measuring resistance.

[0002]

2. Description of the Related Art In general, evaluation of ohmic contact resistance in a field effect transistor is performed by using TLM (Tran
The Smmission Line Model method is used (Masamichi Omori, “Ultra High-Speed Compound Semiconductor Device”, Baifukan). The TLM method is a method of measuring a resistance value of a test pattern in which an ohmic electrode interval is changed, and separately obtaining an ohmic contact resistance and a sheet resistance of a contact layer by calculation based on the measured value.

This will be described with reference to the drawings. For example, as shown in FIGS. 7 to 10, two types of test patterns are prepared. First, for the sample A shown in FIGS. 7 and 8, when the distance between the ohmic electrodes 103 and 104 on the contact layer 102 formed on the semiconductor substrate 101 is L,
In the sample B shown in FIGS. 9 and 10, the distance between the ohmic electrodes 103 and 104 on the contact layer 102 formed on the same type of semiconductor substrate 101 is set to 2L having a length twice as long as the distance L. Set. The width of each of the ohmic electrodes 103 and 104 in each of the samples A and B is equal to W. Reference numeral 105 denotes an element isolation region.

When using these two test patterns,
The ohmic contact resistance Rc is obtained as follows. That is, Rc = R ₁ -1 / 2R ₂ . The sheet resistance ρs of the contact layer 102 is given by ρs = W · (R ₂
−R ₁ ) / L. Here, R ₁ is the ohmic electrode 10
Spacing 3,104 resistance value when the L, R _2, the spacing of the ohmic electrodes 103 and 104 is a resistance value when the 2L. Therefore, the ohmic contact resistance Rc is determined by measuring the resistance values of the ohmic electrodes 103 and 104 of the two test patterns.

[0005]

However, the above conventional measuring method has a problem that the ohmic contact resistance cannot be accurately measured and evaluated in a field effect transistor having a heterojunction. Will be described with reference in Figure, as shown in FIG. 11, for example n ⁺ -G
With respect to the field effect transistor P having a multilayer structure of aAs / AlGaAs / GaAs, the conventional measurement method causes a problem.

This field effect transistor P is made of GaAs
AlGaAs serving as a hetero barrier on the channel layer 111
A layer 112 is formed, and an n ⁺ -GaAs layer 11 as a contact layer is further formed on the AlGaAs layer 112.
3 and 114 are formed apart from each other by the recess etching portion 115, and the AlGaAs in the recess etching portion 115 is formed.
It has a structure in which the gate electrode 110 is formed on the s layer 112. The ohmic electrodes 116 and 117 are formed on the n ⁺ -GaAs layers 113 and 114 separated from each other via the recess etching portion 115 as described above.

In such a field effect transistor P, since the recess etching portion 115 exists, the current always flows through the n ⁺ -GaAs layer 113 and the AlGaAs layer 112.
Overcoming the hetero barrier between them. However, in the conventional TLM method in this regard, although some of the current indeed passing between n ⁺ -GaAs layer 113 and the AlGaAs layer 112, the majority are to pass through the n ⁺ -GaAs113. That is, as shown in the end view 12, n ⁺ -
Due to the current i0 passing through the GaAs 113, the conventional T
The ohmic contact resistance obtained from the LM method is estimated to be lower than the ohmic contact resistance of an actual field effect transistor. As a result, for example, the design of a device that reduces ohmic contact resistance has been hindered.

The present invention has been made in view of such a point, and even in such a heterojunction field effect transistor having a recess between ohmic contact layers, the ohmic contact resistance can be accurately measured and evaluated. Its purpose is to provide a way to do that.

[0009]

According to a first aspect of the present invention, an ohmic contact resistance in a heterojunction field-effect transistor having a recess between ohmic contact layers where an ohmic electrode is formed is reduced. In the measuring method, first, a plurality of three or more test field effect transistors having the same structure as the field effect transistor to be measured are prepared.

For example, the test field-effect transistor having a certain reference pattern and the test field-effect transistor having the reference pattern have the same width of the ohmic electrode and the width of the recess portion, and have no ohmic electrode. The test field-effect transistor in which the width of the ohmic contact layer is changed and the test field-effect transistor of the reference pattern have the same width as the ohmic electrode and the width of the ohmic contact layer where no ohmic electrode is formed, and have a recessed portion. And a test field-effect transistor having a different width.

Next, the resistance value between the ohmic electrodes of the three test field effect transistors is measured. On the other hand, from these three test field effect transistors, a relational expression of three ohmic contact resistances, that is, a relational expression between the resistance value between the ohmic electrodes to be measured and the ohmic contact resistance is obtained. For example, three relational expressions based on the sheet resistance of the ohmic contact layer, the sheet resistance of the channel layer, the width of the ohmic electrode, the width of the recess portion, the ohmic contact resistance to be obtained, and the like are obtained. Of these, the ohmic contact resistance, the sheet resistance of the ohmic contact layer, and the sheet resistance of the channel layer are unknown, and the widths of the other ohmic electrodes and the recesses can be treated as known values. Are simultaneously determined, the ohmic contact resistance is determined simultaneously with the sheet resistance of another ohmic contact layer and the sheet resistance of the channel layer.

As described above, in the present invention, the width of the recessed portion is also used as a parameter as compared with the conventional TLM method, and the number of types of test field effect transistors is increased accordingly to obtain the ohmic contact resistance. It is possible to accurately determine the ohmic contact resistance of a field effect transistor having a heterojunction.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. FIG. 1 shows a structure of a field effect transistor a which is a sample of a basic pattern. The sample of the first pattern, which can also be called the basic pattern, is an n ⁺ -GaAs / AlGaAs / GaAs having a heterojunction, similarly to the field-effect transistor P shown in FIG.
Is a field-effect transistor having a multi-layer structure.

That is, this field effect transistor a
An AlGaAs layer 2 is formed on the GaAs channel layer 1, and an n ⁺ -GaAs layer is further formed on the AlGaAs layer 2.
The s layers 3 and 4 are formed apart by the recess etching portion 5. The ohmic electrodes 6 and 7 are connected to the n
⁺ -Formed on the GaAs layers 3 and 4. Where n ⁺
Let L be the width of the portion of the GaAs layers 3 and 4 where the ohmic electrodes 6 and 7 are not formed, and Lless the opening width of the recess etching portion 5. Reference numeral 10 denotes an element isolation region, and the illustration of the element isolation region is omitted in FIGS.

A field effect transistor b of the second pattern shown in FIG. 2 is prepared. The structure of the field-effect transistor b is the same as that of the field-effect transistor a of the basic pattern, but the width of the n ⁺ -GaAs layers 3 and 4 where the ohmic electrodes 6 and 7 are not formed is 2.
It is set to 2L, which is twice as large.

Further, a field effect transistor c of the third pattern shown in FIG. 3 is prepared. The structure of the field effect transistor c is the same as that of the field effect transistor a of the basic pattern, and the width of the portion of the n ⁺ -GaAs layers 3 and 4 where the ohmic electrodes 6 and 7 are not formed is also L. , The opening width of the recess etching portion 5 ′ is set to 2 Lless, which is twice as large. The width of each of the ohmic electrodes 6 and 7 in the field effect transistors a, b and c is W having the same width.

Next, ohmic electrodes 6 and 7 in these three patterns of field effect transistors a, b and c, respectively.
The resistance between the ohmic electrodes is measured. In this case, according to the knowledge of the inventor, as shown in FIG. 4, the current between the ohmic electrodes 6 and 7 shows a saturation tendency when the applied voltage exceeds a certain value. Is determined from the slope of the linear region.

The measured values between the ohmic electrodes 6 and 7 of the three field effect transistors a, b and c of the three patterns are denoted by R (a), R (b) and R (c), respectively. Is the Rc, n ⁺ -GaAs layer 3,
Assuming that the four sheet resistance is ρ n ⁺ and the sheet resistance of the GaAs channel layer 1 is ρ channel, the following equation holds.

That is, R (a) = 2Rc + (ρn ⁺ 2L / W) + (Lless · ρchannel 1 · 1 / W) (1) Equation R (b) = 2Rc + (ρn ⁺ · 4L / W) ) + (Lless · ρchannel 1 / W) (2) Equation R (c) = 2Rc + (ρn ⁺ 2L / W) + (Lless · ρchannel 1 / W) (3) formula

When the equations (1), (2) and (3) are simultaneously set, the following equation is obtained. Rc = (3R (a) -R (b) -R (c)) / 2 (4) Equation ρn ⁺ = (R (b) -R (a)) · W / 2L (5) ) Formula ρchannel = (R (c) −R (a)) · W / Lrecess formula (6)

That is, the field effect transistors a, b,
By the resistance values R (a), R (b), and R (c) between the ohmic electrodes between the ohmic electrodes 6 and 7 at the point c, the ohmic contact resistance Rc equivalent to that of the actual field effect transistor becomes n ⁺ The sheet resistance ρn ^{+ of} the GaAs layers 3 and 4 and the sheet resistance ρch of the GaAs channel layer 1
It is obtained at the same time as "annel".

As described above, the second pattern in which the width of the portion where the ohmic electrodes 6 and 7 are not formed in the n ⁺ -GaAs layers 3 and 4 of the field-effect transistor a serving as the basic pattern is doubled to 2L. Not only the field-effect transistor b but also the field-effect transistor c of the third pattern, in which the opening width of the recessed etching portion 5 'is set to 2Lless, which is twice as large, and each ohmic electrode of each of the three patterns is prepared. Resistance values R (a), R between 6 and 7
By measuring (b) and R (c), the contact resistance of the ohmic electrode of a field-effect transistor having a heterojunction can be accurately determined.

In the above-described embodiment, in order to make the description easy to understand, the width of the portion where the ohmic electrodes 6 and 7 are not formed in the n ⁺ -GaAs layers 3 and 4 of the field effect transistor a serving as the basic pattern is set. Double 2L
Field-effect transistor b of the second pattern set to
And 2Lre in which the opening width of the recess etching portion 5 'is doubled.
The third pattern of the field effect transistor c set to cess is prepared. Generally, if C ₁ and C ₂ are used as coefficients and C ₁ L and C ₂ Less are respectively obtained,
Equations (1) to (3) can be rewritten as follows.

R (a) = 2Rc + (ρn ⁺ · 2L / W) + (Lless · ρchannel l · 1 / W (1 ′) Formula R (b) = 2Rc + (ρn ⁺ · 2C ₁ L / W) ) + (Lless · ρchannel el · 1 / W (2 ′) Formula R (c) = 2Rc + (ρn ⁺ 2L / W) + (Lless · ρchannel 1 · C ₂ / W (3 ′) Therefore, Rc, ρn ⁺ , and ρchannel can be obtained even if these expressions (1 ′) to (3 ′) are simultaneously used.

A plurality of test patterns having different C ₁ and C ₂ are prepared, and the resistance between the ohmic electrodes is measured in the same manner. The ohmic electrodes 6 and 7 of the n ⁺ -GaAs layers 3 and 4 are similarly measured.
The width of the portion but is not formed, when a plurality of points plotted the relationship between the resistance value between the ohmic electrode as shown in FIG. 5, from the slope of the line obtained by it, n ⁺ -GaA
The sheet resistance ρn ⁺ of the s layers 3 and 4 can be obtained.

In a similar manner, the relationship between the width of the recess etching portion and the resistance between the ohmic electrodes is plotted at a plurality of points, and as shown in FIG. 1 sheet resistance ρcha
nnel can be determined.

In each of the graphs shown in FIGS. 5 and 6, the intercept of the axis (Y-axis) of the resistance value between the ohmic electrodes of each straight line is 2Rc + Lless · ρrecess /
W, 2Rc + 2 · ρn ⁺ / W, the respective ohmic contact resistances Rc can be obtained. In this case, since the number of measurement points is increased, the accuracy is improved accordingly.

In the above embodiment, GaAs / AlGa
The field effect transistor having an As heterojunction has been described as an example. However, according to the present invention, any other field effect having a heterojunction can similarly obtain ohmic contact resistance in a transistor. The prepared test pattern may be a pattern after the gate electrode is formed as shown in FIG.

[0029]

According to the present invention, the ohmic contact resistance of a field effect transistor having a heterojunction can be accurately determined. Therefore, a device structure that reduces ohmic contact resistance can be efficiently developed.

[Brief description of the drawings]

FIG. 1 is a schematic longitudinal sectional view showing a configuration of a field-effect transistor having a first pattern used for carrying out a method for measuring ohmic contact resistance according to an embodiment of the present invention.

FIG. 2 is a schematic vertical cross-sectional view illustrating a configuration of a field-effect transistor having a second pattern used for performing the method for measuring ohmic contact resistance according to the embodiment of the present invention.

FIG. 3 is a schematic explanatory view of a longitudinal section showing a configuration of a field-effect transistor having a third pattern used for carrying out the method for measuring ohmic contact resistance according to the embodiment of the present invention.

FIG. 4 is a graph showing voltage-current characteristics between ohmic electrodes.

FIG. 5 is a graph showing the relationship between the width of an n ⁺ -GaAs layer and the resistance value between ohmic electrodes prepared based on measurement results of resistance values between ohmic electrodes of a plurality of test patterns.

FIG. 6 is a graph showing a relationship between an opening width of a recess etching portion and a resistance value between ohmic electrodes, which are created based on measurement results of resistance values between ohmic electrodes of a plurality of test patterns.

FIG. 7 is a schematic explanatory view of a vertical section showing a configuration of a transistor having a test pattern used for obtaining ohmic contact resistance by a conventional TLM method.

FIG. 8 is a plan view of the transistor of FIG. 7;

FIG. 9 is a schematic vertical cross-sectional view showing a configuration of a transistor having another test pattern used for obtaining ohmic contact resistance by a conventional TLM method.

FIG. 10 is a plan view of the transistor in FIG. 9;

FIG. 11 is a schematic vertical cross-sectional view showing a configuration of a field effect transistor having a recess etching portion having a multilayer structure of n ⁺ -GaAs / AlGaAs / GaAs.

FIG. 12 is an explanatory diagram showing a current flow when the resistance of an ohmic contact of a field effect transistor having a heterojunction is obtained by a conventional TLM method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 GaAs channel layer 2 AlGaAs layer 3, 4n <^+>- GaAs 5 Recess etching part 6, 7 Ohmic electrode a, b, c Field effect transistor

Claims (1)

[Claims] 1. A method of measuring ohmic contact resistance in a heterojunction field effect transistor having a recess between ohmic contact layers on which ohmic electrodes are formed, the method comprising measuring the same structure as the field effect transistor to be measured. A plurality of the above-mentioned test field-effect transistors are prepared, and the plurality of test field-effect transistors are formed as ohmic contact layers on which no ohmic electrode is formed while the ohmic electrode width of the reference test field-effect transistor is fixed. , And the width of the recessed portion are independently changed, and the resistance between the ohmic electrodes of the test field-effect transistors is measured, and the heterojunction to be measured is determined based on the measured value. Field effect transistor ohmic contacts And obtaining the anti-method for measuring the ohmic contact resistance in a field effect transistor having a heterojunction.