JPH11196074A - Clock decision circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide a clock with a proper phase from a polyphase clock, even when a phase of received data fluctuates. SOLUTION: Figure (a) shows an overall diagram of the clock decision circuit and consists of shift registers 7, 8, 9, in which phase selection information inputted from a clock selection circuit is written and phase decision circuits 10, 11, 12 that decide a phase of the clock under a prescribed condition. Figure (b) is a detailed diagram of each of the phase decision circuits 10, 11, 12 and consists of three AND circuits 13, 14, 15 and one OR circuit 16. Thus, clock selection results which is equivalent to three change points are iterated with adjacent phases to decide a desired clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock determination circuit, and more particularly to a clock determination circuit for identifying received data in digital transmission.

[0002]

2. Description of the Related Art In digital transmission, a method of extracting a clock for identifying received data is an indispensable technique, among which is a multi-phase selection method. In the multi-phase selection method, a clock having several phase differences is prepared on the receiving side, and a clock that meets a predetermined condition is selected from the clocks and used.
FIG. 6 shows a configuration example of a clock extraction circuit using a conventional multi-phase selection method. In this figure, a clock extraction circuit is a multi-phase clock generation circuit 1 for generating clocks having several phase differences, a change point detection circuit 2 for detecting a change point of received data, and a multi-phase clock. A clock selection circuit 3 for selecting a phase of a clock, a clock determination circuit 4 for determining a phase of a clock satisfying a predetermined condition from the selected clock, a determination result holding circuit 5 for holding the determined result, and a multi-phase clock. And a selector 6 for selecting and outputting. The clock extraction circuit of the multi-phase selection system thus configured operates as follows. The multi-phase clock generator 1 generates multi-phase clocks having different phases based on a master clock supplied from a receiving device. In this example, M
It is a multi-phase clock. The change point detection circuit 2 detects a change point of the received data and outputs it to the clock selection circuit 3 as a change point clock. The clock selection circuit 3
A multi-phase clock having a phase difference of 1 to M phases from the multi-phase clock generator 1 and a change point clock from the change point detection circuit 2 are input, and the rising of the clock is centered on the received data. A clock having a phase that is located is selected from the multiphase clocks according to the timing of the transition point clock. The selection of the phase is performed for each change point of the received data. Next, in the clock determination circuit 4, the clock selection circuit 3
If the result of phase selection output from is the same two consecutive times, the result is used to determine the clock phase. The reason that the selection result is set to be continuous twice in the above description is to avoid erroneous clock phase selection due to the influence of transmission distortion and noise on received data passing through the transmission path,
This is because it is desirable that the phase selection of the clock be determined as soon as possible even for a moment. The clock phase determined by the clock determination circuit 4 is held by the determination result holding circuit 5 and then output to the selector 6. The selector 6
A clock of the determined phase is selected and output from the clocks of 1 to M phases which are the outputs of the multi-phase clock generator 1.

FIG. 7 shows a time chart of a conventional clock extraction circuit using a multi-phase selection method. First, (a) shows a master clock supplied from the receiving device, and clocks (b) to (e) having different phases are generated based on this clock. (F) shows a waveform of the received signal, and detects a change point from the received signal to generate a change point clock which is a change point detection output of (g). (H) shows the output of the clock selection circuit, and selects the clock located at the center of the received data from the multi-phase clocks for each of the transition clocks. In this example, the clock of phase 1 is located closest to the center of the received data, and the output of the clock selection circuit shown in (h) selects phase 1. Next, (i) the clock determination output determines whether or not the clock selection output selects the same clock phase twice in succession. If the clock selection output is selected twice in succession, the clock phase is determined as the target clock phase. Therefore, in the clock determination output, the phase 1 is set to 2
Phase 1 is determined as the target clock phase based on the timing after the detection has been performed consecutively. The determined clock phase is held in the (j) determination result holding output, and (k)
In the output of the selector shown in (1), a phase 1 clock which is a phase held as a determination result is output.

[0004]

However, in the above-described clock extraction circuit based on the conventional multi-phase selection method, the clock phase may not be determined even though correct data is received. There's a problem. This problem occurs when the center of the received data is between two clock phases or the like.
It is undefined which of the two clock phases to select.
This is because the phase of the received data fluctuates due to jitter, which is a slight distortion, or variation in the operation of the semiconductor elements that constitute the circuit. Therefore, it is not possible to recognize a clock having the same phase twice consecutively, and it is not possible to determine the clock phase. FIG. 8 shows a time chart of an example in which the phase of the clock cannot be determined. The multi-phase clocks having different phases shown in (b) to (e) are generated from the master clock shown in (a). Phases 1 and 2 of the multiphase clock are located at the center of the received data shown in (f). At this time, the clock selection circuit may alternately select the phase to be selected between phase 1 and phase 2 due to slight phase fluctuation of the received data. Therefore, as shown in (i), the clock determination circuit cannot recognize the clock having the same phase twice consecutively, and cannot determine the phase. As a result, as shown in (j), the decision result holding output remains the phase information at the time of the determination in the previous reception signal, and the output of the selector is the clock of the phase determined by the previous reception signal as shown in (k). Output as is. In such a phase, it is sufficient that the clock rises at a position close to the center of the received data, so that either phase 1 or phase 2 may be determined. SUMMARY OF THE INVENTION The present invention has been made in order to solve the problem of the clock decision circuit which is a component of the clock extraction circuit in the conventional clock extraction circuit based on the multi-phase selection method as described above. The selection is repeated by adjacent phases between adjacent phases so that 2
It is a feature of the present invention to provide a clock determination circuit that can determine the phase of a clock under predetermined conditions even when the same phase clock cannot be recognized consecutively.

[0005]

In a clock extraction circuit for determining a clock for identifying received data by a multi-phase selection method, a three-stage shift register provided for each phase of a multi-phase clock and a predetermined shift register are provided. And a logic circuit for setting a determination condition, wherein a desired clock is determined by repeating clock selection results for three change points in the adjacent phase.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of a clock determination circuit in a multiphase selection type clock extraction circuit according to the present invention. FIG. 3A is an overall view of a clock determination circuit, which includes a shift register 7 for writing phase selection information input from the clock selection circuit,
8 and 9 and phase determining circuits 10, 11, and 12 for determining a clock phase based on predetermined conditions. The clock determination circuit thus configured operates as follows. The phase selection information input from the clock selection circuit is
The data is written into the shift registers 7, 8, and 9 corresponding to the 1 to M phases at the timing of the transition clock generated from the transition of the received data. Shift registers 7, 8, 9
Is composed of three stages of registers, and the shift register always stores the phase selection information for three transition point clocks. The phase determination circuits 10, 11, and 12 determine the clock phase under predetermined conditions based on the phase selection information for the three clocks, and output the result to the determination result holding circuit. (B) is a detailed diagram of the phase determination circuits 10, 11, and 12, and shows three AND circuits 13, 14, and 15;
And one OR circuit 16. The operation of this logical configuration is expressed by the following equation, and the clock phase is determined based on three conditions. NQA * (N + 1) QB * NQC + (N + 1) QA * N
QB * (N + 1) QC + NQA * NQB Explaining the meaning of this expression, QA, QB, and QC indicate outputs corresponding to output stages A, B, and C of a three-stage shift register, and N is the Nth of the multiphase clock. Shows the clock phase of the clock.
The first term of the above equation is that the phase selection is N phases, (N + 1)
The second term shows the case where the phase is selected as the (N + 1) phase, the N phase, and the (N + 1) phase, and the third term shows the case where the same phase is selected. Is performed twice consecutively, and the phase is determined even if any of the first, second, and third terms is selected.

FIG. 2 shows a functional diagram of the clock decision circuit according to the present invention. In this figure, 17, 18, 19, 20
Are clock decision blocks corresponding to the respective phases from phase 1 to phase M, and all have the same function. To explain the case where phase 1 is selected, phase 1 is selected at the change point of the received data for the first time, phase 2 is selected for the second time, and phase 1 is selected for the third time. decide. Similarly, phase 1 in the first time, phase 1 in the second time,
In the third time, when phase 2 is selected, phase 1 is determined.
Further, the phase 1 is determined as the phase 1 in the first time, and the phase 1 is also determined in the case where the phase 1 is selected in the second time.

FIG. 3 shows a time chart of the clock decision circuit according to the present invention. This figure shows a case where a transition point clock (b) is generated from the received signal (a) and the clock selection circuit alternately selects the phase 1 and the phase 2 as shown in (c) and (d). At this time, the phase 1 shift register shifts the phase 1 of FIG.
Write the selection information sequentially. (E), (f) and (g) are 3
Phase 1 shift register 1 composed of stage registers
These are the outputs of the second, third, and third stages. Similarly, phase 2
The shift register sequentially writes the phase 2 selection information (d) at the timing of the transition clock. (H),
(I) and (j) are outputs of the first, second and third stages of the phase 2 shift register composed of three stages of registers, respectively. At this time, the timing at which the output of each shift register satisfies the above-described clock determination condition occurs at the fourth clock of the transition point clock when all three outputs 1QC, 1QA, and 2QB are at the high level. At this time, the clock phase is determined to be phase 1 (k) and phase 1 determination information is output.

FIG. 4 shows an example of the configuration of a clock extraction circuit based on a multi-phase selection system incorporating a clock determination circuit according to the present invention. In the figure, a clock extraction circuit includes a multi-phase clock generation circuit 1 for generating clocks having several phase differences, and a change point detection circuit 2 for detecting a change point of received data.
A clock selecting circuit 3 for selecting an optimal clock phase from among the multi-phase clocks, a clock determining circuit 21 for determining a clock phase that satisfies a predetermined condition from the selected clock, and a determination for holding the determined result. It comprises a result holding circuit 5 and a selector 6 for selecting and outputting a multiphase clock. The clock extraction circuit of the multi-phase selection system thus configured operates as follows. Polyphase clock generator 1
Generates multi-phase clocks having different phases based on the master clock supplied from the receiving device. In this example, an M-phase multiphase clock is used. The change point detection circuit 2 detects a change point of the received data and outputs it to the clock selection circuit 3 as a change point clock. The clock selection circuit 3 inputs a multi-phase clock having a phase difference of each of 1 to M phases from the multi-phase clock generator 1 and a change point clock from the change point detection circuit 2, respectively. A clock having a phase at which the rising edge of the clock is located at the center is selected from the multiphase clocks based on the timing of the transition clock. The selection of the phase is performed for each change point of the received data. Next, in the clock determination circuit 4, the clock selection circuit 3
As described above, the clock phase is determined if the original phase and the next phase are alternately selected or the same phase is selected twice consecutively, as described above. The clock phase determined by the clock determination circuit 4 is held by the determination result holding circuit 5 and then output to the selector 6. The selector 6 outputs 1 to M, which are the outputs of the multiphase clock generator 1.
From the clocks up to the phase, a clock of the determined phase is selected and output.

FIG. 5 is a time chart of a clock extracting circuit based on a multi-phase selection system incorporating a clock determining circuit according to the present invention. First, (a) shows a master clock supplied from the receiving device, and clocks (b) to (e) having different phases are generated based on this clock. (F) shows a waveform of the received signal, and detects a change point from the received signal to generate a change point clock which is a change point detection output of (g). (H) shows the output of the clock selection circuit, and selects the clock located at the center of the received data from the multi-phase clocks for each of the transition clocks. In this example, the clock of phase 1 and the clock of phase 2 are located closest to the center of the received data, and the output of the clock selection circuit shown in (h) alternately selects phase 1 and phase 2. I have. Next, (i) the clock determination output determines the phase 1 as a target clock phase when the clock selection output alternately selects the phases 1 and 2 during the three transition clocks.
The determined clock phase is held by the (j) determination result holding output, and a phase 1 clock, which is the phase holding the determination result, is output from the selector output shown in (k).

[0011]

As described above, according to the present invention, the phase can be determined accurately even when the phase of the received data is fluctuating and the clock phase selection is repeated between adjacent phases. It is very effective in designing and operating transmission equipment.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an embodiment of a clock determination circuit in a multiphase selection type clock extraction circuit according to the present invention.

FIG. 2 is a diagram showing a function of a clock determination circuit according to the present invention.

FIG. 3 is a diagram showing a time chart of the clock determination circuit according to the present invention.

FIG. 4 is a diagram illustrating a configuration example of a clock extraction circuit based on a multi-phase selection system incorporating a clock determination circuit according to the present invention.

FIG. 5 is a diagram showing a time chart of a clock extraction circuit based on a multi-phase selection system incorporating a clock determination circuit according to the present invention.

FIG. 6 is a diagram showing a configuration example of a clock extraction circuit using a conventional multi-phase selection method.

FIG. 7 is a diagram showing a time chart of a conventional clock extraction circuit based on a multi-phase selection method.

FIG. 8 is a diagram showing a time chart of a conventional clock extraction circuit based on a multi-phase selection method.

[Explanation of symbols]

1. Multi-phase clock generation circuit 2. Change point detection circuit 3. Clock selection circuit 4. Clock determination circuit 5. Decision result holding circuit 6. Selector
7, 8, 9 ··· shift register, 10, 11, 12
..Phase determination circuits, 13, 14, 15
16-OR circuit, 17, 18, 19, 20 ...
Clock decision block, 21. Clock decision circuit

Claims (1)

[Claims] 1. A clock extraction circuit for determining a clock for identifying received data by a multi-phase selection method, wherein a three-stage shift register provided corresponding to each phase of the multi-phase clock and a predetermined determination condition are set. And a logic circuit configured to determine a desired clock by repeating a clock selection result for three change points in adjacent phases.