JPH11195788A - Trench-gate type power mosfet having protective diode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of breakdown at a trench-bottom part, to avoid damage of an MOSFET and to improve on-resisting characteristics by forming a second conducting type protecting diffusing part in a chip, and forming a first-conducting type P-N junction part in an epitaxial layer or in a substrate. SOLUTION: In a neighboring cell 37, a deep P<+> diffusing part 38 for protection is formed. In the diffusing part 38, a P-N junction part 39 is formed together with an N-epitaxial layer 14. A metal layer 36 is in contact with the protecting diffusing part 38. Thus, the P-N-junction part 39 functions as a diode, which is connected in parallel with the channel of a cell 35. The protective diffusing part 38 limits the electric field strength and the formation of the carrier, which is generated in the vicinity of the corner part of a trench 32 as a result. Thus, requirement for a deep central diffusing part at the SFET cell 35 is eliminated. When the deep central diffusing part is not used, the dimension of the MOSFET cell 35 is substantially decreased, and the cell density of a MOSFET 30 is strikingly increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power FET, and more particularly, to a MOSFET in which a gate is disposed in a trench formed on a surface of silicon.

[0002] This patent application is a U.S. patent filed on October 31, 1997, which is a continuation-in-part of U.S. Patent No. 08 / 459,555 filed on June 2, 1995 (Patent Attorney Patent No. M-3278-4P). No. 08 / 844,826 filed on Jun. 30, 1997 and No. 08 / 429,414 filed on Apr. 26, 1995;
Related to No. 5,674,766, registered on 07/07. The entirety of this application is incorporated herein by reference to the patents of each prior application.

[0003]

2. Description of the Related Art Trench gate type MOSFETs are MOS
One of the FETs, in which a gate is formed in a trench formed in a surface of silicon and extending inward. The gates are formed in a grid-like geometric pattern, which defines the individual cells of the MOSFET, which pattern is usually in the form of a closed polygon (square, hexagon, etc.) or a series of It is in the form of stripes or rectangles that are interdigitated. The current flows in a vertical channel formed adjacent to the side of the trench. The trench is filled with a conductive gate material, typically doped polysilicon, and is isolated from silicon by a dielectric layer, usually made of silicon dioxide.

[0004] Two important characteristics of power MOSFETs are the breakdown voltage, the voltage at which current begins to conduct during off-conditions, and the on-resistance, ie, the resistance that conducts current during on-conditions. Generally, the on-resistance of a MOSFET changes in proportion to the cell density. The larger the number of cells per unit area, the larger the total “gate width” (periphery of each cell). Because it flows. The breakdown voltage of a MOSFET mainly depends on the doping concentration and the arrangement of the source, body and drain regions in each MOSFET cell.

[0005] MOSFETs are typically formed in lightly doped epitaxial layers of silicon grown on a heavily doped silicon substrate. Gate trenches usually extend into the epitaxial layer and are often square,
It has a flat bottom surface defined by corners. This shape creates the problem that the electric field reaches a maximum near the corner of the gate trench when the MOSFET is turned off. This causes avalanche breakdown and impact ionization, and also results in the generation of carriers. When carriers are generated within the mean free path at the boundary between silicon and the gate oxide,
Carriers have energy high enough to cross their boundaries and may be injected into the gate oxide.
Carriers that can overcome the silicon / silicon dioxide energy barrier are often "hot carriers"
Called. Hot carrier injection can cause extreme damage to the gate oxide layer and cause a change in threshold voltage, transconductance or on-resistance, thereby reducing M
The OSFET may be damaged or destroyed.

US Pat. No. 5,072,266 discloses a deep central body diffusion that extends below the bottom of a trench using a MOS.
Disclosed is a technique for suppressing voltage breakdown near a gate by forming it in an FET cell. This deep central diffusion creates an electric field such that breakdown occurs in the bulk silicon away from the gate, where hot carriers do not reach the gate oxide. A cross-sectional view of a MOSFET according to U.S. Pat. No. 5,072,266 is shown in FIG. 1, including a trench gate 11, an N + source region 12, an N + substrate (drain) 13, an N-epitaxial layer 14, and a deep central P + diffusion 15. MO including
An SFET cell 10 is shown. Note that the lowermost portion of P + diffusion 15 is below the bottom of gate 11.

The doping of the deep P + diffusion is indicated by the dashed line, and the P
Higher than the doping of the body 16; As a result, the distance Ys between the gate trenches must be kept above a certain minimum value. Otherwise, deep P + dopants will diffuse into channel 17 and increase the threshold voltage Vtn of the device. The value of Ys, together with the gate thickness, determines the cell density and plays a role in determining the MOSFET on-resistance.

The deeper P + diffusion limits the spread of current in N-epitaxial layer 14. Figures 20 and 21
Represent a conventional MOSFET having a flat bottom P- body region and a MOSFET having a deep P + diffusion, respectively.
3 shows a simulation of a T current line. 21 is limited to a divergence angle (analytical approximation used to describe the uniformity of the epitaxial current) of approximately 45-47 ° (measured at 95% current line),
As a result, the N-epitaxial region is utilized in a less than optimal state and has a higher specific on-resistance than the device described in FIG. Conventional devices have a large current spread angle, in the range of 73-78 °, and the equation x =
Achieve uniform conduction at a fairly shallow depth estimated by (Y _CELL −Y _G ) 2 tan θ, where θ is the current spread angle, Y _CELL is the full width of the MOSFET cell, and Y _G is the distance between gate trenches. . This relationship is shown in FIG. It has been found that the presence of the deep P + region increases the depth at which uniform conduction is achieved in the N-epitaxial region from 0.5 microns to 1.6 microns.

Power MOS with extremely low voltage and low on-resistance
To make FETs, device dimensions are typically reduced. Specifically, the cell density is increased and the epitaxial layer is thinned until the gate trench is where it extends into the heavily doped substrate. Such a MOS
The FET is shown as MOSFET 20 in FIG. 2A.

This creates a whole new set of design criteria. Referring to FIG. 2A, a corner 2 of the gate trench 21 is formed.
Since 1C is surrounded by N + substrate 13, the electric field at this location falls completely between the gate oxide layers. Although the formation of hot carriers in the silicon is reduced, the high electric field on the gate oxide layer still causes the device to degrade or damage. In one condition, when the gate is biased to approximately the same potential as the source and body (i.e., when the device turns off), it is quite worrisome that the gate oxide layer at the bottom of the trench will have no That means you have to withstand the voltage. This is because there is no epitaxial layer for absorbing a part of this potential difference as compared with the embodiment of FIG.

FIG. 2 shows an equivalent circuit for the MOSFET 20.
B. Diode D _DB represents the PN junction between N-epitaxial layer 14 and P-body region 22,
Capacitor C _GD represents a capacitor between gate oxide layers 21A.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a trench gate type MOSFET in which the occurrence of breakdown at the bottom of the trench is prevented, the MOSFET is not damaged, and the on-resistance characteristic is improved.

[0013]

SUMMARY OF THE INVENTION The trench gate type MOSFET of the present invention is formed in a semiconductor chip consisting of a substrate alone or a substrate on which an overlying epitaxial layer is deposited. The gate of the MOSFET is formed in a trench extending downward from the surface of the chip. MOSFET
Comprises a first conductivity type source region, a second conductivity type body region, and a first conductivity type drain region, which are vertically arranged along the sidewall of the trench. The gate trench may extend into the epitaxial layer,
It may reach the inside of the substrate through the epitaxial layer.

The MOSFET is formed as a plurality of cells defined by gate trenches. The cells can be of any shape. For example, the cells can be square or hexagonal, or a series of parallel stripes or rectangles. In accordance with the present invention, a protective diffusion of the second conductivity type is created in the chip, which forms a PN junction of the first conductivity type in the epitaxial layer or substrate. This PN junction functions as a diode. The metal layer is a protective diffusion (ie, the terminal of the diode) such that the diode is connected in parallel to the channel of the MOSFET cell
To the source region of the MOSFET cell.

In a preferred embodiment, the protective diffusion is a MO
Formed in certain cells in a selected pattern across the SFET.

The protective diffusion of the second conductivity type reduces the strength of the electric field between the gate oxides, and even at the corners of the trench, and limits the formation of hot carriers near the trench. Operate. In certain embodiments, the trench extends into the epitaxial layer. Avalanche breakdown can be triggered by a number of mechanisms (reachthrough, radius of curvature, etc.) as long as the avalanche region is spatially separated from the gate trench. The diode also operates as a voltage clamp, thereby limiting the voltage across the gate oxide layer. In certain embodiments, the trench extends into the substrate and the gate oxide must withstand the full voltage drop between the MOSFETs.

In one preferred embodiment, one cell including a protective diffusion ("diode cell") is provided for a selected number of active MOSFET cells ("active cells") in a pattern across the MOSFETs. Is repeatedly provided. The number of diode cells per active cell is determined by MOSFET design criteria.
In general, for example, MOSFET cells that are expected to undergo more breakdown require a higher percentage of diode cells.

In addition, the presence of the diode cell allows the MOS
When an FET operates using body diode forward conduction, a large portion of the drain-body diode current will flow. Such operation (referred to as the third quadrant operation of an N-channel device) usually occurs when the inductor or motor is driven by push-pull, ie, a pair of bridged MOSFETs.
The high diode current in the active cell results in minor charge storage, which degrades diode turn-off (forced diode reverse recovery) and, when a high reverse voltage is applied again between the devices, the parasitic source- Body-drain active cells may trigger snapback of the NPN bipolar transistor.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention is shown in FIG. Trench gate MOSFET 30 is formed in epitaxial layer 14 that grows on the upper surface of N + substrate 13. Gate 31 is formed in trench 32 and is separated from the semiconductor material by oxide layer 31A.
The cell 35 of the MOSFET 30 includes a P-body region 33,
A shallow P + contact region 33A and an N + source region 34 are also provided. The metal layer 36 includes the P- body region 33 and the N-
+ Source region 34, and short-circuits between them.

The N + substrate 13 functions as a drain of the MOSFET 30 and is contacted from the bottom thereof. Alternatively, a buried N + layer can be used as the drain instead of the N + substrate, and the drain can be contacted from above the structure using, for example, an N + sinker region and an upper contact.

In the adjacent cell 37, a deep P + for protection is used.
The diffusion part 38 is formed. Diffusion portion 38 forms PN junction 39 with N-epitaxial layer 14. The metal layer 36 is in contact with the protective diffusion 38 so that the PN
Junction 39 represents a diode connected in parallel with the channel of cell 35.

The protective diffusion 38 limits the strength of the electric field and the resulting carrier formation near the corners of the trench 32, thereby eliminating the need for a deep central diffusion in the MOSFET cell 35. Without the deep P + central diffusion, the size of MOSFET cell 35 is substantially reduced and the cell density of MOSFET 30 is significantly increased.
For example, the width of each side surface of the N + source region 34 is about 1.0 μm.
m and the P for the metal layer 36 and the P-body 33
+1.0 μm width of contact between contact region
m, so that the overall width between trenches 31 can be approximately 3.5 μm. Actually, trench 3
The total width between 1 is set to 5.0 μm. This is in contrast to a minimum width of about 8.0 μm for MOSFET cells that include a deep central diffusion (see FIG. 1).

FIG. 4A shows an M cell similar to the cell shown in FIG. 2A.
1 shows a MOSFET 40 including an OSFET cell 41. That is, trench 43 extends through N− epitaxial layer 14 into N + substrate 13 and cell 41 does not include a deep central P + diffusion. In the adjacent cell 42, a protective P + diffusion 44 is formed, and the lower junction of the diffusion 44 reaches the upper surface of the N + substrate 13.

FIG. 4B shows an equivalent circuit diagram for MOSFET 40. Since the corners of the trench 43 are located within the N + substrate 13 and the heavily doped N + substrate 13 cannot withstand a strong electric field, the problem of the electric field at the corners of the trench is almost negligible. Instead, the gate 45 and the N + substrate 1
3, ie the gate oxide layer 45A
The strength of the intervening electric field is a significant factor. This position is represented by the capacitor _{CGD in} FIG. 4B. PN between P-body region 22 and N-epitaxial layer 14
The junction is represented by diode D _DB and the PN junction between P + diffusion 44 and N + substrate 13 is diode D _DB.
Represented by _{P + / N +} . As shown here, both diode D _DB and diode D _{P + / N +}
It is connected in parallel with the channel of the ET cell 41.

FIG. 5 shows a conventional MOSFE shown in FIG.
The top view of T10 is shown. A protective deep P + region 15 is shown at the center of each square cell and is surrounded by an N + source region 12 and a gate 11. FIG. 5 shows four complete cells.

FIG. 6 shows the MOSFET 30 shown in FIG.
FIG. A plan view of the MOSFET 40 shown in FIG. 4A will be similarly shown. Since the protective P + region at the center of each cell has been eliminated, the dimensions of the cell have been reduced. A cell containing a P + diffusion (often called a "diode cell") is also shown. In FIG. 6, 8
There is one diode cell for every active MOSFET cell (a total of 9 cells).

FIG. 7 shows a detailed plan view of the three cells shown in FIG. 6 (two active MOSFET cells and one diode cell). In FIG. 7, Ys represents the cross-sectional width of the trench (not to be confused with the gate width W).
Assuming that there is one diode cell for every n cells, the following equation gives the total area of n cells:

[0028]

A = (Y _G + Y _S ) ² + (n−1) (Y _G + Y _S ) ²
= N (Y _G + Y _S ) ²

The n-1 of these cells is an active MOS
Since it is an FET cell, the total gate width W in n cells is equal to:

[0030]

## EQU2 ## W = 4Y _S (n-1)

Therefore, the area-to-width ratio A / W (a goodness index indicating how efficiently the gate width W is accommodated in the area A)
Is equal to

[0032]

A / W = (Y _G + Y _S ) ²

Thus, the MOSFE including the diode cell
The ratio A / W to T is equal to the conventional M without diode cells.
It is increased by a factor n (n-1) compared to the OSFET. This "penalty" factor results from the fact that the diode cell does not conduct current,
Approaches 1 as increases. The losses are offset by an increase in the total gate width (and thus the current carrying capacity) obtained by increasing the cell density of the device.
In general, n is determined by the frequency with which the MOSFET is expected to break down. Devices that are expected to break down more frequently will generally require lower values of n, i.e., there will be more diode cells to total cells. In the extreme case, where the other cell has only one inactive cell (i.e., a diode cell), N = 2 and n / n-
1 = 2, the efficiency gain of this structure is somewhat limited. On the other hand, for example, if only one of all 21 cells is a diode cell, n = 21 and n / n-1 = 2
1/20, indicating that there is substantially no loss due to the diode.

As mentioned above, US Pat. No. 5,072,2
The existence of a deep P + region as disclosed by US Pat.
Limit the spread of current in the epitaxial region, thereby increasing the on-resistance. FIG. 23 shows the specific on-resistance (R
_DS A) is replaced by a MOSFET with a deep P + diffusion (curve 170) and a MOSF with distributed diode cells.
FIG. 7 is a graph showing the ET (curve 172) as a function of cell density. As shown therein, the specific on-resistance of a MOSFET with a deep P + diffusion reaches a certain minimum value, but then the current condenses and the threshold voltage rises due to the penetration of the P + body dopant into the channel. The result increases. MO with distributed diode cells
In the SFET, the current spread is improved, and the improvement becomes more significant with an increase in the cell density, so that a significant improvement in the on-resistance is achieved. In the graph of FIG. 23, the on-resistance of the active flat bottom cell improves 31% to 35 mΩ-cm ² simply as a result of increasing the spreading angle (see 12 Mcells / in ² in FIG. 23). Further 32
Increasing the cell density to Mcells / in ² achieves a 28% improvement primarily as a result of the improved channel resistance from a lower A / W factor. The net effect is to multiply these improvements by 12Mcell
Compared to the previous one o'clock s / in ^2, the die resistance to 30-VN-channel trench-gate MOSFET, a reduction of approximately 51%. FIG. 24 shows the specific R _DS A
Is shown as a function of gate bias for the two devices. For devices with a 20-V gate rating, the threshold voltage was held at 2.9V to be consistent with the rated operation at 10- and 4.5-V gate bias.

The avalanche capability of the 1-of-N clamp MOSFET is based on unclamped inductive switching (UI
S) Analyzed using simulation. The device had one diode cell for every 16 active MOSFET cells. FIG. 25 shows the current lines of the device operating in the linear region during normal conduction before switching, and FIG. 26 shows the current lines after the device has been inductively switched. As shown therein, avalanche breakdown occurred in the diode cell and induced all current, and no impact ionization, pre-avalanche or high gate oxide field was measured in the active MOSFET cell in the "off" state. .

[0036]

EXAMPLE 1 The test was performed using unclamped inductive switching (U
IS) Tester (AOT ILT-200 Induct)
The test was performed using an SO-8 size MOSFET operating at a rated current of 10-A using an I.L. FIG. 27 shows that the measured UIS current is MOSFET
Exceeds 7 times the rated operating current of 950 A / c
indicating that reaches m ² or more. The increase in avalanche breakdown voltage during the UIS from 36 V nominal breakdown (see FIG. 28) to 46 V
No ET damage was observed.

[0037]

Example 2 When using 32 Mcells / in ² technology, the size of 0.57 for D ² PAK type package
A 4 cm × 0.427 cm MOSFET was designed, fabricated and assembled. This device, using 1,075,620 active MOSFET cells, was the first power MOSFET to achieve ULSI class fabrication techniques (> 1 million transistors). As shown in FIG. 28, the measured die showed a saturation current above 140 A with a gate bias of 4.0 V, as well as a drain current at 5 V that remained linear above 300 A (tester limit). . Gate charge is 195 nC at Vgs = 10 V
And the corresponding packaged overall on-resistance was 3.1 mΩ, as shown in FIG.
After subtracting the measured package resistance of 1.1 mΩ, the die resistance that results in less than 2.0 mΩ is the lowest value we have ever reported to date. However, the simulation and measurement of the on-resistance in the smaller die (see circles in FIG. 29) requires the MOSFET
This suggests that the spreading resistance in the upper surface metal may cause an additional resistance of about 0.5 mΩ. Thus,
Packaging typically accounts for 33% of the total resistance of the packaged product. 0.25mΩcm
^Using only ^two specific on-resistances, 32 Mcells /
The in ² MOSFET can be any of the 30-
Among the V power MOSFETs, we have the lowest specific on-resistance to our knowledge, the UIS of other similar devices,
Unaffected by reliability and area scaling limitations.

[0038]

Embodiment 3 A special problem appears when scaling a 1-of-n design when operating with low gate bias. MOS with rated gate oxide breakdown voltage of 20V or more when gate oxide is thick
FET (here, standardized gate oxide thickness η = 10
(Defined as having 0% or 1), the effect of the trench gate on the PN junction field is minimal. As shown in FIG. 30, the P-channel without deep P + diffusion as disclosed in the above-referenced Bulucea patent, or without voltage clamping from distributed diodes as disclosed herein. MEDICI simulation of the device shows avalanche breakdown occurring at the PN junction. However, to optimize the MOSFET for low voltage operation, the gate oxide layer is scaled down (ie, thin).
To achieve a low threshold voltage (without channel punch-through) and a high channel transconductance. For a thin gate oxide, for example, for η = 35% as shown in FIG. 31, field plate induced (FPI) avalanche breakdown occurs at locations adjacent to the gate electrode that do not coincide with the PN junction, and This reduces the breakdown voltage of the device and exposes the gate oxide to the risk of hot carrier generation. In the case of a MOSFET having a deep diffusion according to the above-referenced Bulucea patent, the diode clamp cell has an FPI (see FIG. 32) as a result of the gate being electrostatically shielded by the depletion region associated with the deep diffusion. Low sensitivity to M with flat bottom body region
To protect the OSFET, the breakdown voltage of the 1-of-N diode is set substantially lower than the voltage at which FPI breakdown occurs (see FIG. 32). FP
By overcoming the I problem, higher cell densities can be fully utilized to improve epitaxial region utilization and reduce channel resistance (which reduces total on-resistance at low gate bias).

A P-channel MOSFET was fabricated according to the 1-of-N principle described herein. MOSF
The drain of the ET was designed for 20V operation by known techniques. The cell density was set at 32 Mcells / in ² , the gate oxide was thinned to η = 60%, and the threshold voltage was set at 1.3V. A die for a 10-A rated SO-8 size package that induced 50A or more with a gate bias of only 2.5V was used. FIG. 33 shows the IV characteristics of the device. As shown in FIG. 34, the measured specific on-resistance was 850 at a gate bias of 2.5V.
μΩ-cm ² and 75 at 2.7V gate bias.
It was 0 μΩ-cm ² . To our knowledge, the P-channel MOSFE at low gate bias (<3V) operation
This is the smallest on-resistance reported so far for T. The ON resistance measured at a gate bias of 4.5 V was only 526 μΩ-cm ² . SO
The on-resistance of the -8 package is 11 mΩ, which, to our knowledge, is the lowest on-resistance reported so far for a P-channel device at a gate bias of 4.5V.

In conclusion, having a regular distribution of inactive deep P + cells in a vertical trench FET requires a voltage clamping mechanism that limits the carrier generation rate and electric field at or near the corners of the trench gate. Bring. In the presence of electrical overload, device reliability and survivability are thereby improved without limiting on-resistance or cell density. The deep P + regions need not extend to the trench edges and can be made smaller than the cell configuration if desired. If the trench overlaps the N + substrate, the deep P + region need not extend below the trench, in which case the PIN diode will
It can also be formed between the region and the N + substrate (FIG. 1)
1). PIN (such as diode D2 in FIG. 11)
A graph showing the breakdown voltage of the diode as a function of the doping concentration and the width of the intermediate or “inherent” region is shown in S.K. M. Sze "Physics of
Semiconductor Devices, "Second Edition (John Wiley & Sons, 1981, p.
105, FIG. 32), and is incorporated herein by reference.

Using the "one-of-n" technique of the present invention, the size of the MOSFET cell is significantly reduced, thereby reducing the area and body contact quality from 12 Mcells / in ² to 32 Mcell.
The cell density can be increased to s / in ² (5 cells / cm ² ). The parameter "n" can vary from 2 (every other cell) to a large number such as 64 or more. Therefore, the ability of a MOSFET to withstand avalanche breakdown depends on the factor n
Although there is a loss in on-resistance compared to a completely flat bottom cell represented by / n-1, it can be controlled by design. In many instances, this loss factor can be adjusted to within a few percent of an ideal flat bottom device.

FIG. 8 shows another MOSFE in which the cells are striped.
FIG. 2 shows a plan view of a T cell. In the MOSFET 80, the cell 8
1, 82, 83 and 84 are active MOSFETs
The cell 85 is a diode cell including a protective P + diffusion. Each cell 81-84 includes a P + contact region 87 and an N + source region 88. 8 show two contact holes 89, a metal layer (not shown) and P + regions 8 of MOSFET cells 81-84.
7 and N + source regions 88 and diode cells 85
Is used to provide a contact portion with the P + region 86 of FIG. The contact holes 89 can be arranged in various patterns over the cells 81-85. Gate 9
1 is also shown.

Another use of the P + diode cell is to clamp the drain voltage to protect the gate oxide layer from overloading due to excessive electric fields between the gate and the N + substrate. This situation is caused in particular in embodiments in which the trench extends into the substrate and so the gate oxide layer at the bottom of the trench is exposed to the full potential difference between the gate and the substrate. About 8M silicon dioxide
It can withstand a voltage equal to V / cm. Safety factor 5
Using 0%, X _OX · 4 MV / cm is generally used during manufacture.
(Where X _OX is the thickness of the gate oxide in cm) is considered the maximum voltage applied between the gate oxide layers. Therefore, the breakdown voltage of the diode formed by the protective P + diffusion should not exceed X _OX · 4 MV / cm. For example, if an oxide layer having a thickness of 400 angstroms is used, the oxide layer will break down at about 32V, but for reliable operation the maximum voltage should be limited to 16V.

FIGS. 9-11 show cross-sectional views of several alternative embodiments according to the present invention. FIG. 9 shows a MOSFET 92 in which a trench extends into the N + substrate.
The thin layer of the N-epitaxial layer is
3, the diode cell 94 has a protective P
The + diffusion portion reaches the upper surface of the N + substrate 13. In the MOSFET 100 shown in FIG.
The P- body region in 01 extends to the upper surface of the N + substrate 13, leaving no N-doped region of the epitaxial layer. The MOSFET 110 shown in FIG. 11 has a thin portion of the epitaxial layer 14, doped P- or N-.
Are the MOSFET cell 111 and the MOSFET cell 11
2 are left in each.

In FIG. 9-11, the diode D1 is a MOS.
Diode D2 represents the PN junction in the protective diode cell, and capacitor C1 represents the gate oxide layer abutted on the gate and N + substrate. In all three cases, the relation BV _D2 <50
% · BV _C1 must be maintained. However, BV
_D2 is a breakdown voltage of the diode D2 and BV
_C1 is a breakdown voltage of the capacitor C1. The breakdown voltage of the diode D2 is lower than the breakdown voltage of the diode D1 in each case.

A MOSFET 120 is shown in FIG. 12 and is represented similarly to the conventional MOSFET shown in FIG. 2A. The diode D1 is connected to each MOS by the connection of the shallow P + contact region, P- body and N +
2 represents a PIN diode formed in the center of a FET cell. In MOSFET 120, the breakdown voltage of PIN diode D1 is set to be less than 50% of the breakdown voltage of capacitor C1, and the breakdown voltage of the capacitor reduces the thickness of the gate oxide layer by cm.
It is calculated based on 8 MV / cm when expressed in units. As a result, in MOSFET 120, if breakdown does occur, it will occur in the central region of the individual cell and at a voltage that does not damage the gate oxide.

A further alternative embodiment is shown in FIGS. 13 and 14, which shows the XII shown in the plan view of FIG.
It is sectional drawing seen in the cross section of IA-XIIIA. MOSF
The ET 130 includes a cell 121 and a wide cell 131 including a deep P + region 132. The deep P + region 132
While having the function of protecting the gate oxide layer of the cell 121, it itself functions as an active MOSFET cell and has an N + source region 133. Thus, although cell 131 reduces the overall cell density of the MOSFET, the loss associated with on-resistance is less than if cell 131 only performed a protection function and did not conduct current.
As in the case of the MOSFET 120 of FIG.
1 will generally be smaller than if each cell contains a deep P + region for protection.

While there are many ways to fabricate a MOSFET in accordance with the present invention, FIGS. 15-19 illustrate a typical method for fabricating MOSFET 30 shown in FIG.

In FIG. 15, the starting point is the conventional N + substrate 13, and the N- epitaxial layer 14 is grown on the upper surface by using a known method.

A thick oxide layer 140 is grown, masked and etched, and a thin oxide layer 141 is grown on top of the substrate where the deep P + region 38 is to be formed. Thereafter, a dose of 1 × 10 ¹⁴ to 7 × 10 ¹⁵ cm ^-2 and 60
A deep P + region 38 is implanted through the thin oxide layer 141 with an energy of -100 keV. The resulting structure is shown in FIG. The oxide layers 140 and 141 are removed.

In one variation of the method, a thick oxide layer 142 is grown and then removed by photomasking except on the deep P + regions 38 and a thin oxide layer 143 is formed.
Grows. The thin oxide layer 143 is masked, and FIG.
Is removed from the portion of the structure where the trench is to be formed. The trench is masked and etched using known techniques of reactive ion etching or plasma dry etching. The trench is oxidized to form a gate oxide layer 31A and polysilicon is deposited in the trench until it overflows the top surface of the trench. Then the polysilicon is 5 × 10 ¹³ to 5 ×
Phosphorus is doped by POCl ₃ pre-deposition or ion implantation at a dose of 10 ¹⁵ cm ^-2 and an energy of 60 keV to give a sheet resistance of 20-70 Ω / □. P
-For channel devices, the polysilicon is doped with boron using ion implantation to a sheet resistance of approximately 40-120 ohms / square. The polysilicon is then etched until the surface of the trench returns flat, except where the mask protects, so that it can generally contact the metal layer.

After that, the P-body 33 is thinned
3 (eg, 1 × 10 ¹³ to 4 × 1
Boron is implanted with a dose of 0 ¹⁴ cm ^-2 and an energy of 40-100 keV). A similar method is used in fabricating P-channel devices, except that the dopant is phosphorus. The resulting structure is shown in FIG.

After that, the N + source region is masked and 5 ×
A dose of 10 ¹⁴ to 1 × 10 ¹⁶ cm ^-2 and 20-10
Arsenic ion implantation (or boron implantation in the case of a P-channel device) is performed at an energy of 0 keV. The resulting structure is shown in FIG.

Following the formation of the N + source region 38,
The new mask is formed, a shallow P + region 33A used to contact the P- body, from 1 × 10 ¹³ 5
It is introduced by ion implantation at a dose of × 10 ¹⁴ cm ^-2 and an energy of 20-80 keV. Alternatively, FIG.
As shown in FIG. 9, a shallow P + region 33A is formed by implanting a P-type dopant through the same mask used in forming the contact holes for the N + source / P + contact region and the deep P + region. You. Using this technique, several P-type dopants are
Although implanted in the + source region 34, the level of the P- type dopant is not sufficient to concentrate the N- type ions in the N + source region.

A thin oxide layer is grown thermally. Thereafter, BPSG is deposited on the surface of the substrate. The BPSG flows instantaneously from approximately 850 ° C. to 950 ° C. to flow smoothly and further flatten the surface of the die.
The contact hole is etched in the oxide and BPSG layers and a metal layer 36 is deposited, forming a contact between the source and body regions and the deep P + region through the contact hole. Thereby, the MOSFE shown in FIG.
T30 is generated.

The die is then passivated using SiN or BPSG and the pad mask window is etched to facilitate bonding.

A series of simulations and experiments were performed to determine the range of parameters for producing various commercially available products. They are 20-V and 30-V rated drain potentials, 12-V and 20-V rated gate potentials, and N-channel and P-channel devices. "1
It was desired to specify a range of parameters that would make the device an "-of-N" diode cell that would break down before the MOSFET cell. Two approaches were used. One involves (i) a "reach-through" approach involving the use of a PIN-type diode with a breakdown voltage mainly determined by the thickness of the intermediate layer, and the other involves (ii) two sub-layers An epitaxial layer is used with a deep diffusion in the diode cell that overlays the underside of the sublayer.
i "approach.

The first set of tests addressed a "reach-through" structure of the type shown in FIG. 35, including a MOSFET cell 270 and a diode cell 272. The diode cell includes a deep P + diffusion 274 extending 3 μm below the surface of the epitaxial layer. FIG. 35 shows an N-channel device. The results of a test in which the P-channel device has the same overall structure but the conductivity type will be reversed is shown in FIG. 36, where the vertical axis is the breakdown voltage and the horizontal axis is 2 "Flat" portion of the epitaxial layer (Xepi (flat))
I.e., the portion that is relatively constant in the concentration of the N-type dopant before beginning to increase in the transition region between the N- epitaxial layer and the N + substrate. This transition region is indicated by a hatched region 276 in FIG.

FIG. 36 shows test data associated with a 20-V drain, a 12-V gate, and an N-channel device. The first set of curves 280, 282 and 284
The dopant concentration of the N-epitaxial layer is 1.
0 × 10 ¹⁶ cm ⁻³ , 2.0 × 10 ¹⁶ cm ⁻³ , 3.0 × 1
It shows the breakdown voltage of the device when it is 0 ¹⁶ cm ^-3 . The thickness of the gate oxide layer is 300 Å and the target drain rating is 20V.
If Xepi (flat) is less than 3 μm thick, breakdown will occur in diode cell 272 and Xepi (flat)
(Flat)). Xepi (flat)
Is greater than approximately 4 μm thick, the breakdown is M
Occurs in OSFET 270, so the breakdown voltage is no longer dependent on Xepi (flat).

The curves 286 and 288 in FIG.
2.0 × 10 ¹⁶ cm ^-3 and 3.0 × 10 ¹⁶ cm ^{-3 respectively}
MOSFET cell 270 at N-epitaxial concentration
5 shows the difference between the breakdown voltage between the diode cell 272 and the diode cell 272. Assuming that the difference in breakdown voltage between the MOSFET cell and the diode cell is acceptable up to approximately 5 V, an N-epi concentration of 2.0 × 10 ¹⁶ cm ⁻³ and a Xepi (flat) of 3 μm are satisfactory. Will bring the device. In other situations, other devices with parameters within the ranges shown in FIG. 36 will give satisfactory results.

FIG. 37 shows a similar set of curves for "reach-through" 30-V drain, 20-V gate and N-channel devices with a gate oxide layer thickness of 500 Angstroms. Curves 290, 292 and 2
94 indicates that the concentration of N-epi was 5.0 × 10 ¹⁵ c
The breakdown voltage of the device at m ^-3 , 1.0 × 10 ¹⁶ cm ^-3 and 2.0 × 10 ¹⁶ cm ^-3 is shown. Curves 296, 298, and 299 show that the N-epitaxial concentration is 5.0 × 10 ¹⁵ cm ⁻³ and 1.0 × 10 ¹⁶ cm, respectively.
³ shows the difference between the breakdown voltage of MOSFET cell 270 and diode cell 272 at 2.0 × 10 ¹⁶ cm ⁻³ .

The curves in FIGS. 36 and 37 were created by simulation. Data points (squares, triangles, diamonds, etc.) represent actual experimental results.

FIG. 39 shows the experimental results obtained from the device shown in FIG. 38, and FIG.
N-epi layers, ie different concentrations of N-
-Layers N-epi1 and N-
epi2, which is described in U.S. Patent No. 5,674,766, filed October 7, 1997. This is the "step ep" of the 20-V drain and the 12-V gate.
i-device ". The upper sub-layer N-epi2 is 3.5 microns thick (Xepi2), but in other embodiments, N-epi2 is in the range of 2 m to 5 m.
The trench and P-body region in MOSFET cell 300 extends only in upper sublayer N-epi2, while the deep P + diffusion in diode cell 302 is Ne-e.
It passes through pi2 and extends into the lower sub-layer N-epi1. For P-channel devices, the conductivity types will be opposite. In FIG. 39, the horizontal axis is the lower sublayer N-epi
1.0 × 10 ¹⁶ c
It varies from m ⁻³ to 1.0 × 10 ¹⁸ cm ⁻³ . Curve 31
0, 312 and 314 are the upper sub-layer N-epi
2 has a dopant concentration of 5.0 × 10 ¹⁵ cm ⁻³ ,
The breakdown voltage of the device at 1.0 × 10 ¹⁶ cm ⁻³ and 1.5 × 10 ¹⁶ cm ⁻³ is shown. Broken line 31
6, 318 and 319, the sub-layer N-epi1 has 5.0 × 10 ¹⁵ cm ⁻³ and 1.0 × 10 ¹⁶ c, respectively.
m ⁻³ , MOSFET cell 300 and diode cell 302 when having a dopant concentration of 1.5 × 10 ¹⁶ cm ⁻³
3 shows the difference between the breakdown voltages. In these embodiments, the sub-layer N-epi1
0 and the breakdown voltage of the diode cell 302 are made sufficiently thick so as not to depend on the thickness of the sublayer N-epi1.

FIG. 40 is a graph showing the breakdown voltage (horizontal axis) in a diode cell as a function of the resistivity (vertical axis on the left) and the dopant concentration (vertical axis on the right) of the lower sublayer N-epi1.

FIGS. 41, 42 and 43 show similar data for a step epi N-channel device having a 30-V drain and a 20-V gate. In FIG. 41, curve 330 shows the breakdown voltage of the MOSFET cell, curve 332 shows the breakdown voltage of the diode cell, and curve 334 shows the difference between the breakdown voltage in the MOSFET cell and the diode cell. The dopant concentration for the lower epi sublayer is 4 × 10 ¹⁶ cm ⁻³ and the upper sublayer is 3.5 μm.
m thickness. The horizontal axis represents the dopant concentration of the upper epi sublayer, from 5.0 × 10 ¹⁵ cm ^{−3 to} 2.5.
It is in the range of × 10 ¹⁶ cm ^-3 . This range is 3.0 × 10
Expandable to ¹⁶ cm ^-3 , 2.0 × 10 ¹⁶ cm
^-3 is a preferred concentration.

FIGS. 42 and 43 show data for similar devices in different forms. In FIG. 42, curve 340 shows the breakdown voltage for the MOSFET cell, curve 342 shows the breakdown voltage for the diode cell, and curve 344 shows the difference between the two values. The dopant concentrations for the upper and lower epi sublayers were 1.0 × 10 ¹⁶ cm ⁻³ and 4.0 × 1, respectively.
0 ¹⁶ cm ^-3 . The horizontal axis represents the thickness of the upper sublayer, which is in the range of 2 μm to 5 μm, and is publicly 3 μm. In FIG. 43, curve 350 shows the breakdown voltage for the MOSFET cell, curve 352 shows the breakdown voltage for the diode cell, and curve 354.
Indicates the difference between the two values. The dopant concentration and thickness of the upper epi sublayer are 1.0 × 10 ¹⁶ cm ⁻³ , respectively.
And 3.5 μm. The horizontal axis represents the dopant concentration of the lower epi sublayer, and is 1.0 × 10 ¹⁶ cm ⁻³ or ^less .
5.0 × 10 ¹⁶ cm ⁻³ , preferably 4.0 × 10 ¹⁶ cm ^−3.
10 ¹⁶ cm ^-3 .

FIG. 44 shows similar data for a 30-V drain, 20-V gate P-channel device, which utilizes a "reach-through" approach. Curves 360, 362 and 364 are P-
It shows the breakdown voltage of the diode cell when the thickness of the epi layer changes from 4 μm to 8 μm, and is 5.0 × 10 ¹⁵ cm ⁻³ , 1.0 × 10 ¹⁶ cm ⁻³ , 2.0, respectively.
Indicates a P-epi concentration of × 10 ¹⁶ cm ⁻³ . Curve 36
6, 368 and 369 are the same level of Pe
4 shows the difference between the breakdown voltage of a MOSFET cell and a diode cell at pi concentration.

FIGS. 45 and 46 illustrate the P-channel 20-V
Shown is data for a drain, 12-V gate device, which used a "reach-through" approach. In both figures, the breakdown voltage is plotted as a function of the P-epi layer thickness. Curves 370 and 380 show a Pe of 5.0 × 10 ¹⁵ cm ^−3.
The diode breakdown voltage at pi dopant concentration is shown, curves 372 and 382 are 1.0 × 10 ¹⁶
The diode breakdown voltage at a P-epi dopant concentration of cm ^-3 is shown, and curves 374 and 384 show
4 shows the diode breakdown voltage at a P-epi dopant concentration of 2.0 × 10 ¹⁶ cm ⁻³ . Curve 376
And 386 show the difference in breakdown voltage between the diode cell and the MOSFET cell at a P-epi dopant concentration of 5.0 × 10 ¹⁵ cm ⁻³ , curve 37
8 and 388 show the difference in breakdown voltage between the diode cell and the MOSFET cell at a P-epi dopant concentration of 1.0 × 10 ¹⁶ cm ⁻³ , curve 3
79 and 389 show the difference in breakdown voltage between the diode cell and the MOSFET cell at a P-epi dopant concentration of 2.0 × 10 ¹⁶ cm ⁻³ .

With a P-channel 20-V drain device, it is somewhat difficult to break down the diode cells before the MOSFET cells. With thinner gate oxides, as described above, FPI breakdown tends to occur before PN junction breakdown. Thus, either increasing the dose of the implant used to form the diffusion in the diode cell, or using a special drive-in process to increase the depth of the diode diffusion May be required. FIG. 45 shows the result of a “standard” implant dose of 1.0 × 10 ¹⁵ cm ⁻² , but for 1-3 hours,
Two drive-ins at 1050-1100 ° C are used. FIG. 46 shows the result of an implantation dose of 4.0 × 10 ¹⁵ cm ⁻² , but for 1-3 hours, 1050-1100
Two drive-ins at C are used.

FIG. 47 shows the breakdown voltage for an approximately 3 μm deep N-type diode diffusion at six different implant doses, 1.0 × 10 ¹⁵ cm ⁻² (curve 39).
0), 2.0 × 10 ¹⁵ cm ⁻² (curve 391), 3.0 ×
10 ¹⁵ cm ^-2 (curve 392), 4.0 × 10 ¹⁵ cm
^-2 (curve 393), 5.0 × 10 ¹⁵ cm ^-2 (curve 39
4) In the case of 6.0 × 10 ¹⁵ cm ⁻² (curve 395),
Shown as a function of P-epi layer thickness.

FIG. 48 shows the breakdown voltage for an approximately 3 μm deep N-type diode diffusion at seven different P-epi layer thicknesses, 9.0 μm (curve 400), and 8.
75 μm (curve 401), 8.5 μm (curve 402),
8.25 μm (curve 403), 8.0 μm (curve 40)
4), 7.75 μm (curve 405), and 7.5 μm (curve 406) as a function of implant dose.

The above embodiments are merely illustrative and not limiting. Numerous alternative embodiments according to the broad principles of the present invention will be apparent to those skilled in the art.

[0073]

As described above, the formation of the diode cell according to the present invention prevents the occurrence of breakdown at the bottom of the trench, avoids damage to the MOSFET, and improves the trench gate type M with improved on-resistance characteristics.
An OSFET can be provided.

[Brief description of the drawings]

FIG. 1 shows a conventional trench gate type M having a deep central diffusion to reduce the electric field at the corners of the trench.
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 2 is a cross-sectional view of a conventional trench-gate MOSFET consisting of A and B, without A having a deep central diffusion and having a trench extending into the substrate;
It is an equivalent circuit diagram with respect to T.

FIG. 3 is a cross-sectional view of a first embodiment of the present invention having a protective diffusion in an adjacent MOSFET cell.

FIG. 4 comprises A and B, wherein A has a protective diffusion in an adjacent MOSFET cell and a trench extends into the substrate;
FIG. 6 is a cross-sectional view of a second embodiment of the present invention, wherein B is a MOS of A;
FIG. 3 is an equivalent circuit diagram for the FET.

FIG. 5 is a plan view of a conventional MOSFET cell.

FIG. 6 is a plan view of a square cell type MOSFET according to the present invention.

FIG. 7 is a detailed plan view of the square cell type MOSFET of FIG. 6;

FIG. 8 is a plan view of a striped MOSFET according to the present invention.

FIG. 9 is another sectional view of the second embodiment according to the present invention.

FIG. 10 is a sectional view of a third embodiment according to the present invention.

FIG. 11 is a sectional view of a fourth embodiment according to the present invention.

FIG. 12 is a sectional view of a fifth embodiment according to the present invention.

FIG. 13 is a sectional view of a sixth embodiment having a wide protection cell.

FIG. 14 is a plan view of the sixth embodiment shown in FIG.

FIG. 15 is a diagram showing each step of a step of manufacturing the MOSFET shown in FIG. 3;

FIG. 16 is a diagram showing each step of a step of manufacturing the MOSFET shown in FIG. 3;

FIG. 17 is a diagram showing each step of a step of manufacturing the MOSFET shown in FIG. 3;

FIG. 18 is a diagram illustrating each step of a process of manufacturing the MOSFET illustrated in FIG. 3;

FIG. 19 is a diagram showing each step of a step of manufacturing the MOSFET shown in FIG. 3;

FIG. 20 shows a simulation of current lines in a MOSFET having a flat bottom body region and a MOSFET having a deep central body diffusion as disclosed in US Pat. No. 5,072,266.

FIG. 21 shows a simulation of current lines in a MOSFET having a flat bottom body region and a MOSFET having a deep central body diffusion, as disclosed in US Pat. No. 5,072,266.

FIG. 22 shows a MOS showing the geometric relationship between current spreading angle and depth in the epitaxial layer where uniform conduction is achieved.
It is a figure of FET.

FIG. 23 is a graph showing the specific on-resistance as a function of cell density for a MOSFET with a deep central diffusion and a MOSFET with distributed diode cells.

FIG. 24: 12 Mcells / in ² and 32, respectively.
MOSFET having a cell density of Mcells / in ²
6 is a graph showing the variation of the specific on-resistance as a function of the gate bias with respect to FIG.

FIG. 25 shows a simulation of the current lines in a MOSFET having MOSFET cells operating in the linear region during normal conduction and undergoing avalanche breakdown.

FIG. 26 shows a simulation of a current line in a MOSFET having a diode cell operating in a linear region during normal conduction and undergoing avalanche breakdown.

FIG. 27 is a graph showing unclamped inductive switching current and drain voltage in a MOSFET.

FIG. 28 is a diagram showing measured IV characteristics and breakdown characteristics of a MOSFET.

FIG. 29 illustrates the on-resistance of various components of a packaged MOSFET as a function of gate bias.

FIG. 30: Flat bottom M with relatively thick gate oxide layer
6 is a simulation illustrating a position of avalanche breakdown in an OSFET.

FIG. 31: Flat bottom M with relatively thin gate oxide layer
6 is a simulation illustrating a position of avalanche breakdown in an OSFET.

FIG. 32: MOSFET with deep central body diffusion
4 is a graph showing the breakdown voltage as a function of the normalized gate oxide thickness for the case of FIG. The MOSFET has a flat-bottomed body region and has distributed diode cells according to the invention.

FIG. 33 is a graph showing IV characteristics of a MOSFET.

FIG. 34: 12Mcells / in ² and 32Mcell
MO of thin (12-V gate rated) and thick (20-V gate rated) oxides with cell density of ls / in ²
5 is a graph showing the specific on-resistance for an SFET as a function of gate bias.

FIG. 35 is a cross-sectional view of a “reach-through” type MOSFET structure including a MOSFET cell and a diode cell.

FIG. 36. 20- Using a “reach-through” approach
5 is a graph showing breakdown voltage as a function of epitaxial layer thickness for a V-drain, 12-V gate N-channel MOSFET.

FIG. 37. 30- Using “reach-through” approach
5 is a graph showing breakdown voltage as a function of epitaxial layer thickness for a V-drain, 20-V gate N-channel MOSFET.

FIG. 38 is a cross-sectional view of a “step-type epi” type MOSFET structure including a MOSFET cell and a diode cell.

FIG. 39. Using a “stepped epi” approach 2
0-V drain, 12-V gate N-channel MOSFE
FIG. 7 is a graph showing the breakdown voltage as a function of dopant concentration in the lower epi sublayer at T. FIG.

FIG. 40 is a graph showing the breakdown voltage in a diode cell (horizontal axis) as a function of the resistivity and dopant concentration of the lower epi sublayer.

FIG. 41. Using a “stepped epi” approach 3
0-V drain, 20-V gate N-channel MOSFE
9 is a graph showing various data in the case of T.

FIG. 42. 3 using “stepped epi” approach
0-V drain, 20-V gate N-channel MOSFE
9 is a graph showing various data in the case of T.

FIG. 43. Using the “stepped epi” approach 3
0-V drain, 20-V gate N-channel MOSFE
9 is a graph showing various data in the case of T.

FIG. 44. 30- Using “reach-through” approach
5 is a graph showing various data for a V-drain, 20-V gate P-channel device.

FIG. 45 is a graph showing the breakdown voltage of a diode cell, and the difference between the breakdown voltage for a diode and a MOSFET, as a function of epi concentration for different implantation doses and drive-in times for diode diffusion.

FIG. 46 is a graph illustrating the breakdown voltage of a diode cell, and the difference between the breakdown voltage for a diode and a MOSFET, as a function of epi concentration for different implant doses and drive-in times for diode diffusion.

FIG. 47 shows the breakdown voltage for N-type diode diffusion, P-epi for six different implant doses.
4 is a graph showing as a function of layer thickness.

FIG. 48 is a graph showing the breakdown voltage for N-type diode diffusion as a function of implant dose for seven different P-epi layer thicknesses.

[Explanation of symbols]

REFERENCE SIGNS LIST 10 MOSFET cell 11 trench gate 12 N + source region 13 N + substrate 14 N− epitaxial layer 15 deep P + diffusion 16 P− body 17 channel 20 MOSFET cell 21 gate trench 21 A gate oxide layer 21 C gate trench corner 22 P-body region Reference Signs List 30 trench gate type MOSFET 31 gate 31A gate oxide layer 32 trench 33 P-body region 33A P + contact region 34 N + source region 35 MOSFET cell 36 metal layer 37 adjacent MOSFET cell 38 diffusion unit 39 PN junction 40 MOSFET 41 MOSFET cell 42 Adjacent cell 43 Trench 44 Protective P + diffusion 45 Gate 45A Gate oxide layer 80 MOSFET 81 Active MOSFET cell 82 Active M SFET cell 83 Active MOSFET cell 84 Active MOSFET cell 85 Diode cell 86 P + region 87 P + Contact region 88 N + Source region 89 Contact hole 90 Contact hole 91 Gate 92 MOSFET 93 MOSFET cell 100 MOSFET 101 MOSFET cell 110 MOSFET 111 MOSFET cell 112 MOSFET cell Reference Signs List 120 MOSFET 121 cell 130 MOSFET 131 cell 132 Deep P + region 133 N + source region 140 Thick oxide layer 141 Thin oxide layer 142 Thick oxide layer 143 Thin oxide layer 170 Curve of MOSFET with deep P + diffusion 172 Distributed diode MOSFET with cells
Curve 270 MOSFET cell 272 Diode cell 274 Deep P + diffusion 276 Shaded area 280-299 Curve 300 MOSFET cell 302 Diode cell 310-314 Curve 316-319 Broken line 330-406 Curve

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Richard Kay Williams, Inventor 95014, Coopertino Norwich Avenue, California 10292 Coat 12891

Claims (17)

[Claims] 1. A trench gate type power MOSFET
A semiconductor material; a gate disposed in a trench formed in a surface of the semiconductor material; and a protection diffusion of a second conductivity type, wherein the trench stores a plurality of MOSFET cells. And each of the MOSFETs has a source region of a first conductivity type and a body region of the second conductivity type adjacent to the source region, wherein the source region and the body region are defined by side surfaces of the trench. Wherein the protective diffusion portion is adjacent to the first conductivity type region so as to form a diode, and the diode is connected in parallel to a channel region of each MOSFET cell. Trench gate type power MOSFET
T. 2. The MOSFET of claim 1 wherein said trench defines a diode cell and said protective diffusion is located within said diode cell. 3. The MOSFET according to claim 2, wherein the semiconductor material has a substrate and an epitaxial layer formed on a surface of the substrate. 4. The MOSFET of claim 3, wherein a bottom of the trench is located in the epitaxial layer and is separated from an interface between the substrate and the epitaxial layer. 5. The MOSFET according to claim 4, wherein a bottom portion of the protection diffusion portion is disposed in the epitaxial layer and is separated from an interface between the substrate and the epitaxial layer. 6. The protection diffusion unit according to claim 1, wherein
The MOSFET according to claim 5, wherein the MOSFET is short-circuited to the source region of a T cell. 7. The semiconductor device according to claim 2, further comprising a plurality of said diode cells, wherein said diode cells are arranged at regular intervals in a lattice formed by said gate.
2. The MOSFET according to 1. 8. The MOSFET of claim 7, wherein there is a predetermined number of said MOSFET cells per diode cell. 9. The MOSFE of claim 3, wherein a bottom of the trench is located in the substrate.
T. 10. The MOSFET according to claim 9, wherein a bottom portion of the protection diffusion portion is disposed at an interface between the substrate and the epitaxial layer. 11. The first conductivity type region in the epitaxial layer defines the body region as the MOSFET.
The MOSFET of claim 9, wherein the MOSFET is isolated from the substrate in a cell. 12. The MOSFE of claim 2, wherein said trenches form a grid of square cells.
T. 13. The MOSFE of claim 2, wherein said trenches form a grid of striped cells.
T. 14. The method of claim 9, wherein the gate is separated from the substrate material by a gate oxide layer, and the diode has a breakdown voltage lower than a voltage that damages the oxide layer. MOS described in
FET. 15. The device of claim 1, wherein the first conductivity type region in the epitaxial layer separates the protective diffusion from the substrate of the diode cell.
2. The MOSFET according to 1. 16. A trench gate type power MOSFET.
A semiconductor material having a substrate and an epitaxial layer formed on a surface of the substrate, and a gate formed in the trench and separated from the semiconductor material by an oxide layer, wherein the trench is Formed in the surface of the epitaxial layer,
And extending into the substrate, and the trench includes a plurality of M
An OSFET cell is defined, wherein each of the MOSFET cells has a source region of a first conductivity type and a body region of a second conductivity type adjacent to the source region, wherein the source region and the body region are of the trench. A body region adjacent to the first conductivity type drain region; a PN junction between the body region and the drain region forming a diode; A trench gate type power MOSFET having a breakdown voltage lower than a voltage that damages an object layer. 17. The semiconductor device according to claim 17, wherein the body region is provided with each of the MOSFETs.
17. The MOSFET of claim 16, wherein the MOSFET is shorted to the source region of a T cell.