CN110265300A - Enhance the method for infinitesimal born of the same parents structure I GBT short-circuit capacity - Google Patents
Enhance the method for infinitesimal born of the same parents structure I GBT short-circuit capacity Download PDFInfo
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- CN110265300A CN110265300A CN201910525348.5A CN201910525348A CN110265300A CN 110265300 A CN110265300 A CN 110265300A CN 201910525348 A CN201910525348 A CN 201910525348A CN 110265300 A CN110265300 A CN 110265300A
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- 238000000034 method Methods 0.000 title claims abstract description 20
- 230000002708 enhancing effect Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000001413 cellular effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Ceramic Engineering (AREA)
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Abstract
The present invention relates to the methods of enhancing infinitesimal born of the same parents structure I GBT short-circuit capacity, the IGBT technique initial stage, first trench is dug in the region Cell Mesa Dummy, then extension is grown, form deeper P rod structure, behind after Trench structure formed, this P post region domain is formed deep P+ structure, when short circuit occurs, for the size of limiting short-circuit current.When short circuit occurs, this method can effectively limiting short-circuit current size, enhance the ability of chip short circuit tolerance, avoid the accidental damage of chip, improve the robustness of chip, in the case where not influencing infinitesimal born of the same parents' structure I GBT and turning on and off loss, reduces short circuit current, improve the short-circuit tolerance of chip.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of side for enhancing infinitesimal born of the same parents structure I GBT short-circuit capacity
Method.
Background technique
IGBT (Insulated Gate Bipolar Transistor), insulated gate bipolar transistor is (double by BJT
Polar form triode) and MOS (insulating gate type field effect tube) composition compound full-control type voltage driven type power semiconductor,
Have advantage of both the high input impedance of MOSFET and the low conduction voltage drop of GTR concurrently.GTR saturation pressure reduces, and current carrying density is big,
But driving current is larger；MOSFET driving power very little, switching speed is fast, but conduction voltage drop is big, and current carrying density is small.IGBT is comprehensive
The advantages of both the above device, driving power is small and saturation pressure reduces.Therefore its application is also more and more extensive, is a kind of important
Power semiconductor.
With the development of IGBT technology, chip area is smaller and smaller, and current density is increasing.But with gully density
Increasing, there has been a problem, be exactly that the short circuit current of IGBT becomes larger therewith, pipe short circuit tolerance obviously dies down.Visitor
Family in application process, can encounter some extreme cases, cause IGBT easily damaged.In this case, if with routine
Method improves short-circuit capacity, then can sacrifice conduction voltage drop or switching loss.
Summary of the invention
The object of the present invention is to provide a kind of methods for enhancing infinitesimal born of the same parents structure I GBT short-circuit capacity, can not influence to lead
Under the premise of logical pressure drop and switching loss, the short-circuit capacity of IGBT is improved.
The technical scheme adopted by the invention is as follows:
Enhance the method for infinitesimal born of the same parents structure I GBT short-circuit capacity, it is characterised in that:
The IGBT technique initial stage first digs trench in the region Cell Mesa Dummy, then grows extension, forms deeper P
Rod structure, behind after Trench structure formed, this P post region domain is formed deep P+ structure, short for limiting when short circuit occurs
The size of road electric current.
Specifically includes the following steps:
Step 1, the silicon wafer for choosing the suitable resistivity of N-type；
Step 2, N- silicon substrate on according to cellular the region Dummy, first dig Trench；
Step 3, the growth for carrying out p-type epitaxial layer；
Step 4 removes the P layer on surface；
Step 5, the Trench structure for having dug device, and long grid oxygen；
Step 6 carries out Pwell injection；
Step 7 drives in p-well；
Step 8 carries out N+ injection；
Step 9 clicks interlayer dielectric layer, and carries out hole etching；
Step 10, deposited metal simultaneously carry out positive passivation；
Step 11 carries out back side injection and annealing process, forms backside structure；
Step 12, deposit back metal structure, are completed.
In step 4, the P layer on surface is removed by way of CMP or returning quarter.
The invention has the following advantages that
Invention of the present invention does some deep P columns in the region chip front side Dummy cellular Mesa.When collector low pressure, it can be normal
Work, do not influence conducting and switching loss；When current collection extra-high voltage, the P column in the region Dummy can exhaust rapidly, to electric current shape
At pinch off, the size of electric current is limited.Occur short circuit when, can effectively limiting short-circuit current size, enhance core
The ability of piece short circuit tolerance, avoids the accidental damage of chip, improves the robustness of chip, do not influencing micro- structure cell
In the case that IGBT turns on and off loss, short circuit current is reduced, improves the short-circuit tolerance of chip.
Detailed description of the invention
Fig. 1 is step 1 schematic diagram.
Fig. 2 is step 2 schematic diagram.
Fig. 3 is step 3 schematic diagram.
Fig. 4 is step 4 schematic diagram.
Fig. 5 is step 5 schematic diagram.
Fig. 6 is step 6 schematic diagram.
Fig. 7 is step 7 schematic diagram.
Fig. 8 is step 8 schematic diagram.
Fig. 9 is step 9 schematic diagram.
Figure 10 is step 10 schematic diagram.
Figure 11 is step 11 schematic diagram.
Figure 12 is step 12 schematic diagram.
Figure 13 is not use IGBT structure of the invention.
Specific embodiment
The present invention will be described in detail With reference to embodiment.
Current infinitesimal born of the same parents structure I GBT, mainly substantially reduces cellular size, such IGBT core on the original basis
The overcurrent capability of piece enhances, and loss reduces, and the overcurrent capability of unit area gets a promotion, and chip area reduces.But with
The raising of current density, short circuit current is higher and higher, and the short-circuit tolerance of chip is caused to reduce.In this way, igbt chip exists
In, in the case where encountering extreme case, easily it is damaged.If improving the short-circuit capacity of IGBT, and meeting using the prior art
That sacrifices IGBT turns on and off loss.In this case the meaning for doing micro- structure cell also just loses.
The present invention first digs trench in the region Cell Mesa Dummy, then growth is outer in the IGBT technique initial stage
Prolong, form deeper P rod structure, behind after Trench structure formed, this P post region domain is formed deep P+ structure.In IGBT
The region Dummy Cell Mesa, form deep P+ structure, when short circuit occurs, for the size of limiting short-circuit current, improve it
Short-circuit capacity.Specifically includes the following steps:
1, the silicon wafer of the suitable resistivity of N-type is chosen first；
2, some Trench are first dug according to the region Dummy of cellular on the silicon substrate of N-；
3, the growth of p-type epitaxial layer is carried out；
4, remove CMP or by way of returning quarter by the P layer on surface；
5, the Trench structure of device, and long grid oxygen have been dug；
6, Pwell(P diameter is carried out) injection；
7, p-well is driven in；
8, N+ injection is carried out；
9, interlayer dielectric layer is clicked, and carries out hole etching；
10, deposited metal and positive passivation is carried out；
11, back side injection and annealing process are carried out, backside structure is formed；
12, back metal structure is deposited, is completed.
Above-mentioned technical proposal of the invention is the production method of novel infinitesimal born of the same parents' structure I GBT a kind of, can not influenced
Under the premise of conduction voltage drop and switching loss, the short-circuit capacity of IGBT is improved.
The contents of the present invention are not limited to cited by embodiment, and those of ordinary skill in the art are by reading description of the invention
And to any equivalent transformation that technical solution of the present invention is taken, all are covered by the claims of the invention.
Claims (3)
1. enhancing the method for infinitesimal born of the same parents structure I GBT short-circuit capacity, it is characterised in that:
The IGBT technique initial stage first digs trench in the region Cell Mesa Dummy, then grows extension, forms deeper P
Rod structure, behind after Trench structure formed, this P post region domain is formed deep P+ structure, short for limiting when short circuit occurs
The size of road electric current.
2. the method for enhancing infinitesimal born of the same parents structure I GBT short-circuit capacity according to claim 1, it is characterised in that:
Specifically includes the following steps:
Step 1, the silicon wafer for choosing the suitable resistivity of N-type；
Step 2, N- silicon substrate on according to cellular the region Dummy, first dig Trench；
Step 3, the growth for carrying out p-type epitaxial layer；
Step 4 removes the P layer on surface；
Step 5, the Trench structure for having dug device, and long grid oxygen；
Step 6 carries out Pwell injection；
Step 7 drives in p-well；
Step 8 carries out N+ injection；
Step 9 clicks interlayer dielectric layer, and carries out hole etching；
Step 10, deposited metal simultaneously carry out positive passivation；
Step 11 carries out back side injection and annealing process, forms backside structure；
Step 12, deposit back metal structure, are completed.
3. the method for enhancing infinitesimal born of the same parents structure I GBT short-circuit capacity according to claim 2, it is characterised in that:
In step 4, the P layer on surface is removed by way of CMP or returning quarter.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910525348.5A CN110265300B (en) | 2019-06-18 | 2019-06-18 | Method for enhancing short-circuit capability of IGBT with microcell structure |
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| CN201910525348.5A CN110265300B (en) | 2019-06-18 | 2019-06-18 | Method for enhancing short-circuit capability of IGBT with microcell structure |
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| CN110265300B CN110265300B (en) | 2022-11-08 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11195788A (en) * | 1997-10-31 | 1999-07-21 | Siliconix Inc | Trench-gate type power mosfet having protective diode |
| JPH11345969A (en) * | 1998-06-01 | 1999-12-14 | Toshiba Corp | Power semiconductor device |
| US20060081919A1 (en) * | 2004-10-20 | 2006-04-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
| CN1832172A (en) * | 2002-10-31 | 2006-09-13 | 株式会社东芝 | Power semiconductor device |
| US20090096027A1 (en) * | 2007-10-10 | 2009-04-16 | Franz Hirler | Power Semiconductor Device |
| CN107534053A (en) * | 2015-01-14 | 2018-01-02 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
| CN109830532A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | Superjunction IGBT device and its manufacturing method |
-
2019
- 2019-06-18 CN CN201910525348.5A patent/CN110265300B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11195788A (en) * | 1997-10-31 | 1999-07-21 | Siliconix Inc | Trench-gate type power mosfet having protective diode |
| JPH11345969A (en) * | 1998-06-01 | 1999-12-14 | Toshiba Corp | Power semiconductor device |
| CN1832172A (en) * | 2002-10-31 | 2006-09-13 | 株式会社东芝 | Power semiconductor device |
| US20060081919A1 (en) * | 2004-10-20 | 2006-04-20 | Kabushiki Kaisha Toshiba | Semiconductor device |
| US20090096027A1 (en) * | 2007-10-10 | 2009-04-16 | Franz Hirler | Power Semiconductor Device |
| CN107534053A (en) * | 2015-01-14 | 2018-01-02 | 三菱电机株式会社 | Semiconductor device and its manufacture method |
| CN109830532A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | Superjunction IGBT device and its manufacturing method |
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