JPH11195729A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring body which is arranged in a semiconductor device and a high frequency circuit provided with high noise resistance with respect to high frequency signals and a high-speed operation function. SOLUTION: This semiconductor device is provided with an insulation supporting base body, having with an opening 206 smaller than a semiconductor chip 100 and the wiring body 200A composed of wirings for signals, for a power source and for grounding or the like formed by printing on the first surface and second surface of the insulation supporting base body. The wiring body 200A is loaded on the semiconductor chip, bonding pads on the semiconductor chip 100 and the inner pad parts of the respective wirings for the signals, for the power source and for grounding of the wiring body 200A are connected by a first metallic thin wire 401 and the outer pad parts of the respective wirings and leads 301-303 inside a lead frame 300A are connected. A wiring pattern is finely and variously formed and an impedance matching function is provided as well.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor chip and a lead connected to the semiconductor chip, and more particularly to a semiconductor device having a transistor for handling a high frequency signal and having improved characteristics of the high frequency signal.

[0002]

2. Description of the Related Art Conventionally, as a structure of a general semiconductor device, a semiconductor chip and a lead frame are connected by a bonding wire, sealed with a resin, and then a portion of the lead frame outside the resin is cut. What is formed is known.

FIG. 35 is a perspective view showing a structure of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 7-202111. As shown in FIG.
A semiconductor chip 1002 is mounted thereon. A number of outer leads 1003 extend from an outer frame (not shown) on the outer side of the lead frame, and inner leads 1004 connected to the outer leads 1003 extend toward the semiconductor chip 1002. The tips of the leads 1004 and the respective electrode pads 1005 on the semiconductor chip 1002 are connected by bonding wires 1006, respectively. Then, in this state, the semiconductor chip 1002 is
The die pad 1001 and the inner lead 1004 are sealed. However, since the flow of the sealing resin 1010 is blocked by the dam bar 1007 connecting the outer leads 1003, the outer leads 1003 protrude outward from the sealing resin 1010. In this state, a part of the outer leads 1003 including the dam bar 1007 is cut off, and the outer leads 1003 projecting from the sealing resin 1010 are cut off from each other. Due to such a structure of the semiconductor device, the outer lead 1
003 allows signals to be transmitted and received between an external device and an element such as a transistor in the semiconductor chip 1002.

FIG. 36 is a plan view showing the structure of a general lead frame disclosed in Japanese Patent Application Laid-Open No. 6-151681. As shown in FIG.
Are supported on all sides by suspension leads 1008, and outer leads 1004 are
It is connected to the.

[0005]

By the way, in recent semiconductor devices, as the degree of integration of the semiconductor device has increased and the size of the semiconductor chip has been reduced, the number of elements arranged inside the semiconductor chip has been increased. I have. In addition, semiconductor devices that handle high-frequency signals are also frequently used. Therefore, the above-described conventional semiconductor device has the following problems.

That is, as the number of elements increases as the integration density increases, the number of electrode pads on the semiconductor chip increases, and naturally the number of inner leads and outer leads also increases. I have no choice. As a result, there is a possibility that the inner leads 1004 may come into contact with each other due to the flow during resin sealing. In particular, a semiconductor device that handles high-frequency signals has the following problems.

Generally, a voltage drop e due to a current i in an RLC series circuit is expressed by the following equation (1).

E = R ・ i + L ・ di / dt + (1 / C) ∫idt (1) where R is a resistance, L is an inductance, and C is a capacitance. Generally, a system in a package is a distributed constant circuit. Has become. Further, the inductance L includes a self inductance and a mutual inductance.

As can be seen from the above equation (1), if the time change of the current i becomes large, L · di / dt increases,
A voltage corresponding to L · di / dt is generated. Therefore, when the two inner leads come closer to each other, a voltage drop occurs in one of the inner leads due to a mutual inductance proportional to a time change amount of a current flowing through the other inner lead. In other words, noise due to crosstalk and switching may increase. In particular, in a semiconductor device in which many internal transistors operate simultaneously and at high speed and many signal terminals are simultaneously turned on and off, such as a multi-bit large-capacity DRAM, a conventional lead frame is used. Therefore, it is difficult to reduce noise due to crosstalk, switching, and the like.

In a semiconductor device handling a high-frequency signal, a lead connected to a power supply or a ground has a voltage variation due to a self-inductance of a lead connected to another signal or a mutual inductance between a power supply and a ground lead. Therefore, there is a possibility that a potential difference may occur between the ground in the semiconductor chip and the ground of the external device, or between the power supply voltage in the semiconductor chip and the power supply voltage of the external device. Therefore, a multi-bit large-capacity DRAM
In a semiconductor device in which many transistors operate at the same time and at high speed and many signals flow simultaneously through each wiring, the power supply potential and the ground potential fluctuate with time, resulting in deterioration of the signal waveform. Or the element may malfunction.

Furthermore, in a semiconductor device that handles high-frequency signals, it has been practically impossible to match the impedance with a lead frame.

As another problem, in a conventional semiconductor device, a large-capacity pass capacitor must be mounted between a power supply wiring and a ground wiring in order to remove power supply noise. Has been a major obstacle to downsizing.

The present invention has been made in view of the above point, and a first object of the present invention is to interpose a wiring body having a wiring and an insulating support base for supporting the wiring between a lead and a semiconductor chip. Accordingly, it is an object of the present invention to provide a semiconductor device capable of high-speed operation without noise to a high-frequency signal or a change in ground or power supply potential.

A second object of the present invention is to provide a wiring body having a high function of removing power supply noise in a circuit in which a high-frequency semiconductor device is arranged.

[0015]

According to a first aspect of the present invention, there is provided a semiconductor device having a first surface and a second surface and having a plurality of bonding pads on the first surface. The semiconductor chip comprises: a plate-shaped insulating support base having an opening smaller than the first surface; and a plurality of wirings supported by the insulating support base, one end of which is disposed around the opening. A thin metal wire made of at least one of a thin metal wire and a thin metal film for electrically connecting the wiring body provided on the first surface and each of the bonding pads of the semiconductor chip to the one end of each of the wirings; And a connection member made of at least one of a metal thin film and a plurality of leads connected to other portions of each wiring of the wiring body.

Thus, a semiconductor device having a new concept of a board-on-chip instead of the conventional chip-on-board can be obtained. For example, in a conventional resin-encapsulated semiconductor device, the inner leads in the resin-encapsulation process come close to or come into contact with each other due to the flow of the resin, causing problems such as short-circuiting of electric signals and crosstalk. There is a risk. On the other hand, in the present invention, the wiring body is present in place of the inner lead, so that even in the resin sealing step of forming the resin-sealed semiconductor device, the entire wiring body is formed by the flow of the sealing resin. The distance between the wirings is kept constant, though it may move slightly. Moreover, even if the wiring in the wiring body is made thinner, there is no problem in terms of strength, so that it is possible to always secure a necessary interval between the wirings. Further, even if the semiconductor device is not a resin-sealed semiconductor device, the wires in the wiring body do not come close to each other during use. Furthermore, since the wiring body exists between the semiconductor chip and the lead, and one end of the wiring is located near the opening of the insulating support base, the length of the lead itself in the conventional semiconductor device is extremely reduced. Can be. Therefore, even in a semiconductor device that handles high-frequency signals, reduction of inductance, prevention of crosstalk, and the like can be easily realized.

In the case where the wiring is a power supply wiring or a grounding wiring through which a large current flows, by increasing the width of these wirings, a voltage drop due to self-inductance can be suppressed. It is also possible to prevent the potential and the ground potential from fluctuating.

Further, by providing the insulating support base in this manner, the width, interval, and shape of the wiring can be freely designed, and it is possible to have an impedance matching function.

In the first semiconductor device, the plurality of wirings include a signal wiring, a power supply wiring, and a grounding wiring, and the plurality of leads include a signal lead, a power supply lead, and a grounding lead. And the signal wiring and the signal lead, the power supply wiring and the power supply lead, and the grounding wiring and the grounding lead are electrically connected. preferable.

As a result, the above-described effects can be obtained for various wirings required for the semiconductor device.

In the first semiconductor device, the power supply wiring and the ground wiring may be formed on at least one of the first surface and the second surface of the insulating support base.
It can be formed so as to have regions facing each other with a small gap therebetween.

As a result, a large capacitance component is formed between the power supply wiring and the grounding wiring, so that power supply noise can be reduced without disposing a pass capacitor or the like occupying a large area in any part of the semiconductor device. Can be removed.

In the first semiconductor device, it is preferable that a bonding pad of the semiconductor chip is formed so as to be located in the opening.

Thus, the bonding pads can be freely arranged in the semiconductor chip, and the wiring pattern in the wiring body can be freely drawn, so that various structures can be adopted according to the type of the semiconductor device.

According to a second semiconductor device of the present invention, there is provided a semiconductor chip having a first surface and a second surface and having a plurality of bonding pads on the first surface; a plate-shaped insulating support base; A plurality of wirings supported by the base,
A wiring member provided on the first surface of the semiconductor chip, and a connection member comprising a bump for electrically connecting each bonding pad of the semiconductor chip and a part of each of the wirings;
And a plurality of leads connected to other portions of each wiring of the wiring body.

Thus, the same effect as in the first semiconductor device can be obtained for a semiconductor device in which a semiconductor chip is flip-chip connected on a wiring body.

In the second semiconductor device, the insulating support base in the wiring body has an opening smaller than the first surface of the semiconductor chip, and a plurality of wirings in the wiring body are formed around the opening. It is preferable that the bump has a structure in which the bump is connected to one end of the wiring body and a bonding pad of the semiconductor chip.

In the second semiconductor device, the plurality of wirings include a signal wiring, a power supply wiring, and a grounding wiring, and the plurality of leads include a signal lead, a power supply lead, and a grounding lead. A structure in which the signal wiring and the signal lead, the power supply wiring and the power supply lead, and the ground wiring and the ground lead are electrically connected. Is preferred.

In the first or second semiconductor device,
The insulating support base is made of at least one of glass epoxy, polyimide, polyester, benzocyclobutene resin, BT resin and polyimide amide ether.
It can be composed of one or more organic materials.

Thus, since the wiring body is supported by the flexible insulating support base, handling in the manufacturing process of the wiring body and the semiconductor device is facilitated.

In the first or second semiconductor device,
The insulating support base may be made of an inorganic material containing at least one of alumina, silicon nitride, aluminum nitride, silicon carbide, beryllium oxide, silicon, an insulating film-forming metal, and high-purity glass.

Thus, since the insulating support base is made of a material having a high melting point, the bonding between the lead and the wiring can be performed using a process performed under a high temperature condition such as brazing, and the reliability of the connection portion can be improved. The performance is improved.

In the first or second semiconductor device,
It is preferable that the wiring be formed by printing a conductive film on an insulating support base.

Thus, it becomes possible to make each wiring in the wiring thin, to change the shape of each wiring in various ways, and to reduce the manufacturing cost.

In the first or second semiconductor device,
A semiconductor device is further provided by assembling a wiring body and a lead frame, further comprising a wiring body wiring body fixing support for supporting the wiring body on one of the first surface and the second surface of the wiring body. Since it is easy to fix the wiring body at the time of formation, the connection state between the wiring body and the lead becomes more reliable.

In this case, the wiring body fixing support may function as at least one of a power supply lead and a grounding lead.

In the first or second semiconductor device,
The semiconductor chip, the wiring body, the connection member,
The semiconductor device may further include a sealing resin for sealing a portion of the lead on the wiring body side.

As a result, even in an inexpensive resin-encapsulated semiconductor device, the proximity and contact between wirings in the resin encapsulation process are prevented, thereby preventing crosstalk and reducing inductance.

In the first or second semiconductor device,
By further providing a ferroelectric chip provided over the ground wiring and the power supply wiring, a semiconductor device having a high power supply noise removing function can be obtained.

In the first or second semiconductor device,
A semiconductor device having a high power supply noise removing function can be obtained by further including a chip capacitor provided over the ground wiring and the power supply wiring.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor device according to each of the following embodiments basically has a three-dimensional structure shown in FIG. That is, a semiconductor chip (not shown) is built in a package sealed with the sealing resin 500,
A large number of signal leads 301, power supply leads 302, and grounding leads 303 project from both side surfaces of the reference numeral 00. However, depending on the type of the semiconductor device, the power supply lead 302 and the grounding lead 303 protrude from the end face side of the sealing resin as shown by the broken line in FIG. In addition,
Although the members in the sealing resin are not shown in FIG. 33, in the drawings relating to the following embodiments and modifications,
The sealing resin 500 is shown as transparent, and the members arranged in the sealing resin 500 are shown.

(First Embodiment) First, a first embodiment will be described with reference to FIGS. 1 (a) to 1 (d), 2 (a) and 2 (b).
This will be described with reference to FIGS. 3 (a) to 3 (c) and FIG.

FIGS. 1A to 1D are views showing the structure of a semiconductor device according to the first embodiment. FIG. 1A is a plan view of a semiconductor chip or the like viewed from a second surface side. FIG. 1 (b)
1 is a sectional view taken along the line Ib-Ib shown in FIG.
1C is a plan view of the semiconductor chip and the like as viewed from the first surface side, and FIG. 1D is a cross-sectional view taken along the line Id-Id shown in FIG.

As shown in FIGS. 1A to 1D, in a semiconductor device, a semiconductor chip 100 containing elements such as transistors, and elements and the like inside the semiconductor chip 100 and external members are electrically connected. Lead frame 300A for connection
And a wiring body 200A having wiring for electrically connecting the lead frame 300A to elements and the like in the semiconductor chip 100, and a wiring in the wiring body 200A and the semiconductor chip 1
1st thin metal wire 4 for connecting to a bonding pad
01, the lead in the lead frame 300A and the wiring body 2
It is composed of a second thin metal wire 402 connecting the wires in 00A and a sealing resin 500 sealing these members.

As shown in FIGS. 1A and 1C, the tips of the leads of the lead frame 300A are arranged along the outer contour of the wiring body 200A, and these leads are connected to the wiring body 200A. A power lead 302 and a ground lead 303 extending from two short sides of the wiring body 200A to portions located on the second surface 220 of the wiring body 200A, respectively. Are roughly divided into

As shown in FIGS. 1 (b), 1 (c) and 1 (d), a signal bonding pad (member indicated by reference numeral 101 shown in FIG. 3 (b)) of the semiconductor chip 100 and the wiring body 200A The power supply bonding pad of the semiconductor chip 100 (FIG. 3)
(A member denoted by reference numeral 102 shown in FIG. 2B) and the wiring body 20
Between the pad portion of the power supply wiring 202 of 0A and the bonding pad for grounding of the semiconductor chip 100 (member indicated by reference numeral 103 in FIG. 3B) and the pad portion of the grounding wiring 203 of the wiring body 200A. The spaces are connected by the first thin metal wires 401. Further, the signal lead 301 and a pad portion formed at an outer end of each wiring on the wiring body 200A are connected by a second thin metal wire 402. Further, the power supply lead 302 and the grounding lead 303 are connected to the power supply wiring 212 and the grounding wiring 213 on the second surface 220 of the wiring body 200A by soldering, respectively, to fix and support the wiring body 200A. It also plays a role.

Next, the detailed structure of the wiring body 200A and the laminated state of the wiring body 200A and the semiconductor chip 100 will be described.

FIGS. 2A and 2B show the wiring 2
FIG. 9 is a plan view of the insulating support base 205 of 00A viewed from the first surface 210 side and the second surface 220 side. The wiring body 200A includes wiring and an insulating support base 205 for supporting the wiring. The insulating support base 205 has a rectangular opening 206 at the center and is formed so that the outer side is substantially rectangular. Then, as shown in FIG. 2A, on the first surface 210 of the insulating support base 205, a large number of wirings extending from the vicinity of the outer side to the vicinity of the opening 206, that is, a linear signal wiring 201, and a strip-shaped wiring are provided. A power supply wiring 202, a strip-like grounding wiring 203, and the like are formed by printing, and both ends of each of the wirings 201, 202, and 203 are pad portions for wire bonding. Also, the second
On the surface 220, a wide power supply wiring 212 and a grounding wiring 213 occupying almost half of the area on the surface are formed. The power supply wiring 212 and the grounding wiring 213 on the second surface 220 side are electrically connected to the power supply wiring 202 and the grounding wiring 203 on the first surface 210 via conductive members formed in the through holes 215, respectively. Connected. However, in this embodiment and each of the following embodiments, the conductive member may be embedded in the entire through-hole 215 or may cover the inner wall surface of the through-hole 215.

FIGS. 3A to 3C show the semiconductor chip 10.
FIG. 5 is a perspective view showing a structure when bonding a wiring body 0 and a wiring body 200A. FIG. 3A shows the wiring body 200 already described.
It is a perspective view of A. FIG. 3B shows the semiconductor chip 100.
It is a perspective view of. As shown in FIG. 1B, the wiring body 200A in the region on the first surface 110 of the semiconductor chip 100 is formed.
A large number of bonding pads arranged along the edge of the opening 206 are formed in a region included in the opening 206. This bonding pad is a signal bonding pad 101 connected to a transistor in a semiconductor chip.
A power bonding pad 102 connected to a power terminal in the semiconductor chip 100; and a ground bonding pad 10 connected to a ground terminal in the semiconductor chip 100.
It is roughly divided into three. Then, as shown in FIG.
By laminating the first surface 110 of the semiconductor chip 100 and the second surface 220 of the wiring body 200A, a laminate is formed.

FIG. 4 is a plan view of a lead frame 300A used in the present embodiment. Although FIG. 4 shows only two chip mounting areas, it is continuous in the vertical direction in FIG. Many chip mounting areas may be formed in the device.

Then, the bonding pads 101 to 103 of the semiconductor chip 100 and each wiring 20 of the wiring body 200A are formed.
After connecting the first and second fine metal wires 401 and 402 to the pads of Nos. 1 to 203 and the leads of the lead frame 300A shown in FIG. By sealing with the stopper resin 500, the semiconductor device shown in FIGS. 1A to 1D is obtained.
However, in FIG. 1A and FIG. 1C, the wiring of the wiring body 200A is omitted for easy viewing. FIGS. 1 to 3 and 4 are views for explaining the embodiment in an easy-to-understand manner. In an actual example, an extremely large number of wirings are formed in a complicated pattern. Therefore, even if the number of fine metal wires shown in FIGS. 1A and 1C, the number of wires shown in FIGS. 2A and 2B, and the number of leads shown in FIG. Are formed as many as the required number of signal terminals.

The power supply lead 302 and the power supply wiring 2
12, the ground lead 303 and the ground wire 21
In the case where the second metal thin wire 402 is connected to the third metal wire 402, an insulating adhesive is used for fixing and supporting the wiring body 200A.

However, in this embodiment and each of the embodiments described later, instead of soldering, brazing using a high melting point metal brazing is performed, or the leads and pads are replaced with Au.
And Au, Au and Sn, Au and Ag, and Ag and Pd, etc., which are made of a combination of metals that can be electrically welded. A current is applied between the lead and the pad to connect them by Joule heat. For example, there are methods such as spot welding), welding such as laser welding, and joining using a conductive adhesive, and any method may be used. Further, a thin metal plate may be used instead of the thin metal wire.

A feature of the semiconductor device of the present invention is that the semiconductor device is provided with a wiring body 200 described in the present embodiment and each embodiment described later. And the semiconductor device of the present invention is:
With the above configuration, the following effects can be exerted. That is, when a printed wiring is formed on the insulating support base 205 of such a wiring body 200, a thin wiring having various patterns can be formed.
That is, since the wiring is formed on the plate-like insulating support base 205, even if the entire wiring body 200 moves at the time of resin sealing, each wiring does not individually move like a lead in a lead frame. Because there is no. Further, since the wiring can be made thin, a sufficiently large interval between the wirings can be ensured. The effect of reducing the thickness of the wiring and increasing the wiring interval will be described.

The self-inductance L of each wiring is represented by the following equation (2).

L = (μo y / 2π) [ln {2y / (a + b)} + (1/2)] (2) where μo is the vacuum permeability, y is the length of the conductor, and a is the width of the conductor. , B is the thickness of the conductor.

The mutual inductance LM of the wiring is
It is represented by the following equation (3).

LM = (μo / 2π) [yln {(y + (y ² + d ² ) ^1/2 / d} − (y ² + d ² ) ^1/2 + d] (3) where d is the distance between wirings When the current i flows through the adjacent wiring, a voltage drop corresponding to -LM (di / dt) occurs, which causes crosstalk.

According to the above equation (2), when the width a of the wiring is reduced, the self-inductance L is increased. However, when the thickness b of the wiring is increased, the increase in the self-inductance L can be suppressed. Unlike a lead frame whose thickness is determined by a standard, when a wiring is formed by printing, the width and thickness can be freely set, so that there is no problem even if the width is reduced. From equation (3), it can be seen that the mutual inductance LM decreases as the wiring distance d increases. Therefore, the wiring body 200A of the present embodiment
It can be understood that the crosstalk can be prevented by the structure of FIG.

In addition, since the wiring on the insulating support base 205 can have a complicated shape that cannot be formed by a lead frame, the impedance can be adjusted very easily.

Therefore, by interposing such a wiring body 200 between the semiconductor chip and the lead, or by arranging the wiring body 200 in a signal transmission section of a circuit that handles a high-frequency signal, high-speed operation and resistance to high-frequency signals can be achieved. A semiconductor device having excellent noise characteristics can be configured. These effects are the basic effects of the present invention.

In particular, in the semiconductor device according to the first embodiment, the power supply lead 302 and the grounding lead 303 are connected to the power supply wiring 212 and the grounding wiring 21 on the wiring body 200A.
3 is directly connected without a thin metal wire, so that the inductance can be suppressed to an extremely small value. Therefore, even in a semiconductor device having a built-in transistor that operates at high speed, fluctuation of the ground potential can be suppressed. Deterioration and malfunction of the signal waveform can be reliably prevented.

FIGS. 34 (a) to 34 (c) are diagrams showing the results of experiments performed to compare the difference in ground noise between the conventional high-frequency semiconductor device and the high-frequency semiconductor device of the present embodiment. FIG. 34 (a) shows the waveform of the signal voltage applied for measurement, and FIGS. 34 (b) and (c)
It is the data which shows the ground noise at the time of performing simultaneous switching of eight lines in the conventional product and the product of the present invention. 34 (b) and 34 (c), it can be easily understood that ground noise is significantly reduced by the product of the present invention.

The power supply wiring 202 on the first surface 210
And the ground wiring 203, and between the power supply wiring 212 and the ground wiring 213 on the second surface 220 are formed so as to have extremely narrow intervals. Here, the capacitance C of the parallel plate type capacitor formed by two sufficiently long conductor films opposed to each other with a distance d across the insulating material is expressed by the following equation (4).

C = (ε / d) · y · b = (ε / d) · S (4) where ε is the dielectric constant of the intervening dielectric substance, and S is the area of the opposing regions of the two conductor films. Area. That is, the smaller the gap between the two conductor films, the larger the capacitance C. The capacitance C can be adjusted by adjusting the area S, that is, the opposing regions (see the structure of FIG. 20 regarding a modified embodiment described later). Therefore, the power supply noise can be reliably removed without providing a pass capacitor conventionally provided between the power supply wiring and the grounding wiring, thereby improving the performance of the semiconductor device and reducing the size of the semiconductor device. Can be achieved. Further, the proportion of the power supply wiring 212 and the grounding wiring 213 on the second surface 220 does not necessarily have to be the same, and one of them may be larger than the other.

The number and size of the through holes 215
It has been found that the noise can be adjusted to an extremely low level by adjusting the position and the like.

Note that this embodiment and each of the following embodiments,
In a modification, the insulating support base 205 constituting the wiring body 200 can be made of an organic material such as glass epoxy, polyimide, polyester, benzocyclobutene (BCB), BT resin, and polyimide amide ether. By supporting the wiring with such a flexible wiring body, handling in a manufacturing process or the like becomes easy. Further, the insulating support base 205 can be made of a ceramic such as alumina, silicon nitride, aluminum nitride, silicon carbide, beryllium oxide, a silicon substrate, an insulating film-forming metal called so-called enamel, high-purity glass, or the like. In this case, since the melting point is higher than that of the organic material, it is easy to perform brazing when connecting the lead and the wiring, and the reliability of the connection portion can be improved.

Further, the present embodiment and each of the following embodiments,
In a modified embodiment, the semiconductor chip 100 and the wiring body 200
Examples of the adhesive for fixing the resin include a thermosetting resin such as epoxy and polyimide, a thermoplastic resin such as PPS and polyamideimide, and an ultraviolet curable resin, and any of them may be used. In addition, quartz,
Fine particles such as hard glass, ceramic, and high-melting point metal having an insulating oxide film on the surface can be filled.

Further, in the present embodiment and each of the following embodiments and modifications, each wiring in the wiring body is formed by a method of printing a conductive material, a method of forming a metal film by CVD or plating, and then a patterning method. And any method may be used. Note that each wiring does not necessarily have to be formed on the surface of the insulating support base, and may have a structure in which part or most of the wiring is embedded in the insulating support base.

(Second Embodiment) Next, a semiconductor device according to a second embodiment will be described with reference to FIGS. 5 (a) to 5 (d) and FIG. FIGS. 5A to 5D are views showing the structure of the semiconductor device according to the second embodiment. FIG. 5A is a plan view of the semiconductor chip viewed from the second surface side. 5B is a cross-sectional view taken along line Vb-Vb shown in FIG. 5A, FIG. 5C is a plan view of the semiconductor chip viewed from the first surface side, and FIG. 5D is FIG. It is sectional drawing in the Vd-Vd line | wire shown.

As shown in FIGS. 5A to 5D, the basic structure of the semiconductor device according to the present embodiment is almost the same as that of the semiconductor device according to the first embodiment, and is the same as that of the first embodiment. The wiring body 200A is used. The features of this embodiment are as follows.
As shown in FIG. 6, the insulating support base 20 is attached to the lead frame.
5, a pair of strip-shaped wiring body fixing bars 352 extending from both short sides to the long side end of the insulating support base 205.
353 are provided, and the wiring body fixing bar 35 is provided.
2, 353 are connected to the power supply wiring 212 and the grounding wiring 213 on the second surface 220 of the wiring body 200A, respectively. Here, the wiring body fixing bars 352, 353, the power supply wiring 212, and the grounding wiring 213 are generally connected by soldering, brazing, welding, or a conductive adhesive. However, both may be fixed with an insulating adhesive.

FIG. 6 is a view showing the structure of a lead frame 300B used in this embodiment. As shown in the figure, the wiring body fixing bars 352 and 353 are configured to connect between both rails of the lead frame 300B.
However, in FIG. 6, the wiring body fixing bars 352, 3
Although the shape of 53 is simplified and displayed, it is actually the shape shown in FIG.

Here, the power supply lead 302 and the ground lead 303 are disposed at the outermost positions adjacent to the signal leads 301 arranged in parallel with each other along the two long sides of the wiring body 200A. Is common. However, the position and the number are not limited to this embodiment. That is, it may be arranged at a position other than the outermost position, or may be provided in a larger number. In the present embodiment, each pair of the power supply lead 302 and the grounding lead 303 is connected to the pad portion of the power supply wiring 202 and the grounding wiring 203 on the first surface 210 of the wiring body 200A by the second thin metal wire 402. I have.

In this embodiment, the method of laminating the semiconductor chip 100 and the wiring body 200A is as shown in FIGS. 3A to 3C in the first embodiment.

According to the present embodiment, similarly to the first embodiment, while using the wiring body 200A shown in FIG. 2A, it is provided with high noise resistance and high-speed operation function and high impedance matching. A semiconductor device having a function can be obtained.

Moreover, one continuous strip-shaped wire fixing bar 35 extending to both ends across the wiring body 200A.
Since the 2,353 are provided, the support of the wiring body 200A at the time of assembling the semiconductor device becomes more stable and strong, and the manufacturing can be facilitated. further,
In the present embodiment, all the lead terminals after resin sealing have a so-called DIP structure protruding from two long sides of the semiconductor device (the wiring fixing bars 352 and 353 are located near the surface of the sealing resin 500). This has the advantage that the automatic assembly process such as mounting on a printed circuit board can be performed extremely smoothly.

However, the wiring fixing bars 352 and 353 can be used as power supply leads and grounding leads, and the original power supply leads 302 and grounding leads 303 can be used as sub power supply leads and sub grounding leads. is there. In this case, a structure is adopted in which the three lines of the front and back wiring and the lead are arranged in parallel. Therefore, the resistance component of the impedance can be particularly reduced. Further, since the inductance is also reduced, there is an advantage that the fluctuation of the ground potential or the power supply potential can be more reliably prevented. Further, the connection of the wiring body 200A to the power supply wiring 212 and the grounding wiring 213 becomes more stable and strong, and the fluctuation of the ground potential and the power supply potential can be more reliably prevented.

(Third Embodiment) Next, a third embodiment will be described with reference to FIGS. 7 (a) to 7 (d) and FIG. FIGS. 7A to 7D are views showing the structure of the semiconductor device according to the third embodiment. FIG. 7A is a plan view of the semiconductor chip viewed from the second surface side, and FIG. 7B is a sectional view taken along the line VIIb-VIIb shown in FIG.
FIG. 7C is a plan view of the semiconductor chip viewed from the first surface side, and FIG.
FIG. 8D is a cross-sectional view taken along the line VIId-VIId shown in FIG.

As shown in FIGS. 7A to 7D, the basic structure of the semiconductor device according to the present embodiment is almost the same as the structure of the semiconductor device according to the second embodiment. In the lead frame 300C according to the present embodiment, each pair of the power lead 302 and the ground lead 303
The feature is that it is integrated with the wiring body fixing bar in the second embodiment.

FIG. 8 is a view showing the structure of a lead frame 300C used in this embodiment. As shown in the drawing, the power supply lead 302 and the grounding lead 303 are not connected between both rails of the lead frame 300C, but are connected between outer frames connecting both rails. However, in FIG. 8, the shapes of the power lead 302 and the ground lead 303 are shown in a simplified manner.
Actually, the shape is as shown in FIG.

That is, the power supply lead 302 and the ground lead 303 in the present embodiment are the same as the wiring body fixing bar 3 in the structure of the semiconductor device according to the second embodiment.
Similarly to 52 and 353, it also has a function of supporting the wiring body 200A when assembling the wiring body 200A and the lead frame 300C. Then, in the lead frame 300C according to the present embodiment, unlike the first embodiment,
The power leads 302 and the ground leads 303 are not extended straight out of the short side of the insulating support base 205, but are bent in a right angle direction and are arranged in parallel with the signal leads 301 described below. That is, the semiconductor device of the present embodiment has a structure in which all the leads 301 to 303 protrude from both side surfaces on the long side in the state shown in FIG.

In this embodiment, the method for laminating the semiconductor chip 100 and the wiring body 200A is as shown in FIGS. 3A to 3C in the first embodiment.

In the present embodiment, similarly to the first embodiment, while using the wiring body 200A shown in FIG. 2A, it is provided with high noise resistance and high-speed operation function and high impedance matching function. Can be obtained.

In addition, since the power supply lead 302 and the grounding lead 303 are formed in one continuous band extending to both ends across the wiring body 200A, three lines of the front and back wiring and the lead are formed. The structure is arranged in parallel. Therefore, the resistance component of the impedance can be particularly reduced. Further, since the inductance is also reduced, there is an advantage that the fluctuation of the ground potential or the power supply potential can be more reliably prevented. Furthermore, in the second embodiment, the power supply lead 302 and the ground lead 303 are formed continuously so as to connect the rails of the lead frame 300B, and have a function of fixing the wiring body. Since it also has the same fixing function, the connection between the lead frame 300C and the power supply wiring 212 and the grounding wiring 213 of the wiring body 200A becomes more stable and strong.
Variations in the ground potential and the power supply potential can be more reliably prevented. Further, in the present embodiment, since all signal terminals have a so-called DIP structure protruding from two long sides of the semiconductor device, there is an advantage that an automatic assembly process such as attachment to a printed circuit board can be performed extremely smoothly. .

The lead frame used in the present embodiment is not limited to the one having the structure shown in FIG. FIG. 9 is a plan view of a lead frame 300D according to a modification of the present embodiment. In the modified lead frame 300D, the power lead 302 and the ground lead 303 are also connected to each rail of the lead frame 300D. Then, after sealing with the sealing resin, the power supply lead 302 and the ground lead 303 are separated from the respective rails of the lead frame 300D. By adopting such a structure, the strength of the power supply lead 302 and the grounding lead 303 before assembling is increased, so that there is an advantage that deformation of the lead frame 300D during assembling can be suppressed.

(Fourth Embodiment) Next, a fourth embodiment will be described with reference to FIGS. 10 (a) to 10 (d), FIGS.
This will be described with reference to FIG.

FIGS. 10A to 10D are views showing the structure of a semiconductor device according to the fourth embodiment.
10A is a plan view of a semiconductor chip or the like viewed from the second surface side, FIG. 10B is a cross-sectional view taken along line Xb-Xb shown in FIG. 10A, and FIG. FIG. 10D is a plan view seen from one surface side, and FIG. 10D is a cross-sectional view taken along line Xd-Xd shown in FIG.

As shown in FIGS. 10A to 10D, the basic structure of the semiconductor device according to this embodiment is the same as that shown in FIG.
This is the same as the structure of the semiconductor device according to the first to third embodiments shown in (a) to (d) and the like. However, in the present embodiment, although the first thin metal wire 401 connecting the wiring in the wiring body 200B and the bonding pad of the semiconductor chip 100 is formed, the lead in the lead frame 300E and the wiring in the wiring body 200B are not formed. Are not provided.

FIGS. 11A and 11B are plan views of the insulating support base 205 in the wiring body 200B as viewed from the first surface 210 side and the second surface 220 side, respectively. As shown in FIG. 11A, on the first surface 210 of the insulating support base 205 in the wiring body 200B, a large number of wirings extending from near the outer end to near the opening 206, that is, linear signal Wiring 20
1, strip-shaped power supply wiring 202, strip-shaped grounding wiring 203
Etc. are formed by printing. This structure is the same as the structure of the wiring body 200A according to the first to third embodiments. However, in the wiring body 200B according to the present embodiment, as shown in FIG.
The pad portions 202 and 203 are not provided on the first surface 210. Then, the second of the insulating support base 205 is
A signal wiring pad 221, a power supply wiring pad 222, and a ground wiring pad 223 are formed on the surface 220. The signal wiring pad portion 221 is formed on the first surface 21 via a conductive material formed in a through hole.
It is electrically connected to the end of the signal wiring 201 on the zero. On the other hand, the power supply wiring pad 222 and the grounding wiring pad 223 are connected to the power supply wiring 212 and the grounding wiring 213 on the second surface 220, respectively. However, the power supply wiring 212 on the second surface 220 side and the grounding wiring 2
Reference numeral 13 is electrically connected to the power supply wiring 202 and the grounding wiring 203 on the first surface 210 side via conductive members formed in the through holes 215, respectively.

FIG. 12 is a plan view showing the structure of a lead frame 300E used in this embodiment.

In the present embodiment, the semiconductor chip 10
0 and the wiring body 200B are laminated as shown in FIG.
This is basically the same as the first embodiment shown in FIGS. That is, the first surface 1 of the semiconductor chip 100
By laminating 10 and the second surface 220 of the wiring body 200B, a laminate is formed.

Then, the lead frame 30 shown in FIG.
In a state where 0E is in contact with the second surface 220 of the wiring body 200B, each lead is connected to the pad portion of the wiring body 200B by soldering, brazing, welding, a conductive adhesive, or the like. Then, as shown in FIGS. 10B to 10D, between the signal bonding pad 101 of the semiconductor chip 100 and the pad portion of the signal wiring 201 of the wiring body 200B, the power bonding pad 102 of the semiconductor chip 100 is formed. And the pad portion of the power supply wiring 202 of the wiring body 200B,
Ground bonding pad 103 of semiconductor chip 100
The first metal fine wire 401 connects between the first metal thin wire 401 and the pad portion of the ground wire 203 of the wiring body 200B.

Further, the semiconductor chip 100 and the wiring body 20
After embedding the end portions (inner leads) of the leads of the lead frame 300B and the lead frame 300E in the sealing resin, the dam bar and the outer leads of the lead frame 300E are cut to obtain the structure of the semiconductor device shown in FIG. .

In the present embodiment, the wiring body 200B and the lead are connected by soldering, brazing, welding, a conductive adhesive or the like instead of the second metal fine wire. It is possible to further reduce the inductance at the connection part of the wiring for use.

(Modifications Regarding Wiring Body) In the above embodiments, the embodiments relating to the overall structure of the semiconductor device have been described. Here, various modifications of the embodiment of the wiring body will be described.

(1) First Modification FIGS. 13A and 13B are views from the first surface 210 and the second surface 220 of the insulating support base 205 in the wiring body 200C according to the first modification. FIG. The structure of the wiring body 200C in the present modified example is different from the structure of the wiring body 200A in the first to third embodiments (see FIG. 2) by the first structure.
The structure on the surface 210 is the same, but the second surface 220
The structure above is different. That is, the power supply wiring is not formed on the second surface 220 of the wiring body 200 </ b> C according to the present modification, and the grounding wiring 213 is formed in a substantially entire area on the second surface 220. Therefore, when using the wiring body 200C according to the present modification, the first
In the state shown in FIGS. 1A to 1D in the embodiment, the power supply lead 302 of the lead frame 300 is connected to the power supply wiring 202 on the first surface 210 of the wiring body 200C, and the grounding lead 303 is connected to the wiring. The body 200C is connected to the ground wiring 213 on the second surface 220 side of the insulating support base 205.

According to the structure of the wiring body 200C according to this modification, there is an advantage that the fluctuation of the ground potential which adversely affects the operation of the element can be surely prevented.

(2) Second Modification FIGS. 14A and 14B are views from the first surface 210 and the second surface 220 of the insulating support base 205 in the wiring body 200D according to the second modification. FIG. The structure of the wiring body 200D according to the present modification is different from the structure of the wiring body 200B according to the fourth embodiment (see FIG. 11) on the first surface 2D.
Although the structure on 10 is the same, the structure on the second surface 220 is different. That is, the power supply wiring is not formed on the second surface 220 of the wiring body 200 </ b> D according to the present modification, and the grounding wiring 213 is formed over a substantially entire area on the second surface 220. However, also in this modification, the pad portions 221, 222, and 223 of the respective wirings for making electrical connection with the leads are all formed on the second surface 220.
D is also used, as shown in FIGS. 10A to 10D in the fourth embodiment, as shown in FIG.
0 leads 301, 302, 303 to the wiring body 200D.
Pad portions 221, 222, 223 on the second surface 220
It can be connected by soldering, brazing, welding, conductive adhesive or the like.

According to the structure of the wiring body 200D according to this modification, similarly to the above-described first modification, it is possible to reliably prevent the fluctuation of the ground potential, which adversely affects the operation of the element, and to ensure that the lead and each wiring There is an advantage that the inductance of the connecting portion between them can be reduced.

(3) Third Modification FIGS. 15A and 15B are views from the first surface 210 and the second surface 220 of the insulating support base 205 in the wiring body 200E according to the third modification. FIG. The structure of the wiring body 200E in the present modification is different from the structure of the wiring body 200A in the first to third embodiments (see FIG. 2) by the first structure.
The structure on the surface 210 is the same, but the second surface 220
The structure above is different. That is, neither the power supply wiring nor the grounding wiring is formed on the second surface 220 of the wiring body 200E according to the present modification, and both are formed only on the first surface 210. Therefore, when the wiring body 200E according to the present modification is used, in the state shown in FIGS. 1A to 1D in the first embodiment, the power lead 302 and the ground lead 303 of the lead frame 300 are provided.
Are connected to the power supply wiring 202 and the grounding wiring 203 on the first surface 210 of the wiring body 200E.

According to the structure of the wiring body 200E according to this modification, since no conductor film is formed on the second surface 220 side, it is possible to surely prevent the deformation of the laminate of the semiconductor chip 100 and the wiring body 200E. Can be. That is, the second
A structure in which a conductor film is solid-coated on the surface side (that is, the wiring bodies 200A to 200D according to each of the above-described embodiments or modifications).
In the case of the above, 20
When held at a high temperature of about 0 ° C., the conductor film on the second surface and the insulating support base 205 are joined together in a stretched state due to the difference in the coefficient of thermal expansion between the two. When the semiconductor chip is returned, the semiconductor chip is deformed by the stress of the wiring body to be shrunk, so that it is necessary to take measures to prevent the joint between the two from coming off. On the other hand, in the present modification, since no conductor film is formed on the second surface 220 of the wiring body 200E, such deformation can be suppressed. In addition, this eliminates the need for measures to prevent the two from being separated from each other.

(4) Fourth Modified Embodiment FIGS. 16A and 16B are views from the first surface 210 and the second surface 220 of the insulating support base 205 in the wiring body 200F according to the fourth modified embodiment. FIG. The structure of the wiring body 200F according to the present modification is different from the structure of the wiring body 200B according to the fourth embodiment (see FIG. 11) on the first surface 2F.
Although the structure on 10 is the same, the structure on the second surface 220 is different. That is, neither the power supply wiring nor the grounding wiring is formed on the second surface 220 of the wiring body 200F according to the present modified embodiment, and both are formed only on the first surface 210. However, also in this modification, the pad portion 22 of each wiring for making an electrical connection with the lead is provided.
Since the wirings 1, 222, and 223 are all formed on the second surface 220, even when the wiring body 200F according to the present modified example is used, FIGS.
As shown in (d), each lead 301, 302, 303 of the lead frame 300 is connected to the second surface 22 of the wiring body 200F.
It is sufficient to connect to the respective pad portions 221, 222, 223 on the soldering plate by soldering, brazing, welding, conductive adhesive or the like.

According to the structure of the wiring body 200F according to this modification, the wiring body 200F is similar to the third modification.
Since the conductive film is not formed on the second surface 220 of F,
Such deformation can be suppressed, and there is an advantage that a measure for preventing the two from being separated from each other becomes unnecessary. In addition, since pad portions 221, 222, and 223 for connection to all the wiring leads are formed on the second surface 220 of the wiring body 200F, the fourth embodiment shown in FIG. Similarly, the leads can be easily connected to the pads 221, 222, and 223 by soldering, brazing, welding, a conductive adhesive, or the like, and the inductance can be reduced.

(5) Fifth Modification FIGS. 17A to 17C show a first surface 210, a second surface 220, and a third surface 23 of a wiring body 200G according to a fifth modification.
0 is a plan view showing the structure at 0. FIG. Each of the wiring bodies 200A to 200F according to each of the above-described embodiments and modified examples has wirings formed on two surfaces of one substrate 205. However, the wiring body 200G according to the modified example has two wirings. It is configured by laminating substrates 207 and 208. And
On the first surface 210, which is the upper surface of the upper substrate 207, a signal wiring 201, a power supply wiring 202, a ground wiring 203, and the like are formed, and pad portions are provided at both ends of each wiring. Also, the lower surface of the upper substrate 207 or the lower substrate 20
8 is formed on the second surface 220, which is the upper surface of the substrate 8, and the ground wiring 213 connected to the ground wiring 203 on the first surface 210 is formed on the third surface 230, which is the lower surface of the lower substrate 208. The power supply wiring 212 connected to the power supply wiring 202 on the first surface 210 is formed. In other words, the present modification is a wiring body 2 according to a third modification shown in FIG.
This is equivalent to one obtained by adding one substrate having power supply wiring 212 to 00C.

According to the wiring body 200G according to the present modification, since the virtual ground is formed by the wide conductor film as described above, the effect of preventing noise in the signal wiring 201 can be exhibited, and Two substrates 207 and 208 made of an insulating material and two conductive films 21
2 and 213 are alternately stacked.
When a laminate with a semiconductor chip is formed, thermal deformation of the two is suppressed, and peeling of bonding between the two due to thermal deformation can be prevented as much as possible.

However, the wiring body 200 in the present embodiment
G, the lower surface of the upper substrate 207 or the lower substrate 2
The power supply wiring 212 connected to the power supply wiring 202 on the first surface 210 is formed on the second surface 220 which is the upper surface of the substrate 08, and on the third surface 230 which is the lower surface of the lower substrate 208, A structure in which a ground wiring 213 connected to the ground wiring 203 on the first surface 210 may be formed. Also in that case, the effect of blocking crosstalk and switching noise can be exhibited by virtual grounding.

(6) Sixth Modified Embodiment FIGS. 18A to 18C show a first surface 210, a second surface 220, and a third surface 23 of a wiring body 200H according to a sixth modified embodiment.
0 is a plan view showing the structure at 0. FIG. The wiring body 200H according to the present modification includes the wiring body 2 according to the fifth modification.
Similar to 00G, the two substrates 207 and 208 are stacked. On the first surface 210, which is the upper surface of the upper substrate 207, the signal wiring 201 and the power wiring 2
02, the grounding wiring 203 and the like are formed.
The pad portion is provided only at the end on the 06 side. A ground wiring 213 is formed on the lower surface of the upper substrate 207 or on the second surface 220 which is the upper surface of the lower substrate 208.
On the third surface 230, which is the lower surface of the lower substrate 208, the power supply wiring 212 and the pad portions 221 and
22, 223 are provided. The wiring on each surface and the pad portion are electrically connected via a conductive material formed in the through hole. In the wiring body 200H according to the present modification, for example, in FIG.
As shown in (a), each pad portion 22 on the third surface 230
1, 222, 223, soldering, brazing, welding,
Each lead on the lead frame can be electrically connected via a conductive adhesive or the like.

According to the wiring body 200H according to the present modification, similar to the wiring body 200G according to the fifth modification, a virtual ground is formed by a wide conductor film, so that noise in the signal wiring 201 is prevented. The effect can be exhibited, and the inductance of the connection between the lead and the wiring can be reduced. Further, since the two substrates 207 and 208 and the two conductor films 212 and 213, which are made of an insulating material, are alternately laminated, when forming a laminate with a semiconductor chip, the heat of both substrates is reduced. Deformation is suppressed, and peeling of bonding between the two due to thermal deformation can be prevented as much as possible.

However, the wiring body 200 according to this modification is
H, the lower surface of the upper substrate 207 or the lower substrate 2
The power supply wiring 212 connected to the power supply wiring 202 on the first surface 210 is formed on the second surface 220 which is the upper surface of the substrate 08, and on the third surface 230 which is the lower surface of the lower substrate 208, A structure in which a ground wiring 213 connected to the ground wiring 203 on the first surface 210 may be formed. Also in that case, the effect of blocking crosstalk and switching noise can be exhibited by virtual grounding.

(7) Seventh Modified Embodiment FIGS. 19A to 19C are perspective views showing a structure when a wiring body 200I and a semiconductor chip 100 according to a seventh modified embodiment are bonded together. FIG. 19A is a perspective view of a wiring body 200I according to the present modification. The wiring body 200I has a rectangular opening 206 at the center, and has an insulating support base 205 formed so that the outer side is substantially rectangular, and wiring thereon. As shown in FIG. 19A, on the first surface 210 of the wiring body 200I, a large number of wirings, that is, signal wirings 201 extending from the vicinity of the outer side to the vicinity of the opening 206 are formed. Both ends of the wiring 201 are pad portions for wire bonding. However, only the outer and inner pad portions 202a and 202b of the power supply wiring and the outer and inner pad portions 203a and 203b of the ground wiring are formed on the first surface 210, and are illustrated. Not on the second surface 220,
A power supply wiring and a grounding wiring occupying almost half of the area on the surface are formed. The power supply wiring and the grounding wiring on the second surface 220 are the pad portions 202a, 202b and 203 of the power supply wiring and the grounding wiring on the first surface 210 side.
a, 203b are electrically connected via conductive members formed in through holes (not shown). The feature of the wiring body 200I according to this modification is that a noise prevention wiring 204 is formed between the signal wirings 201 on the first surface 210 of the insulating support base 205, and the noise prevention wiring 204 is formed. 204 is a second surface 220 via a conductive member formed in a through hole (not shown).
Side is connected to the power supply wiring or the grounding wiring.

Then, after the wiring body 200I is mounted on the semiconductor chip 100 shown in FIG. 19B to obtain the state shown in FIG. 19C, the semiconductor chip 100 Electrical connection between the bonding pad and the pad portion of each wiring on the wiring body, and between the lead and the pad portion of each wiring, and further, resin sealing, lead By performing the cutting, the semiconductor device is completed.

Also in this modification, a semiconductor device having high noise resistance and a high-speed operation function and having an excellent impedance matching function can be obtained as in the above embodiments. In addition, in this modification, the signal wiring 20
1 is provided with the noise prevention wiring 204, so that crosstalk between the signal wirings 201 can be reliably prevented.

It is also possible to form a grounding wiring that shows almost the entire surface on the second surface 210, and connect all the noise prevention wirings to this grounding wiring.

(8) Eighth Modification FIG. 20 shows a second modification of the wiring body 200J according to the eighth modification.
It is a top view which shows the structure of the surface 220 side. Wiring body 200J
Although the illustration of the structure on the first surface side is omitted, it has a structure similar to the wiring body 200A in the above-described first embodiment. The feature of the wiring body 200J according to the present modification is that the power supply wiring 212 formed on the second surface 220 and the grounding wiring 213 are adjacent to each other via a folded boundary. Then, the power supply wiring 212 and the grounding wiring 21
3 is connected to a power supply wiring and a grounding wiring on the first surface 210 side via conductive members formed in the through holes 215, respectively.

According to the wiring body 200J of the present modification, the power supply wiring 212 formed on the second surface 220 and the grounding wiring 213 are adjacent to each other via the folded boundary. A large capacitance of the capacitor constituted by the two wirings 212 and 213 can be ensured. In other words, by setting such various patterns, the capacitance can be widely adjusted, so that a high noise removal function can be exhibited.

Next, the setting of an appropriate interval between the power supply wiring 212 and the grounding wiring 213 for obtaining a noise reduction effect will be described. For example, the material constituting the power supply wiring 212 and the grounding wiring 213 is Cu foil, and the thickness thereof is 5
Assuming 0 μm (= 5 × 10 ⁻³ cm) and the total length of the meandering opposing region is 4 cm, the area of the opposing electrode is 20 ×
It is 10 ⁻³ cm ² . Here, assuming that an interval between the wirings is d, an appropriate interval d can be obtained as follows. However, the dielectric constant of vacuum εo = 8.854 × 10 ⁻¹⁴ F / c
m, and the relative permittivity εN of the sealing resin is set to 4.2. In the following calculation, an interval d for obtaining a capacitance C of 0.1 μF or more is obtained.

D = ε · S / C = 8.854 × 10 ⁻¹⁴ × 4.2 × 20 × 10 ⁻³ / 1 × 10 ⁻¹ = 7.4 (μm) That is, the capacitance C of 0.1 μF or more In order to obtain this, it is necessary that the power supply wiring 212 and the grounding wiring 213 face each other at an interval of 7.4 μm or less. In this way, the interval d for obtaining the desired capacitance C can be set.

(9) Ninth Modification FIGS. 21A to 21C are perspective views showing a structure when a wiring body 200K and a semiconductor chip 100 according to a ninth modification are bonded to each other. FIG. 21A is a perspective view of a wiring body 200K according to this modification. The wiring body 200K has a rectangular opening 206 in the center, and has an insulating support base 205 formed so that the outer side is substantially rectangular, and wiring formed thereon. Then, as shown in FIG. 21A, on the first surface 210 of the insulating support base 205, a number of wirings, that is, signal wirings 201 extending from the vicinity of the outer side to the vicinity of the opening 206 are formed. Both ends of the signal wiring 201 are pad portions for wire bonding. Further, on the outer side of the insulating support base 205 and in the vicinity of the opening 206, the pad portion 202 of the power supply wiring is provided.
a, 202b and pad portions 203a, 20 of the ground wiring.
3b are formed. On the other hand, although not shown,
On the second surface 220, a power supply wiring and a grounding wiring occupying almost half of the second surface 220 are formed. This second
The power supply wiring and the grounding wiring on the surface 220 are respectively connected to the pad portions 202a, 202b, and 20 on the first surface 210 side.
3a and 203b are electrically connected via conductive members formed in the through holes. The feature of the wiring body 200 </ b> K according to the present modification is that neither the power supply wiring nor the grounding wiring is formed on the first surface 210. Then, after the wiring body 200K is mounted on the semiconductor chip 100 shown in FIG. 21B to obtain the state shown in FIG. 21C, the bonding on the semiconductor chip 100 is performed in the same manner as in the above embodiments. Electrical connection is made between the pad and the pad portion of each wiring on the wiring body 200K, and between the lead and the pad portion of each wiring, and further, as in the above-described embodiments, resin sealing and lead cutting are performed. Is performed, the semiconductor device is completed.

With such a structure, a semiconductor device having high noise resistance and a high-speed operation function and an excellent impedance matching function can be obtained as in the above embodiments. In particular, in this modification, the wiring body 200
Since there is no wide power supply wiring or ground wiring on the first surface 210 side of K, there is an advantage that the pattern of the signal wiring 201 on the first surface 210 can be more varied.

(10) Tenth Modification FIGS. 22A to 22C are perspective views showing a structure when a wiring body 200L and a semiconductor chip 100A according to a ninth modification are bonded to each other. FIG. 22A is a perspective view of a wiring body 200L according to the present modification. The insulating support base 205 in the wiring body 200L is basically rectangular, but has a number of cutouts 209 around the periphery. The central portion of the first surface 210 of the wiring body 200L is a mounting region Retr2 for the second semiconductor chip, so that semiconductor chips and various electronic components other than the semiconductor chip 100A shown in FIG. 22B can be mounted. It has become. In the wiring body 200L of the present modification, a detailed wiring structure is not shown.

Then, after the wiring body 200L is mounted on the semiconductor chip 100 shown in FIG. 22B to obtain the state shown in FIG. 22C, the semiconductor chip 100 Electrical connection between the bonding pad and the pad portion of each wiring on the wiring body, and between the lead and the pad portion of each wiring, and further, resin sealing, lead By performing the cutting, the semiconductor device is completed.

With such a structure, a semiconductor device having high noise resistance and a high-speed operation function and having an excellent impedance matching function can be obtained as in the above embodiments. In particular, the present modified example is advantageous when a semiconductor chip having a large area is provided, and it is possible to variously design the formation locations and patterns of wirings and pad portions, and to design the first and second surfaces 210 and 220 of the wiring body 200L. Both have the advantage that a semiconductor chip can be mounted. In addition, a cutout portion 209 as shown in the present modified embodiment and an opening 20 provided in the wiring bodies 200A to 200K in each of the above-described embodiments and modified embodiments are provided in one insulating support base 205.
By forming them together with No. 6, further various wiring patterns can be formed.

(11) Eleventh Modification FIGS. 23A to 23C are perspective views showing a structure when a wiring body 200M and a semiconductor chip 100B according to a ninth modification are bonded to each other. FIG. 23A is a perspective view of a wiring body 200M according to the present modification. The structure of the wiring body 200M is the same as that of the wiring body 2 shown in FIG. 21A except that the long side of the opening 206 is parallel to the long side of the insulating support base 205.
It is the same as the structure of 00K. Therefore, detailed description of the wiring and the like is omitted.

Then, the wiring body 200M is mounted on the semiconductor chip 100B shown in FIG.
After that, the electrical connection between the bonding pad on the semiconductor chip and the pad portion of each wiring on the wiring body, and the electrical connection between the lead and the pad portion of each wiring by the same method as the above embodiments. The semiconductor device is completed by performing the connection and further performing the resin sealing and the lead cutting as in the above embodiments.

With such a structure, a semiconductor device having high noise resistance and a high-speed operation function and an excellent impedance matching function can be obtained as in the above embodiments.

(Fifth Embodiment) Next, a fifth embodiment of the semiconductor device obtained by laminating the second wiring body 250 on any of the wiring bodies 200A to 200M according to each of the above-described embodiments and modifications will be described. A fifth embodiment will be described.

FIGS. 24A to 24C are perspective views showing a structure when the two wiring bodies 200A to 200M and 250 according to the fifth embodiment and the semiconductor chip 100 are bonded. FIG. 24A is a perspective view illustrating the structure of the second wiring body 250. FIG. The wiring body 250 has a rectangular opening 256 at the center, an insulating support base 255 formed so that the outer side is substantially rectangular, and a signal formed by printing on the insulating support base 255. Wiring 251, power supply wiring 252, and ground wiring 253. However, both ends of each of the wirings 251, 252, and 253 are pad portions. Then, as an example, the second wiring body 250 is overlaid on the wiring bodies 200A to 200M shown in FIG. 24B to form a stacked wiring body shown in FIG.

Further, after mounting the wiring bodies 200A to 200M and 250 laminated on the semiconductor chip 100 shown in FIG. 24D (see FIG. 24E), the bonding pads and the wiring body of the semiconductor chip 100 are mounted. 200A-20
0M and between two wiring bodies 200A-2
The pads between 00M and 250M are connected to each other via a thin metal wire or a thin metal plate, and the leads are electrically connected to the pads of each wiring. Further, similar to the above-described embodiments, By performing resin sealing and lead cutting,
The semiconductor device is completed.

According to the semiconductor device of this embodiment, a semiconductor device having high noise resistance and a high-speed operation function and having an excellent impedance matching function can be obtained as in the above embodiments. In particular, in the present embodiment, signals can be transmitted to and received from more external devices via the wirings 251, 252, and 253 on the second wiring body 250, and the application range of the semiconductor device is expanded. I do.

(Sixth Embodiment) Next, a sixth embodiment will be described with reference to FIGS. 25 (a) to 25 (d) and FIG.

FIGS. 25A to 25D are views showing the structure of a semiconductor device according to the sixth embodiment.
25A is a plan view of the semiconductor chip or the like viewed from the second surface side, FIG. 25B is a cross-sectional view taken along line XXVb-XXVb shown in FIG. 25A, and FIG. FIG. 25D is a plan view as viewed from one side, and FIG.
It is sectional drawing in the XXVd line.

As shown in FIGS. 25A to 25D, the basic structure of the semiconductor device according to the present embodiment is almost the same as the structure of the semiconductor device according to the first embodiment.
In the present embodiment, the wiring body 200C shown in FIG. 14 is used. However, the wiring bodies 200A, 200B, 200D
~ 200K may be used. And in this embodiment,
It is characterized in that a pair of wiring body fixing leads 361 to 364 for supporting and fixing the insulating support base 205 on both short sides are provided. Then, the wiring body fixing lead 36
1 to 364 are connected to the ground wiring 213 on the second surface 220 of the wiring body 200C by soldering, brazing, welding, or a conductive adhesive. However, both may be fixed with an insulating adhesive.

On the other hand, the power lead 302 and the ground lead 303 are arranged at the outermost positions adjacent to the signal leads 301 arranged in parallel with each other along the two long sides of the wiring body 200C. Then, each pair of power leads 30
The second lead 2 and the ground lead 303 are connected to each other by a second thin metal wire 402 to the power supply wiring and the ground wiring pad on the first surface 210 of the wiring body 200C.

In this embodiment, the method of laminating the semiconductor chip 100 and the wiring body 200C is as shown in FIGS. 3A to 3C in the first embodiment.

FIG. 26 is a plan view of a lead frame 300F used in this embodiment. Although FIG. 26 shows only two chip mounting areas, it is continuous in the vertical direction in FIG. Many chip mounting areas may be formed in the device.

In the present embodiment, as in the first embodiment, a semiconductor device having high noise resistance and a high-speed operation function and a high impedance matching function can be obtained.

In addition, a pair of wiring fixing leads 361 to 364 for supporting and fixing the wiring body 200C at both short sides.
Is provided, the support of the wiring body 200C at the time of assembling the semiconductor device becomes more stable and strong,
Manufacturing can be facilitated. Further, in the present embodiment, all the lead terminals after resin sealing are the same as those of the semiconductor device.
(The wiring fixing leads 361 to 364 are formed of a sealing resin 500).
Is cut in the vicinity of the surface of the printed circuit board).

However, in this embodiment, instead of soldering, brazing using a high melting point metal brazing,
There are welding such as resistance welding, laser welding, etc., in which a current flows between u-plated lead-pad portions and Joule heat is used to connect the two, and bonding using a conductive adhesive may be used. Further, a thin metal plate may be used instead of the thin metal wire.

In each of the above embodiments, the lead frame is provided with the lead for fixing the wiring body or the bar for fixing the wiring body, but these are not necessarily required. In other words, when connecting the lead of the lead frame to the wiring body assembled with the semiconductor chip, assembly can be performed smoothly by separately providing means for supporting and fixing the wiring body with an assembling apparatus or the like. It is.

In this and other embodiments, the wiring body fixing lead or the wiring body fixing bar may support the wiring body on the first surface side or the second surface side. .
The same applies when the grounding lead, the power supply lead, or the signal lead is used as a wiring body fixing lead or a wiring body fixing bar.

Further, the power supply wiring and the grounding wiring need not be provided at both ends of each signal wiring. That is, the power supply wiring and the ground wiring may be mixed between many signal wirings. Further, also in the DIP type semiconductor device, the power supply lead and the ground lead do not have to be at the outermost positions.

(Seventh Embodiment) Next, a seventh embodiment in which a ferroelectric chip extending between a power supply wiring and a ground wiring is provided.
An embodiment will be described.

FIGS. 27 (a) to 27 (c) show, respectively,
FIG. 2 is a plan view of the wiring body according to the present embodiment viewed from a first surface, and FIG.
FIG. 2 is a plan view seen from a plane, and a partial cross-sectional view showing a ferroelectric chip mounting area in an enlarged manner.

In the present embodiment, a ferroelectric chip 261 is provided over the power supply wiring 202 and the grounding wiring 203 on the first surface 210 of the wiring body 200B according to the fourth embodiment. This ferroelectric chip 261
Are connected to the power supply wiring 202 and the grounding wiring 203 via bumps 262, respectively. That is, when viewed as an electric circuit, the power supply wiring 202 and the grounding wiring 20
3 is provided with a capacitor.

In this embodiment, since the ferroelectric chip 261 is provided over the power supply wiring 202 and the grounding wiring 203, power supply noise can be removed without providing a pass capacitor outside the semiconductor device. Therefore, a semiconductor device with low noise and good performance can be easily obtained.

Note that PZT, barium titanate, or the like can be used as the ferroelectric material constituting the ferroelectric chip 261 in this embodiment.

Further, the ferroelectric chip 261 of the present embodiment is the same as the wiring body 200B of the fourth embodiment.
In addition, as long as the power supply wiring and the grounding wiring are close to each other, the wiring can be provided in the wiring body of any of the embodiments. In that case, the ferroelectric chip may be provided not only on the first surface of the wiring body but also on the second surface.

(Eighth Embodiment) Next, an eighth embodiment which is an example in which a chip capacitor extending between a power supply wiring and a ground wiring is provided will be described.

FIGS. 28 (a) to 28 (c) show, respectively,
FIG. 2 is a plan view of the wiring body according to the present embodiment viewed from a first surface, and FIG.
FIG. 2 is a plan view as viewed from a plane, and a partial cross-sectional view showing an enlarged chip capacitor mounting area.

In the present embodiment, a chip capacitor 265 is provided on the first surface 210 of the wiring body 200B according to the fourth embodiment described above, extending over the power supply wiring 202 and the grounding wiring 203. This chip capacitor 2
Numeral 65 is connected to the power supply wiring 202 and the grounding wiring 203 via the baked silver paste 266, respectively. That is, when viewed as an electric circuit, similarly to the seventh embodiment, a capacitor is provided between the power supply wiring 202 and the grounding wiring 203.

In the present embodiment, similarly to the seventh embodiment, since the chip capacitor 265 extending between the power supply wiring 202 and the grounding wiring 203 is provided, a pass capacitor is provided outside the semiconductor device. Even without this, power supply noise can be easily removed, and a semiconductor device with low noise and good performance can be easily obtained.

Note that the chip capacitor 265 of this embodiment is the same as the wiring body 200 of the fourth embodiment.
In addition to B, the wiring body according to any of the embodiments can be provided as long as there is a portion where the power supply wiring and the grounding wiring are close to each other. In that case, the chip capacitor may be provided not only on the first surface of the wiring body but also on the second surface.

(Ninth Embodiment) Next, a ninth embodiment which is an example of a semiconductor device having a wiring body provided with solid power supply wiring or ground wiring on both sides will be described.
FIG. 29 is a perspective view schematically showing the structure of the semiconductor device according to the present embodiment. However, in FIG. 29, illustration of wirings and leads is omitted.

As shown in the figure, the feature of the semiconductor device according to the present embodiment is that the first wiring body 200X as shown in each of the above embodiments and the like is provided on the first surface side of the semiconductor chip 100. On the second surface side of the chip 100, a second power supply wiring or a grounding wiring occupying almost the entire surface on both surfaces is provided.
The point is that the wiring body 200N is provided. The first wiring body 200X and the second wiring body 200N may have the following wirings.

First, there is a case where the power supply wiring occupying almost the entire surface is formed on one surface of the second wiring body 200N, and the ground wiring occupying almost the entire surface is formed on the other surface. In this case, it is sufficient that the first wiring body 200X has at least a signal wiring. However, the first
The wiring body 200X may further be provided with a power supply wiring and a grounding wiring as in the above embodiments.

Second, a power supply wiring occupying almost the entire surface may be formed on both surfaces of the second wiring body 200N.
In this case, the first wiring body 200X only needs to have at least the ground wiring and the signal wiring. However,
The power supply wiring may be further provided in the first wiring body 200X.

Third, a ground wiring occupying almost the entire surface may be formed on both surfaces of the second wiring body 200N.
In this case, the first wiring body 200X only needs to have at least the power supply wiring and the signal wiring. However,
The first wiring body 200X may further be provided with a ground wiring.

In the present embodiment, the semiconductor device as shown in each of the above embodiments is further provided with a second wiring body 200N having a large-area solid wiring for grounding and power supply. In addition, a high-frequency semiconductor device in which the grounding line and the power supply line are more stable and the voltage variation hardly occurs can be obtained. Further, when a large-area solid-state grounding wiring or power supply wiring is formed on both surfaces of the second wiring body 200N, an electric current flows in parallel from both surfaces, so that the electric potential of the ground line or the power supply line is reduced. This has the effect of reducing the resistance value.

(Tenth Embodiment) Next, an example of a high-frequency semiconductor device having a general lead frame structure and a wiring body provided with solid power wiring or ground wiring on both sides will be described. A tenth embodiment will be described. FIG. 30 is a perspective view schematically showing the structure of the semiconductor device according to the present embodiment. However, some wirings and leads are not shown in FIG. FIG. 30 shows the structure of the semiconductor device before the resin sealing step is performed.

In the semiconductor device of this embodiment, as shown in FIG. 30, a ground wiring 213 occupying almost the entire surface on the first surface 210 of the insulating support base 205 is formed.
0, a wiring body 200P on which power supply wiring (not shown) occupying almost the entire surface, and a first surface 2 of the wiring body 200P.
10. A lead frame 30 for performing signal connection between a semiconductor chip 100 mounted on the semiconductor chip 10 and a bonding pad on the semiconductor chip 100 or a wiring on the wiring body 200P
0G is provided. Then, the semiconductor chip 100
Bonding pad and ground wiring 2 of wiring body 200P
13 and between the bonding pad of the semiconductor chip 100 and the power supply terminal 242 on the first surface 210 connected to the power supply wiring on the back surface of the wiring body 200P are connected via the first thin metal wire 401, respectively. I have. The lead frame 300G has a signal inner lead 30.
1a, the outer lead 301b connected to the signal inner lead 301a, and the second surface 22 of the wiring body 200P.
Wiring fixing lead 36 connected to power supply wiring on 0
2, a wiring body fixing lead 363 connected to a ground terminal (not shown) on the second surface 220 connected to the ground wiring 213 of the wiring body 200P, and a dam bar 370 for connecting the leads to each other. Is provided. The wiring body fixing lead 362 supports the wiring body 200P and connects an external power supply line to a power supply line in the semiconductor device.
Supports the wiring body 200P and connects an external ground line to a ground line in the semiconductor device. The bonding pads of the semiconductor chip 100 and the signal inner leads 301a are connected via the second thin metal wires 402.

Although the semiconductor device of this embodiment has a general lead frame structure having inner leads 301a, the ground wiring 213 occupying almost the entire surface on one surface.
A wiring body 200P having power supply wiring occupying almost the entire surface on the other surface is provided, and the semiconductor chip 100 is mounted on the wiring body 200P. A line and a ground line can be obtained. In a conventional semiconductor device, since the member supporting the semiconductor device is a lead frame which is a conductor instead of the insulating support base 205 as in the present embodiment, power supply wiring and grounding wiring are provided on both surfaces. Although such a structure cannot be taken, in the present embodiment, the wiring body 2
Focusing on the features of 00P, such a structure can be adopted.

However, also in the present embodiment, the wiring 2
In each of the first surface 210 and the second surface 220 of 00P, only the ground wiring or only the power wiring may be provided. In that case, the electric resistance value in the ground line or the power supply line can be reduced.

(Eleventh Embodiment) Next, the first embodiment of the wiring body will be described.
An eleventh embodiment, which is an example in which opposing regions at a narrow interval are provided between the ground wiring and the power supply wiring on the surface side, will be described.

FIGS. 31 (a) and 31 (b) are plan views of the insulating support base 205 in the wiring body 200Q according to the present embodiment as viewed from the first surface 210 side and the second surface 220 side, respectively. As shown in FIG. 31A, on the first surface 210 of the insulating support base 205 in the wiring body 200Q, a linear signal wiring 2 extending from near the outer end to near the opening 206.
01, a belt-like power supply wiring 202, and the power supply wiring 20
2 and a strip-shaped grounding wire 203 extending in the vicinity are formed by printing. Further, as shown in FIG. 31B, on the second surface 220 of the insulating support base 205, a power supply wiring 212 and a grounding wiring 213 that divide almost half of the entire surface are formed. Then, the second surface 220
The power supply wiring 212 and the grounding wiring 213 on the side
The power supply wiring 202 and the ground wiring 203 on the 10 side are electrically connected to each other via conductive members formed in the through holes 215.

Here, the feature of the wiring body according to the present embodiment is that, as shown in FIG. 31A, on the first surface of the insulating support base 205, the power supply wiring 202 and the grounding wiring 20 are provided.
3 are not parallel from the central part to the outer end, but each of the band-like parts 202a, 203a near the outer end.
203a is opened up and down, and linear portions 202b and 203b extending upward and downward from the opened strip portions 202a and 203a are provided. Since the linear portions 202b and 203b are alternately interleaved, a region where the power supply wiring 202 and the grounding wiring 203 face each other at a small interval meanders, and the length of the region facing each other is reduced. Is configured to enlarge.

According to the wiring body 200Q of this embodiment, the power supply wiring 2 is provided on the first surface 210 side of the wiring body 200Q.
The wiring body 200 shown in FIG. 20 in the eighth modification of the above-described wiring body is expanded by increasing the length of the region where the wiring 02 and the grounding wiring 203 oppose each other at a narrow interval.
The same effect as J can be exerted. That is, 2
By setting various patterns, such as increasing the capacitance of the capacitor formed by the two wirings 202 and 203, the capacitance can be adjusted widely, so that a high noise removing function can be exhibited.

The wiring body 200Q according to the present embodiment
Are the lead frames 300A, 300B, 300C, 300 shown in FIG. 4, FIG. 6, FIG. 8, FIG.
D, 300E, etc. can be used in combination.

(Twelfth Embodiment) Next, a description will be given of a twelfth embodiment, which is an example in which a waveguide capable of improving the pass characteristic of a high-frequency signal is provided in a wiring body.

FIG. 32A is a cross-sectional view showing a structure of a microstrip line that can be formed on a part of an arbitrary wiring body in each of the above embodiments. That is, by appropriately adjusting the relative permittivity and thickness of the insulating support base 205 and the width and thickness of the signal wiring 201, the ground wiring 213 on the back surface, the signal wiring 201, and the dielectric film are formed. A microstrip line including the insulating support base 205 can be provided.

FIG. 32B is a cross-sectional view showing a structure of a coplanar line that can be formed in a part of the wiring body. That is, by providing a signal wiring 201 and a pair of grounding wirings 203 sandwiching the signal wiring 201 from both sides on one surface of the insulating support base 205, the insulating support base 205 serving as a base is formed of a dielectric film. The coplanar line described above can be configured.

(Thirteenth Embodiment) Next, a thirteenth embodiment in which a signal connection between a semiconductor chip and a wiring body is made via bumps will be described with reference to FIGS.
This will be described with reference to (d) and FIGS. 38 (a) and (b).

FIGS. 37A to 37D are diagrams showing the structure of the semiconductor device according to the thirteenth embodiment.
37A is a plan view of a semiconductor chip or the like viewed from the second surface side, FIG. 37B is a cross-sectional view taken along the line XXXVIIb-XXXVIIb shown in FIG. 37A, and FIG. FIG. 37 (d) is a plan view seen from one surface side, and FIG. 37 (c) is shown.
It is sectional drawing in the XXXVIId-XXXVIId line.

As shown in FIGS. 37A to 37D, the basic structure of the semiconductor device according to the present embodiment is the same as that shown in FIG.
This is the same as the structure of the semiconductor device shown in FIGS. However, in the present embodiment, the first fine metal wire connecting the wiring in the wiring body 200R and the bonding pad of the semiconductor chip 100 is not formed. That is, the present embodiment is characterized in that both are connected via bumps 405 such as solder bumps.

FIGS. 38A and 38B are plan views of the insulating support base 205 in the wiring body 200R as viewed from the first surface 210 side and the second surface 220 side, respectively. As shown in FIG. 38 (a), on the first surface 210 of the insulating support base 205 in the wiring body 200R, a large number of wirings extending from the vicinity of the outer end to the vicinity of the opening 206, that is, a linear signal Wiring 20
1, strip-shaped power supply wiring 202, strip-shaped grounding wiring 203
Etc. are formed by printing. This structure is the same as the structure of the wiring body 200A according to the first to third embodiments. However, in the wiring body 200R according to the present embodiment, as shown in FIGS. 38 (a) and (b), the inner pad portions of the wirings 201, 202 and 203 have the first surface 2R.
10 is not provided. Further, on the second surface 220 side, a wide power supply wiring and a ground wiring are not formed. Then, on the second surface 220 of the insulating support base 205 via the conductive material formed in the through hole, the first
A signal wiring pad 225, a power wiring pad 226, and a ground wiring pad 227 connected to the signal wiring 201, the power wiring 202, and the ground wiring 203 on the surface 210 side are formed. I have. In addition, the wiring body 20
In the vicinity of the short side end of the second surface 220 of the OR, outer power supply wiring pad portions 222 and ground wiring pad portions 223 connected to the power supply lead 302 and the grounding lead 303 are formed. Have been. This power supply wiring pad 2
The ground wiring pad portion 223 is connected to the power supply wiring 202 and the ground wiring 203 on the first surface 210 via conductive materials formed in the through holes.

In this embodiment, the semiconductor chip 10
The method of laminating 0 and the wiring body 200R is different from the above embodiments, and is performed by so-called flip chip mounting. That is, the signal bonding pads on the semiconductor chip 100 (members indicated by reference numeral 101 shown in FIG. 3B) and the signal wiring pads 22 in the wiring body 200R.
5, a power bonding pad on the semiconductor chip 100 (a member indicated by reference numeral 102 shown in FIG. 3B).
Between the power supply wiring pad 226 in the wiring body 200R and
Ground bonding pad (member 103 shown in FIG. 3B) on the semiconductor chip 100 and the wiring body 2
The semiconductor chip 100 and the wiring body 200R are mechanically joined with an adhesive or the like with a bump interposed between the semiconductor chip 100 and the ground wiring pad 227 in 00R.

When the leads shown in FIG. 4 are used in the present embodiment, they are formed at the outer ends of the signal leads 301 and each wiring on the wiring body 200R. The pad portion is connected by the second thin metal wire 402. Also, the power lead 302 and the ground lead 3
03 is soldered to the power supply wiring pad 222 and the grounding wiring pad 223 on the second surface 220 of the wiring body 200R.
The connection is made by brazing, welding, conductive adhesive or the like.

Further, the semiconductor chip 100, the wiring body 20
After embedding the end portions (inner leads) of the leads and the lead of the lead frame in the sealing resin, the dam bar and the outer leads of the lead frame are cut to obtain the structure of the semiconductor device shown in FIG.

In the present embodiment, the wiring body 200R and the bonding pads of the semiconductor chip 100 are connected by bumps instead of the first thin metal wires. Can be further reduced.

In the present embodiment, the pad provided on the second surface 220 side of the wiring body 200R and the semiconductor chip 1
2 is connected via a bump to the bonding pad provided on the first surface of the wiring body 200A, for example, using the wiring body 200A shown in FIG.
The pad portion provided on the side 10 and the bonding pad of the semiconductor chip can be connected via a bump.

[0180]

According to the semiconductor device of the present invention, as a structure of the semiconductor device, a wiring body composed of an insulator and a wiring supported by an insulating support base is interposed between a bonding pad and a lead of a semiconductor chip. In this case, the semiconductor device is sealed with a sealing resin, so that it is possible to provide a semiconductor device having high noise resistance and high-speed operability and an excellent impedance matching function.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment viewed from a second surface, a cross-sectional view taken along a line Ib-Ib, a plan view viewed from a first surface, and a cross-sectional view taken along a line Id-Id. is there.

FIG. 2 shows a first surface and a second surface of the wiring body according to the first embodiment.
It is the top view seen from the surface.

FIG. 3 is a perspective view showing a step of laminating the wiring body and the semiconductor chip according to the first embodiment.

FIG. 4 is a plan view of the lead frame according to the first embodiment.

FIG. 5 is a plan view of the semiconductor device according to the second embodiment as viewed from the second surface side, a cross-sectional view taken along line Vb-Vb, a plan view as viewed from the first surface side, and a cross-sectional view taken along line Vd-Vd. is there.

FIG. 6 is a plan view of a lead frame according to a second embodiment.

FIG. 7 is a plan view of the semiconductor device according to the third embodiment as viewed from the second surface side, a cross-sectional view taken along line VIIb-VIIb, a plan view as viewed from the first surface side, and a cross-sectional view taken along line VIId-VIId. is there.

FIG. 8 is a plan view of a lead frame according to a third embodiment.

FIG. 9 is a plan view showing a modification of the lead frame according to the third embodiment.

FIG. 10 is a plan view of the semiconductor device according to the fourth embodiment when viewed from the second surface side, a cross-sectional view along line Xb-Xb, a plan view as viewed from the first surface side, and a cross-sectional view along line Xd-Xd. is there.

FIG. 11 is a plan view of a wiring body according to a fourth embodiment viewed from a first surface and a second surface.

FIG. 12 is a plan view of a lead frame according to a fourth embodiment.

FIG. 13 is a plan view of a wiring body according to a first modification as viewed from a first surface and a second surface.

FIG. 14 is a plan view of a wiring body according to a second modification as viewed from a first surface and a second surface.

FIG. 15 is a plan view of a wiring body according to a third modification as viewed from a first surface and a second surface.

FIG. 16 is a plan view of a wiring body according to a fourth modification viewed from a first surface and a second surface.

FIG. 17 shows a first surface and a second surface of a wiring body according to a fifth modification.
It is the top view seen from the surface and the 3rd surface.

FIG. 18 shows a first surface and a second surface of a wiring body according to a sixth modification.
It is the top view seen from the surface and the 3rd surface.

FIG. 19 is a perspective view showing a step of laminating a wiring body and a semiconductor chip according to a seventh modification;

FIG. 20 is a plan view of a wiring body according to an eighth modification viewed from a second surface.

FIG. 21 is a perspective view showing a step of laminating a wiring body and a semiconductor chip according to a ninth modification.

FIG. 22 is a perspective view illustrating a step of laminating a wiring body and a semiconductor chip according to a tenth modification;

FIG. 23 is a perspective view showing a step of laminating a wiring body and a semiconductor chip according to an eleventh modification.

FIG. 24 is a perspective view showing a step of laminating two wiring bodies and a semiconductor chip according to a fifth embodiment.

FIG. 25 is a plan view of the semiconductor device according to the sixth embodiment as viewed from the second surface side, a cross-sectional view along line XXVb-XXVb, a plan view as viewed from the first surface side, and a cross-sectional view along line XXVd-XXVd. is there.

FIG. 26 is a plan view of a lead frame according to a sixth embodiment.

FIG. 27 is a plan view of the wiring body according to the seventh embodiment as viewed from a first surface, a plan view as viewed from a second surface, and a partial cross-sectional view showing a ferroelectric chip mounting region in an enlarged manner.

FIG. 28 is a plan view of the wiring body according to the eighth embodiment as viewed from a first surface, a plan view as viewed from a second surface, and an enlarged partial cross-sectional view of a chip capacitor mounting area.

FIG. 29 is a perspective view schematically showing a structure of a semiconductor device according to a ninth embodiment.

FIG. 30 is a perspective view schematically showing a structure of a semiconductor device according to a tenth embodiment.

FIG. 31 is a plan view seen from a first surface and a plan view seen from a second surface in a wiring body according to an eleventh embodiment.

FIG. 32 is a partial cross-sectional view of a microstrip line and a coplanar line according to a twelfth embodiment.

FIG. 33 is a perspective view showing the overall structure of a semiconductor device common to the embodiments.

FIG. 34 is a diagram showing the results of an experiment performed to compare the difference in ground noise between the conventional high-frequency semiconductor device and the high-frequency semiconductor device of the present embodiment.

FIG. 35 is an enlarged perspective view showing a connection portion between a lead frame and a semiconductor chip in the technique described in the conventional publication.

FIG. 36 is a plan view showing the structure of a conventional general lead frame.

FIG. 37 is a plan view of the semiconductor chip and the like according to the thirteenth embodiment as viewed from the second surface side, a cross-sectional view taken along line XXXVIIb-XXXVIIb, a plan view viewed from the first surface side, and a cross-sectional view taken along line XXXVIId-XXXVIId. It is.

FIG. 38 is a plan view of the wiring body according to the thirteenth embodiment as seen from the first surface side and a plan view as seen from the second surface side.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor chip 101 signal bonding pad 102 power supply bonding pad 103 grounding bonding pad 110 first surface 110 second surface 200 wiring body 201 signal wiring 202 power supply wiring 203 grounding wiring 204 noise prevention wiring 205 insulating support base 206 Opening 207 First substrate 208 Second substrate 210 First surface 212 Power supply wiring 213 Grounding wiring 215 Through hole 220 Second surface 221 Signal wiring pad 222 Power supply wiring pad 223 Ground wiring pad 230 Third surface 250 2 Wiring 251 Signal Wiring 252 Power Wiring 253 Ground Wiring 256 Opening 261 Ferroelectric Chip 262 Bump 265 Chip Capacitor 266 Silver Paste 300 Lead Frame 301 Signal Lead 302 Power Supply Over de 303 grounding lead 352, 353 wiring member fixing bars 361 to 364 wiring member fixing leads 401 first thin metal wires 402 second metal thin wires 500 sealing resin

Claims (15)

[Claims] 1. A semiconductor chip having a first surface and a second surface and having a plurality of bonding pads on the first surface, and a plate-shaped insulating support having an opening smaller than the first surface of the semiconductor chip. A wiring body which is constituted by a base and a plurality of wirings supported by the insulating support base and one end of which is arranged around the opening, and which is provided on a first surface of the semiconductor chip; A connection made of at least one of a metal thin wire and a metal thin film that electrically connects each bonding pad of the chip and the one end of each of the wirings. A semiconductor device, comprising: a member; and a plurality of leads connected to other portions of each wiring of the wiring body. 2. The semiconductor device according to claim 1, wherein the plurality of wires include a signal wire, a power wire, and a ground wire, and the plurality of leads are a signal lead, a power lead, and a ground wire. A lead between the signal wiring and the signal lead, a power supply wiring and the power supply lead, and a ground wiring and the ground lead are electrically connected, respectively. A semiconductor device. 3. The semiconductor device according to claim 2, wherein at least one of the first surface and the second surface of the insulating support base, the power supply wiring and the grounding wiring are arranged at a narrow distance from each other. A semiconductor device characterized in that it is formed to have regions facing each other with a space therebetween. 4. The semiconductor device according to claim 1, wherein the bonding pad of the semiconductor chip is formed so as to be located in the opening of the insulating support base. A semiconductor device characterized by the above-mentioned. 5. A semiconductor chip having a first surface and a second surface and having a plurality of bonding pads on the first surface, a plate-like insulating support base, and a plurality of wirings supported by the insulating support base. A wiring member provided on the first surface of the semiconductor chip, a connection member comprising a bump for electrically connecting each bonding pad of the semiconductor chip and a part of each of the wirings, A semiconductor device comprising: a plurality of leads connected to other portions of each wiring of a wiring body. 6. The semiconductor device according to claim 5, wherein said insulating support base in said wiring body has an opening smaller than a first surface of said semiconductor chip, and a plurality of wirings in said wiring body are said openings. A semiconductor device having one end disposed in a peripheral portion of the portion, wherein the bump connects one end of the wiring body and a bonding pad of the semiconductor chip. 7. The semiconductor device according to claim 5, wherein the plurality of wires include a signal wire, a power wire, and a ground wire, and the plurality of leads are a signal wire, a power wire, and a power wire. Including a ground lead, the signal wire and the signal lead, the power wire and the power lead, and the ground wire and the ground lead are respectively electrically connected. A semiconductor device characterized by being performed. 8. The semiconductor device according to claim 1, wherein the insulating support base is at least one of glass epoxy, polyimide, polyester, benzocyclobutene resin, BT resin, and polyimide amide ether. Any one
A semiconductor device comprising an organic material containing at least one of the following. 9. The semiconductor device according to claim 1, wherein the insulating support base is made of alumina, silicon nitride, aluminum nitride, silicon carbide, beryllium oxide, silicon, or an insulating film-forming metal. And a high-purity glass made of an inorganic material containing at least one of them. 10. The semiconductor device according to claim 1, wherein the wiring is formed by printing a conductive film on an insulating support base. apparatus. 11. The semiconductor device according to claim 1, wherein the wiring body supports the wiring body on one of a first surface and a second surface of the wiring body. A semiconductor device further comprising a body fixing support. 12. The semiconductor device according to claim 11, wherein said wiring body fixing support functions as at least one of a power supply lead and a grounding lead. 13. The semiconductor device according to claim 1, wherein the semiconductor chip, the wiring body, the connection member,
A semiconductor device, further comprising a sealing resin for sealing a portion of the lead on a wiring body side. 14. The semiconductor device according to claim 2, further comprising a ferroelectric chip provided over the ground wiring and the power supply wiring. 15. The semiconductor device according to claim 2, further comprising a chip capacitor provided across the ground wiring and the power supply wiring.