JPH11195620A - Manufacture of semiconductor device and sputtering device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sputter a high-melting point metal on the condition that the deterioration of the breakdown strength of a gate due to a sputtering device is not generated, in a method of manufacturing a semiconductor device, which is formed with a high-melting point metal silicide layer. SOLUTION: A semiconductor device is manufactured into a structure, wherein a high-melting point metal is deposited on the whole surface of a silicon substrate formed with a gate electrode of a semiconductor element to form a high-melting point metal film and thereafter, when a heat treatment is performed on the surface of the substrate and a high-melting point metal silicide layer is formed on the interface between the surface of the substrate and the high-melting point metal film, the high-melting point metal film is sputtered and deposited by a magnetron sputtering unit on the condition that the amount Q of a charge to reach the gate electrode is less than 5 C/cm<2> . Moreover, a sputtering device 30 is constituted into a structure, wherein a collimater plate 32, which has a multitude of through holes penetrated from a target toward a wafer and consists of a conductor, is made to interpose between a target holder 16 and a wafer holder 14 in a state that the plate 32 is grounded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MOS field effect transistor (MOSFET) for reducing the resistance by silicidizing the surface of a gate, a source and a drain in a self-aligned manner. And a method for producing the same. Further, the present invention relates to a sputtering apparatus capable of sputtering a high-melting-point metal on a polysilicon film while preventing the deterioration of the withstand voltage of a gate oxide film when a high-melting-point metal silicide film is formed on a gate electrode. is there.

[0002]

2. Description of the Related Art A conventional salicide process known as one of the methods for manufacturing a semiconductor device is disclosed in Japanese Unexamined Patent Application Publication No. 2-459.
There is a method disclosed in Japanese Patent Publication No. This conventional method of manufacturing a semiconductor device will be described with reference to longitudinal sectional views shown in the order of steps of FIGS. 3A to 3D.

As shown in FIG. 3A, an N well 302 is formed on a P-type silicon substrate 301 by a known method.
Next, a field oxide film 303 is formed on the surface of the P-type silicon substrate 301 as a field insulating film by a selective oxidation method. In the active region surrounded by the field oxide film 303, a gate insulating film 304 such as a silicon oxide film is sequentially formed.
Then, polycrystalline silicon is grown, and phosphorus is doped into the polycrystalline silicon by a known method to reduce the electric resistance of the polycrystalline silicon. Next, the gate electrode 305 is formed by patterning the polycrystalline silicon by a known method such as photolithography and dry etching.

Next, as shown in FIG. 3A, a low concentration N-type impurity diffusion layer 313 and a low concentration P-type impurity diffusion layer 314 are formed by photolithography and ion implantation. Next, a sidewall 306 made of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 305 by using a known chemical vapor deposition (CVD) technique and an etching technique.

Next, as shown in FIG. 3B, an N-type impurity diffusion layer 307 and a P-type impurity diffusion layer 308 are formed by photolithography and ion implantation. Thus, as the LDD structure, the N-type source / drain regions 30 are formed.
7. P-type source / drain regions 308 are formed. Next, the surface of the polycrystalline silicon as the gate electrode and the natural oxide film on the surface of the semiconductor substrate are removed, and for example, a titanium film 309 is removed.
Is sputter deposited.

Next, as shown in FIG. 3 (c), a rapid heat treatment (hereinafter, RTA) at 700 ° C. or lower is performed in a nitrogen atmosphere to silicide only the titanium film 309 in contact with silicon, thereby forming a C49 type structure. Titanium silicide layer 31
0 is formed. At this time, the field oxide film 303
Film 309 in contact with side wall 306
Then, part of the titanium film on the semiconductor substrate is nitrided to form a titanium nitride film 311.

Next, as shown in FIG. 3 (d), wet etching is performed selectively using a mixed solution of ammonia water and hydrogen peroxide solution, etc.
Remove only 11 Next, RTA at a higher temperature (800 ° C. or higher) than the above-mentioned RTA is performed, and C having a lower electrical resistivity than the above-mentioned titanium silicide layer 310 having the C49 type structure is formed.
A 54-type titanium silicide layer 312 is formed.

By using the salicide process described above, since the surface portions of the polycrystalline silicon 305 and the N-type and P-type impurity diffusion layers 307 and 308 are silicified in a self-aligned manner, the resistance is reduced. Can be speeded up. This salicide process has an advantage that silicidation can be selectively performed only in a necessary region.

Meanwhile, a conventional magnetron sputtering apparatus 10 generally has a sputtering system as shown in FIG.
The chamber 12 includes a wafer holder 14 on which a wafer W is placed, and a cathode magnet 16 for holding a target T at a position facing the wafer W at a distance. Using a conventional magnetron sputtering apparatus 10,
For example, when a Co silicide electrode is formed by sputtering Co on a polysilicon gate electrode, a chip in which insulation failure has occurred in the gate oxide film often occurs on the wafer, particularly in the peripheral portion of the wafer. However, there has been a problem in improving the product yield.

Here, using a conventional magnetron sputtering apparatus 10, Co is sputtered on polysilicon of the gate electrode under the following sputtering conditions to form a Co film, and then RTA is performed to form Co silicide. After that, the result of testing the quality of the withstand voltage of the gate oxide film for each chip of the wafer is shown. In this test, a conventional magnetron sputtering apparatus 10 was used, as shown in FIG.
Co is sputtered on the polysilicon film 22 of the gate electrode formed on the gate electrode 0 to form a Co film 24, and then RTA
To form a Co silicide layer. FIG. 9 shows a state in which a Co film 24 is formed on the polysilicon film 22 of the gate electrode by sputtering. In FIG. 9, 26 is SiN
And 28 are gate oxide films. Sputtering conditions Chamber pressure: 5 to 15 mTorr Gas flow rate: Ar / 50 to 100 scc / m Sputter power: 1.5 kW However, in the Co sputtering using the conventional magnetron sputtering apparatus 10, as shown in FIG. Insufficient insulation occurs in the gate oxide film of the part of the chip, and the percentage of the good chips having a withstand voltage of the gate oxide film equal to or higher than a predetermined value with respect to the chip of the whole wafer, the so-called non-defective rate, is shown in FIG. As shown together with the result of Example 2, it was about 46%. In FIG. 11, a chip having a severe insulation defect in the gate oxide film is colored black, and a chip having a slight insulation failure is colored gray.

[0011]

However, in the above-mentioned conventional method for manufacturing a semiconductor device, after a gate polysilicon is formed, a refractory metal is sputter-deposited on the gate polysilicon. There is a problem that the gate electrode 305 is charged up by the generated charges, and the gate breakdown voltage is deteriorated.

A salicide process is an effective method for forming silicide only on the gate electrode and the diffusion layer. However, the underlying structure when sputtering a high melting point metal is such that the natural oxide film on the surface of the gate electrode 305 is The gate electrode 305 has been removed, and has already been doped with impurities, and has become a floating gate.

Therefore, at the moment when the shutter is opened from the discharge during the sputter discharge or during the standby and the sputter deposition is started on the wafer, an electric charge is generated in the gate electrode portion, and the electric charge flows through the gate insulating film 304. hand,
There is a problem that the gate breakdown voltage is deteriorated. This phenomenon becomes more conspicuous as the thickness of the gate insulating film 304 becomes thinner and more highly integrated, and becomes a serious problem as miniaturization progresses.

The present invention has been made in view of the above points,
In a method of manufacturing a semiconductor device in which a high-melting-point metal silicide layer is formed between insulating films selectively formed on a semiconductor substrate, a method of sputtering a high-melting-point metal under conditions that do not cause deterioration in gate breakdown voltage due to a sputtering device. It is intended to provide a manufacturing method.

Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a MOS field effect transistor capable of achieving high reliability and low resistance.

As described above, when a high melting point metal such as Co, Ti, Ni, or W is sputtered on a polysilicon film using a conventional magnetron sputtering apparatus to form a silicide, a gate oxide film is formed. However, there is a problem that the insulation properties of the metal are deteriorated. Therefore, a further object of the present invention is to form a high-melting-point metal silicide film on a gate electrode so that a high-melting-point metal can be sputtered on a polysilicon film by preventing deterioration of the withstand voltage of the gate oxide film. It is to provide a device.

[0017]

According to the present invention, a refractory metal is deposited on the entire surface of a silicon substrate on which a gate electrode of a semiconductor device is formed to form a refractory metal film. And forming a refractory metal silicide layer at the interface with the refractory metal film, the refractory metal film is magnetron-treated under the condition that the electric charge Q reaching the gate electrode is 5 C / cm ² or less. The sputter deposition is performed by a sputtering apparatus.

Here, the above magnetron sputtering apparatus has a configuration in which the size of the target is set such that the high-melting-point metal is sputter-deposited such that the maximum plasma density region is outside the silicon substrate.

Further, the above magnetron sputtering apparatus comprises:
A configuration in which a high-melting-point metal is sputter-deposited with the holder magnet on the silicon substrate side covering the side surface of the wafer having the silicon substrate, and the region having the maximum plasma density is located above the wafer having the silicon substrate, A configuration in which the strength of the holder magnet is set and the high melting point metal is deposited by sputtering may be used.

Further, the above-mentioned magnetron sputtering apparatus may have a structure in which a high-melting-point metal is sputter-deposited in a space between a target and a wafer having a silicon substrate with a conductive collimating plate inserted. It is desirable that the high melting point metal is any one of titanium, cobalt and nickel.

In the present invention, a high melting point metal is sputter deposited under the condition that the charge amount Q reaching the gate electrode is 5 C / cm ² or less, so that the gate withstand voltage does not deteriorate.

The operation of this will be described. FIG. 4 shows a wafer obtained by etching a natural oxide film using hydrofluoric acid, sputter-depositing titanium, and then wet-etching the deposited titanium with a mixed solution of aqueous ammonia and hydrogen peroxide without performing heat treatment. The non-defective rate of gate breakdown voltage is shown. As a comparison, a result measured without performing sputtering is also shown.

In the case where titanium is sputtered and wet-etched immediately, the initial withstand voltage of the gate is poor, and the gate withstand voltage is significantly deteriorated during the sputtering. The yield rate of the gate in this case is indicated by I in FIG. Thus, the non-defective rate is lower than the non-defective rate II when the titanium is not sputtered.

FIG. 5 shows the percentage of good gate breakdown voltage when a collimating plate is inserted between a wafer and a target during sputter deposition, the percentage of good gate withstand voltage when sputtering deposition is performed without inserting a collimating plate, and the case where sputter deposition is not performed. And the gate breakdown voltage non-defective rate is shown in comparison. Also in this case, FIG.
In the same manner as in the above, wet etching is performed without performing heat treatment after sputtering, and measurement is performed.

In sputter deposition, the non-defective gate breakdown voltage ratio when the collimating plate is inserted between the wafer and the target is 100%, as shown by IV in FIG. As shown by III in the figure, the gate breakdown voltage is not degraded due to sputtering, and a good gate breakdown voltage is obtained, as compared with the gate breakdown voltage non-defective rate when titanium is sputtered and immediately wet etched. I understand.

In this case, since the collimating plate is inserted between the wafer and the target, the charges that would reach the wafer flow into the collimating plate, and the charge-up of the gate electrode is suppressed, and This is because sputter deposition can be performed so that the amount of charge Q that reaches the target is 5 C / cm ² or less.

Usually, the collimated sputtering is for improving the coverage of the sputtered film by depositing titanium at the bottom of the contact hole with good anisotropy. However, in this case, it is not necessary to use an existing collimating plate, and an electrically grounded plate such as a mesh plate may be inserted between the wafer and the target. A result similar to the obtained result is obtained.

As described above, when the refractory metal is sputter-deposited on the floating gate electrode having the salicide structure, a method of controlling the amount of charge reaching the wafer is to prevent unnecessary charge from being generated from the plasma. Or prevent the generated charge from reaching the wafer. Therefore, the gate breakdown voltage characteristics can be improved by combining the above two types or a combination thereof.

In order to realize a sputtering apparatus capable of achieving the above-described object of the present invention, the present inventor has found that, after research, the cause of insulation failure of a gate oxide film is that charged particles near a target are caused by wafers. It has been found that it reaches the surface, penetrates the polysilicon film and the gate oxide film of the gate electrode, and penetrates the silicon substrate. That is, it is speculated that the cause of the deterioration of the withstand voltage of the gate oxide film is caused by an increase in the collision probability of charged particles flying from the high charged particle density region existing near the plasma (on the wafer side) and colliding with the wafer. did. As is apparent from the erosion measurement of the target, the region where the plasma density is high is more concentrated in the peripheral direction than in the center in the diameter direction of the target. The region with high plasma density is located very close to the target when viewed from the target toward the wafer, but the region with high charged particle density is considered to be located on the wafer side of the plasma region. Can be Therefore, in order to prevent charged particles from flying on the wafer and colliding, a collimator plate is placed at a position close to the target and slightly away from the plasma area to the wafer side. With the idea of capturing the particles by a collimating plate, and further studying the positional relationship between the target and the collimating plate, the present invention was completed.

In order to achieve the above-mentioned further object of the present invention, based on the above findings, a sputtering apparatus according to the present invention comprises a target held by a target holder and a target facing the target. A wafer holder for holding a wafer on which metal is to be deposited,
In a sputtering device that sputters a target metal onto a wafer, a collimator plate made of a conductor having a large number of through-holes penetrating from the target toward the wafer is interposed between the target holder and the wafer holder in a grounded state. It is characterized by having

Further, as can be seen from the results of Experimental Examples 1 and 2 described later, the effect of the interposition of the collimating plate greatly differs depending on the position of the collimating plate with respect to the target. Has a critical significance with respect to its position relative to the target. Accordingly, in a preferred embodiment of the present invention, the collimator plate, be arranged at intervals of a first distance D ₁ second interval D ₂ or more ranges in the following with respect to the target holder, more preferably, The sputtering apparatus includes position adjusting means for positioning and holding the collimating plate within the above-mentioned range.
The first distance D ₁ and the second distance D ₂ are different depending on the structure of the sputtering apparatus and the sputtering conditions, but practically, the first distance D ₁ is 50 mm for the reason described later. Yes, the second distance D ₂ is 24 mm
It is.

It is preferable that the ratio of the sum of the opening areas of all the through holes to the surface area of the collimating plate, that is, the opening ratio be higher.
Further, although there is no limitation on the shape and size of the through hole of the collimating plate, the collimating plate is preferably a mesh plate having an aspect ratio of the through hole of 0.7 or more and 1.3 or less.

The present invention can be applied to any type and type of sputtering apparatus without limitation as long as the sputtering apparatus performs sputtering by glow discharge. For example, the present invention can be applied to a DC sputtering apparatus, a high frequency (RF) sputtering apparatus and a magnetron sputtering apparatus. it can.

When the collimating plate is interposed between the target and the wafer, the degree of the initial withstand voltage deterioration of the gate insulating film is considered to depend on the distance between the collimating plate and the target holder, the aspect ratio of the collimating plate, and the sputtering rate. .

When the collimating plate is not interposed, the probability that charged particles flying from the high charged particle region directly collide with the wafer is higher in the peripheral portion of the wafer, and therefore, the degree of deterioration of the initial breakdown voltage of the gate insulating film in the peripheral portion of the wafer is high. Is more intense than in the center of the wafer. For example, in the case of a magnetron sputtering apparatus, the shape and dimensions of the cathode magnet differ for each magnetron sputtering apparatus. As a result, the plasma density distribution in the target diameter direction and, consequently, the distribution of charged particles are different. However, as a general tendency, the deterioration is more severe in the peripheral portion of the wafer. Also, when no collimating plate is interposed, an increase in leakage current between the gate, source, and drain was measured at the center of the wafer as compared with the case where the collimating plate was interposed, and the gate oxide film was damaged during sputtering. Is clearly given.

The distance between the collimating plate and the target holder (distance between T / C) is a factor that should be determined so that the probability of capturing charged particles directly flying from the high charged particle density region is high. As described above, the interposition effect of the collimating plate greatly differs depending on the position of the collimating plate with respect to the target, and the position of the collimating plate with respect to the target has a critical significance. For example, when the T / C distance is 50 mm or more, the effect of the collimating plate is significantly reduced. If the distance between T / C is shortened and the angle of incidence of the charged particles on the collimator plate is increased, the probability of the charged particles being captured by the collimator plate can be increased, so that the charged particles fly and collide with the gate oxide film. Deterioration of the withstand voltage can be effectively prevented. However, conversely, T / C
If the distance is too short, since the collimating plate comes into contact with the high-density plasma existing region, the collimating plate may be sputtered and shaved, which is extremely dangerous.
From this point of view, the T / C distance is the shortest allowable distance (for example, 2
4mm) is set.

Further, increasing the aspect ratio of the collimating plate increases the probability of capturing charged particles from the high charged particle density region described above, and is therefore effective in preventing the initial dielectric breakdown voltage of the gate oxide film from deteriorating. . However, if the aspect ratio is too large, the sputtered metal is captured, and the sputter rate is reduced.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. First Embodiment of a Method for Manufacturing a Semiconductor Device According to the Present Invention FIG. 1 is a sectional view of an element in each step of a first embodiment of a method for manufacturing a semiconductor device according to the present invention. First, FIG.
As shown in FIG.
Is formed by a known method. Next, a field oxide film 103 is formed as a field insulating film on the surface of the P-type silicon substrate 101 by a selective oxidation method. In the active region surrounded by the field oxide film 103, a gate insulating film 104 such as a silicon oxide film and polycrystalline silicon are sequentially grown, and phosphorus is doped into the polycrystalline silicon by a known method to thereby reduce the electrical resistance of the polycrystalline silicon. To reduce

Next, the gate electrode 105 is formed by patterning the polycrystalline silicon by photolithography and dry etching, which are known methods, as shown in FIG. Next, a low concentration N-type impurity diffusion layer 113 is formed by photolithography and ion implantation.
And a low concentration P-type impurity diffusion layer 114 is formed. Next, a sidewall 106 made of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 105 by using a known CVD technique and an etching technique.

Next, as shown in FIG. 1B, the source / drain region 107 of the N-type impurity diffusion layer and the source / drain region 108 of the P-type impurity diffusion layer are formed by photolithography and ion implantation. I do. Thus, L
N-type source / drain regions 107 and P-type source / drain regions 108 are formed as a DD structure.

Next, the surface of the polycrystalline silicon which is the gate electrode 105 and the natural oxide film on the surface of the semiconductor substrate are removed,
For example, the charge amount Q reaching the gate electrode 105 is 5 C / c.
A titanium film 109 is formed by sputtering titanium, which is a refractory metal, by using a magnetron sputtering apparatus having a condition of not more than m ² . At this time, in the magnetron sputtering apparatus used, for example, a net-like conductor such as a collimator plate is inserted between the wafer and the target to perform sputtering.

FIG. 6 is a block diagram showing an example of a magnetron sputtering apparatus used in the first embodiment of the method of the present invention. In the magnetron sputtering apparatus shown in FIG. 6A, a wafer 63 is placed on a wafer holder 62 in a chamber 61, and a cathode magnet 64 and a target 65 are arranged at positions opposed to and separated from the wafer 63. A collimating plate 66 is arranged at a spatial position between them.

A commonly used collimating plate enhances the anisotropy of sputtered particles and has an aspect ratio of a net of about 1. The collimating plate 66 used in this sputtering apparatus is shown in FIG. As shown in the top view, the structure is made of a net-like conductor. The collimating plate 6
In the method 6, the conductive plate may be simply inserted between the wafer and the target. The aspect ratio, size and shape of the collimating plate 66 are arbitrary, and the collimating plate 66 does not need to cover the entire surface of the wafer 63. It is only necessary to cover only the region where the intensity distribution is high or the charge is easily generated.

Further, the shape and shape of the collimating plate 66 may be adjusted by a sputtering device. The reticulated conductor of the collimating plate 66 may be used as a ground potential, but the effect is further enhanced by applying a potential corresponding to the plasma state. Further, in the first embodiment, the example in which the titanium film 109 is deposited is shown. However, the same effect can be obtained by depositing another refractory metal such as cobalt or nickel. It is.

Next, as shown in FIG. 1C, the surface of the gate electrode 105 made of polycrystalline silicon and the source / drain regions 107 and 108 are subjected to rapid thermal processing (RTA) at 700 ° C. or less in a nitriding atmosphere. A titanium silicide layer 110 having a C49 type structure is formed only at the interface of the titanium film 109 that comes into contact with the titanium film 109. At this time, the titanium film 109 in contact with the field oxide film 103 and the sidewall 106 and a part of the titanium film 109 on the semiconductor substrate are nitrided to form a titanium nitride film 111.

Next, as shown in FIG. 1 (d), the unreacted titanium and the titanium nitride film 1 are selectively wet-etched with a mixed solution of ammonia water and hydrogen peroxide solution or the like.
Remove only 11 Next, RTA at a higher temperature (800 ° C. or higher) than the above-mentioned RTA is performed, and C having a lower electric resistivity than the above-mentioned titanium silicide layer 110 having the C49 type structure is formed.
A titanium silicide 112 having a 54-type structure is formed.

The MOS field-effect transistor manufactured in this manner does not cause deterioration of the gate breakdown voltage due to sputtering, and has a good gate breakdown voltage. This is because, since the collimating plate 66 is inserted between the wafer 63 and the target 65, charges that should reach the wafer 63 flow to the collimating plate 66, and the charge-up of the gate electrode 105 is suppressed.

When a refractory metal is sputter-deposited on a floating gate electrode having a salicide structure as described above, a method of controlling the amount of charge reaching the wafer is to prevent generated charge from reaching the wafer. This can improve the gate breakdown voltage characteristics. Second Embodiment of Method for Manufacturing Semiconductor Device According to the Present Invention As shown in FIG. 2A, an N well 202 is formed on a P-type silicon substrate 201 by a known method. Next, a field oxide film 203 is formed as a field insulating film on the surface of the P-type silicon substrate 201 by a selective oxidation method. In the active region surrounded by the field oxide film 203, a gate insulating film 204 such as a silicon oxide film and polycrystalline silicon are sequentially grown, and phosphorus is doped into the polycrystalline silicon by a known method to form an electric resistance of the polycrystalline silicon. To reduce
Next, the polycrystalline silicon is patterned by a known method such as photolithography and dry etching to form a gate electrode 205 as shown in FIG.

Next, a low concentration N-type impurity diffusion layer 213 and a low concentration P-type impurity diffusion layer 214 are formed by photolithography and ion implantation. Next, a side wall 206 made of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 205 by a known CV.
It is formed using a D technique and an etching technique.

Next, as shown in FIG. 2B, a source / drain region 207 of an N-type impurity diffusion layer and a source / drain region 208 of a P-type impurity diffusion layer are formed by photolithography and ion implantation. . Next, a magnetron sputtering apparatus is used in which the surface of the polycrystalline silicon which is the gate electrode 205 and the natural oxide film on the surface of the semiconductor substrate are removed and, for example, the charge amount Q reaching the gate electrode becomes 5 C / cm ² or less. A titanium film 209 is formed by sputtering titanium as a high melting point metal.

FIG. 7B, FIG. 7D or FIG. 7E shows the configuration of the magnetron sputtering apparatus used at this time.
As a conventional sputtering apparatus, as shown in FIG. 7A, a wafer 73 is placed on a wafer holder 72 in a chamber 71, and a target 74 is arranged at a position facing and away from the wafer 73, and there is no holder magnet. Although a sputtering apparatus having a structure is known, according to the detailed experimental results of the present inventors, in the region where the plasma density of the plasma 75 is the highest, the gate initial breakdown voltage deterioration was most observed.

On the other hand, in the magnetron sputtering apparatus shown in FIG. 7B, in a magnetron sputtering apparatus having no holder magnet, the region where the plasma density of the plasma 77 is maximum is outside the substrate (wafer). This is a magnetron sputtering apparatus having a structure using a target 76 whose size is set, and the titanium film 20
In the case of depositing 9 by sputtering, electric charges generated from the plasma 77 can be prevented from reaching the wafer 73, so that good electric characteristics were obtained.

The magnetron sputtering apparatus shown in FIGS. 7A and 7B has a structure in which the plasmas 75 and 77 are in direct contact with the wafer 73, whereas the conventional magnetron sputtering apparatus has the structure shown in FIG. As shown in c), a magnetron sputtering apparatus having a structure in which a holder magnet 79 is mounted in a state where the plasma 80 does not contact the wafer 73 is also known. That is, in this conventional magnetron sputtering apparatus, the wafer 73 is placed on the wafer holder 72 via the holder magnet 79 in the chamber 71, and the plasma 80 from the target 74 does not contact the wafer 73.

However, even in this conventional magnetron sputtering apparatus, the charge (Ar ⁺ or electron) generated from the plasma reaches the wafer 73, which also causes a gate initial breakdown voltage defect. In the peripheral portion of the wafer 73, a deteriorated portion of the gate initial withstand voltage was observed.

In this embodiment, the titanium film 209 is formed by using a magnetron sputtering apparatus having a structure shown in FIG. 7D or FIG. 7E as a magnetron sputtering apparatus having a structure having the holder magnet. Sputter deposition is performed under such a condition that the charge amount Q reaching the gate electrode is 5 C / cm ² or less. The magnetron sputtering apparatus shown in FIG. 7D is characterized in that the holder magnet 81 attached for stabilizing the plasma is shaped so as to cover the side surface of the wafer 73, thereby generating the plasma 82. By trapping the generated charges by the magnetic field of the holder magnet 81, the gate initial withstand voltage failure can be suppressed.

In the magnetron sputtering apparatus shown in FIG. 7E, the magnetic field strength of the holder magnet 83 attached for stabilizing the plasma is adjusted so that the plasma maximum region of the plasma 84 is located above the wafer 83. Is characterized in that the charge generated from the plasma 84 is trapped by the magnetic field of the holder magnet 83, whereby the gate initial breakdown voltage defect can be suppressed.

In the case of the magnetron sputtering apparatus having the structure shown in FIG. 7D or FIG. 7E, the electric charges are trapped by the magnetic field generated from the holder magnets 81 and 83, so that the peripheral parts also deteriorate. Good electrical characteristics were obtained without any spots. Actually, the degree of deterioration of the initial withstand voltage of the gate changes depending on the structure of the magnetron sputtering apparatus. Therefore, optimization is made by combining the above-mentioned method of changing the maximum plasma area and the method of trapping by the magnetic field generated by the holder magnet on the wafer side. It is also conceivable.

Although the second embodiment shows an example in which titanium is deposited, the same effect can be obtained by depositing another refractory metal such as cobalt or nickel. is there.

Returning to FIG. 2 again, FIG.
As shown in (c), a rapid thermal treatment (RTA) at 700 ° C. or lower is performed in a nitrogen atmosphere to form a titanium film 109 which is in contact with the surface of the gate electrode 205 and the source / drain regions 107 and 108 which are polycrystalline silicon. A titanium silicide 210 having a C49 type structure is formed only at the interface. At this time, as shown in FIG. 2C, the titanium film 209 in contact with the field oxide film 203 and the sidewall 206 and a part of the titanium film 209 on the semiconductor substrate are nitrided to form a titanium nitride film 211. .

Next, as shown in FIG. 2D, wet etching is selectively performed using a mixed solution of ammonia water and hydrogen peroxide solution to remove only the unreacted titanium and the titanium nitride film 211. Next, RTA at a higher temperature (800 ° C. or higher) than the above-described RTA is performed, and C having a lower electric resistivity than the titanium silicide 210 having the C49 type structure is used.
A 54-type structure titanium silicide 212 is formed.

In this embodiment, by making the configuration of the magnetron sputtering apparatus as shown in FIG. 7B, FIG. 7D or FIG. 7E, the charge generated from the plasma does not reach the wafer, and the gate initial state is reduced. Withstand voltage deterioration is suppressed. Further, in the magnetron sputtering apparatus used in the first embodiment, since a conductive net-like collimating plate is inserted, the sputtered film is deposited on the conductive net-like collimating plate, so that the sputtered film is deposited on the wafer. The collimator plate needs to be replaced due to a problem such as a decrease in sputter rate or particles, but the magnetron sputtering device used in the second embodiment does not include a conductor mesh collimator plate. Therefore, there is an advantage that it is not necessary to replace the collimating plate, and it is easy to stably maintain the apparatus.

In the first and second embodiments, the method of forming silicide on the gate and the diffusion layer at the same time has been described. However, the polycide gate (WSix / Pol
When silicide is formed on a diffusion layer by sputtering a refractory metal on a floating gate such as y-Si), poly-tamel gate (W / WNx / Poly-Si), or metal gate (W / SiO ₂ ) It goes without saying that the present invention can also be applied to

Embodiment of the Sputtering Apparatus According to the Present Invention This embodiment is an example of an embodiment in which the sputtering apparatus according to the present invention is applied to a magnetron sputtering apparatus.
FIG. 10A is a schematic cross-sectional view showing the configuration of the magnetron sputtering apparatus of the present embodiment, FIG. 10B is a plan view of a collimator plate, and FIG. 10C is a side view of the collimator plate. 10, the same components and parts as those in FIG. 8 are denoted by the same reference numerals. As shown in FIG. 10, the magnetron sputtering apparatus 30 of the present embodiment is basically similar to the aforementioned FIG.
Has the same configuration as that of the magnetron sputtering apparatus shown in FIG. 1, and includes a wafer holder 14 for mounting a wafer W in a sputtering chamber 12, and a cathode magnet for holding a target T at a position separated from and facing the wafer W. 16, a net-like collimating plate 32 provided between the wafer holder 14 and the cathode magnet 16.
And

The collimating plate 32 is provided to increase the anisotropy of the sputtered particles and to capture the charged particles, and as shown in FIG. 10B, a conductive hexagonal continuous mesh is formed. It is configured as a mesh-like plate made of a body and is grounded. A regular hexagonal mesh or hole of the collimating plate 32 penetrates from the target T toward the wafer W,
The aspect ratio of the mesh or hole is 1. That is, the thickness t of the collimating plate (see FIG. 10C) and the diameter D of the mesh or hole.
(Maximum diameter of mesh or hole, see FIG. 10B). The collimating plate 32 is provided with the position adjusting mechanism 3.
4, the distance from the surface of the collimator plate 32 to the target holding surface of the cathode magnet 16 (T / C distance,
In FIG. 10 (a), indicated by L ₁₎ is changed, and is held in that position. The position adjustment mechanism 34
This is a known mechanism, and the collimator plate 32 is freely moved up and down by a driving device such as a hydraulic cylinder or an air cylinder. The size of the collimator plate 32 does not need to cover the entire surface of the wafer W, and it is sufficient that the collimator plate 32 covers only a region where the plasma intensity distribution is high or charged particles are easily generated.

EXPERIMENTAL EXAMPLE 1 A sputtering experiment was conducted using an experimental apparatus having the same configuration as the magnetron sputtering apparatus 30 of the present embodiment, in which a collimating plate was attached to Model No. I-1060 manufactured by Anelva Co., Ltd. The specifications of the experimental device are briefly described below. Target thickness: 3 mm Diameter: 12 inches Wafer holder Wafer dimensions: 6 inch diameter or 8 inch diameter Chuck method: Clamp chuck Collimator plate Hole diameter D: 23 mm Thickness t: 23 mm Hole shape: Regular hexagonal continuous shape Aspect ratio: 1 Material: stainless steel

In the above experimental apparatus, the cathode magnet 1
6, the distance between the target holding surface and the surface of the wafer W (T
/ S distance, in FIG. 10 (a), the displayed L ₂₎ 103
mm, and the distance L ₁ between the target holding surface of the cathode magnet 16 and the opposing surface of the collimating plate 32 is set to 34.
mm, the sputtering power applied between the wafer holder 14 and the cathode magnet 16 was set to 1.0 kW,
Co was sputtered under the following sputtering conditions while changing the power to 1.5 kW and 2.0 kW, and a Co film having a thickness of 100 ° was formed on the polysilicon film shown in FIG. Sputtering conditions Holder temperature: room temperature Chamber pressure: 3 to 8 mTorr Next, the quality of the dielectric breakdown voltage of the gate oxide film was checked for each chip, and as shown in FIGS. The chips were colored black, and the chips with slightly poor insulation were colored gray.

Experimental Example 2 Using the same experimental apparatus as in Experimental Example 1, the cathode magnet 1
Distance L ₂ between the target holding surface 6 and the surface of the wafer W
Is adjusted to 113 mm, and the distance L between the target holding surface of the cathode magnet 16 and the opposing surface of the collimator plate 32 is adjusted.
₁ for 24mm, 29mm, 34mm, 39mm, 44mm and 56
instead changed to mm, and a sputtering power to be applied between the wafer holder 14 and the cathode magnet 16 at the same L ₁ 1.0 kW, the 1.5kW and 2.0 kW, a total of 1
Co sputtering was performed eight times under mutually different conditions. Other conditions are the same as the sputtering conditions as in Experimental Example 1. Next, the quality of the withstand voltage of the gate oxide film is checked for each chip, and as shown in FIGS. 13A to 13C to FIGS. Black and slightly insulated chips were colored gray.

As shown in FIG. 19, the experimental results of Experimental Examples 1 and 2 were totaled using the sputtering power as a parameter. In FIG. 19, L _{1 is} plotted on the horizontal axis, and the yield rate (%) of the gate oxide film is plotted on the vertical axis. As can be seen from Figure 19, regardless of the sputtering power, the L ₁ is 39mm or less, the yield rate reaches almost 100%, whereas, by L ₁ is more than 44mm, the
The non-defective rate drops sharply to 60% or less. In other words, regarding the yield rate of the gate oxide film, that is, the effect of the interposition of the collimating plate 32, it is found that a clear critical position of the collimating plate 32 with respect to the target or the cathode magnet exists between 39 mm and 44 mm. The bar graph at the left end of FIG.
A numerical value of the yield rate when not interposed the collimator plate is approximately the same as the non-defective rate when L ₁ is 56 mm.

Experimental Example 3 Using the same experimental apparatus as in Experimental Example 1, the distance L ₁ between the collimator plate and the cathode magnet was set to 29 mm, and the distance L ₂ between the cathode magnet and the wafer holder was set to 68 mm. Under sputtering power (k
The relationship between W) and the yield rate of the gate oxide film was examined, and the results are shown in FIG. Also, for comparison, sputtering was performed using a magnetron sputtering apparatus having the same configuration as the experimental apparatus except that no collimating plate was provided,
The results are also shown in FIG. Sputtering conditions Chamber pressure: 8 to 10 mTorr Gas flow rate: 80 to 100 scc / m Sputter power: 1.5 kW As can be seen from FIG. 20, magnetron sputtering without a collimating plate by providing a collimating plate with the distance relationship specified in the present invention. Compared with the apparatus, the magnetron sputtering apparatus of the present embodiment has a very low dependency of the yield rate of the gate oxide film on the sputtering power.

Experimental Example 4 Using the same experimental apparatus as in Experimental Example 1, the distance L ₁ between the collimator plate and the cathode magnet was set to 29 mm, and the distance L ₂ between the cathode magnet and the wafer holder was set to 68 mm. The relationship between the sputter rate (Å / sec) and the yield rate of the gate oxide film was examined below, and the results are shown in FIG. For comparison, sputtering was performed using a magnetron sputtering apparatus having the same configuration of this embodiment except that no collimating plate was provided, and the results are also shown in FIG. Sputtering conditions Chamber pressure: 8 to 10 mTorr Gas flow rate: 80 to 100 scc / m Sputter power: 1.5 kW As can be seen from FIG. 21, magnetron sputtering without a collimating plate is provided by providing a collimating plate with the distance relationship specified in the present invention. Compared with the apparatus, the magnetron sputtering apparatus according to the present embodiment has a low yield rate dependency on the sputtering rate.

By increasing the sputter rate, the conductive metal (or metal silicide) quickly covers the wafer surface, so that the charged particles travel in the horizontal direction of the wafer rather than in the depth direction of the gate. In addition, the initial withstand voltage deterioration probability of the gate oxide film is reduced. Therefore, increasing the sputtering rate is effective in preventing the initial withstand voltage of the gate oxide film from deteriorating as shown in FIG. However, if the sputtering rate is too high, the in-plane film thickness distribution difference of the wafer increases, and there is a concern that the amount of silicidation reaction during high-temperature sputtering may decrease. Not preferred. When the sputter rate was increased by setting the sputtering power of Experimental Example 3 to 2.6 kW, the non-defective rate was 98% even when the distance of the collimating plate to the cathode holding surface of the cathode magnet 16 was 50 mm. Was done. In addition, even if an attempt is made to prevent the deterioration of the withstand voltage of the gate oxide film by increasing the sputter rate, immediately after the start of the sputtering, the conductive metal film for blocking the flying of the charged particles to the gate is not formed. Therefore, the effect of preventing the initial breakdown voltage of the gate oxide film from deteriorating is lower than when the collimating plate is interposed. Also, the results from different endurances (AMAT ENDURA) of equipment manufacturers,
Satisfactory results were obtained even at 46.5 mm.

Experimental Example 5 Using the magnetron sputtering apparatus of this embodiment used in Experimental Examples 1 and 2, the distance L _{1 of the} collimating plate to the cathode magnet was set to 34 mm, and the distance L ₂ between the cathode magnet and the wafer holder was determined. Set to 103mm,
The applied voltage is fixed at 1.5 kW and the gas pressure is 5 mTor
At r, 8 mmTorr, 10 mTorr, and 15 mTorr, Co sputtering was performed, and the gas pressure dependency of the yield rate of the gate oxide film was examined. as a result,
At a gas pressure of 5 mTorr, 8 mmTorr, 10 mTorr, and 15 mTorr, the yield rate of the gate oxide film is 100%, respectively.
Thus, in the magnetron sputtering apparatus provided with the collimating plate, it was found that the yield rate of the gate oxide film did not depend on the gas pressure.

From the results of Experimental Examples 1 to 5 above,
The sputtering apparatus according to the present embodiment includes a cathode magnet 1
By disposing the collimating plate 32 within a range of 24 mm or more and 50 mm or less with respect to the cathode holding surface of No. 6, when the high melting point metal silicide film is formed on the gate electrode, deterioration of the dielectric strength of the gate oxide film is prevented. Thus, it has been proved that the sputtering apparatus can sputter a high melting point metal on a polysilicon film. In addition, the sputtering apparatus of the present embodiment has low sputter power dependence, sputter rate dependence, and gas pressure dependence with respect to the yield rate of the gate oxide film, and can set a wide range of sputtering conditions.

[0074]

As described above, according to the present invention,
In a method of manufacturing a semiconductor device in which a high-melting-point metal silicide layer is formed between insulating films selectively formed on a semiconductor substrate, a high-melting-point metal is sputter-deposited under conditions that do not cause deterioration in gate withstand voltage. Even if a MOS field effect transistor (MOSFET) for reducing the resistance by forming a melting point metal silicide layer is miniaturized by thinning the gate insulating film or increasing the degree of integration, it can be manufactured with higher reliability. .

According to the sputtering apparatus of the present invention, a collimator plate made of a conductor having a large number of through holes penetrating from the target toward the wafer is interposed between the target holder and the wafer holder. by preferably, by placing the collimator plate at intervals of the second distance D ₂ or more ranges in the first interval D ₁ or less with respect to the target holder, a refractory metal silicide film on the gate electrode When forming, a sputtering apparatus capable of sputtering a high melting point metal on a polysilicon film without realizing deterioration of the dielectric strength of the gate oxide film is realized. Further, the sputtering apparatus according to the present invention has low sputter power dependence, sputter rate dependence, and gas pressure dependence with respect to the yield rate of the gate oxide film, and can set sputtering conditions in a wide range.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an element in each step of a first embodiment of the present invention.

FIG. 2 is a sectional view of an element in each step of a second embodiment of the present invention.

FIG. 3 is a sectional view of an element in each step of an example of a conventional method.

FIG. 4 is a diagram showing a non-defective product ratio and the like of a gate withstand voltage when sputtering is performed under conventional sputtering conditions.

FIG. 5 is a diagram showing a non-defective product ratio and the like of gate withstand voltage characteristics when a collimating plate is inserted.

FIG. 6 is a configuration diagram of a sputtering apparatus used in the first embodiment of the present invention.

FIG. 7 is a configuration diagram of a sputtering apparatus of each example used in a second embodiment of the present invention and a conventional sputtering apparatus.

FIG. 8 is a schematic diagram showing a configuration of a conventional sputtering apparatus.

FIG. 9 is an explanatory diagram of silicidation.

FIG. 10A is a schematic diagram illustrating a configuration of a sputtering apparatus according to an embodiment, FIG. 10B is a plan view of a collimator plate, and FIG. 10C is a side view of the collimator plate.

FIG. 11 is a wafer map showing gate oxide film deterioration when sputtering is performed using a conventional sputtering apparatus.

FIGS. 12A to 12C are wafer maps showing gate oxide film deterioration when sputtering is performed under mutually different conditions using the sputtering apparatus of the present embodiment.

FIGS. 13A to 13C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.

FIGS. 14A to 14C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.

FIGS. 15A to 15C are wafer maps showing deterioration of a gate oxide film when sputtering is performed under mutually different conditions using the sputtering apparatus of the embodiment.

FIGS. 16A to 16C are wafer maps showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.

FIGS. 17A to 17C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.

FIGS. 17A to 17C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.

FIG. 19 shows an experimental example 1 in which sputtering power is used as a parameter.
6 is a graph summarizing the experimental results of the first and second experiments.

FIG. 20 is a graph showing the sputter power dependence of the yield rate.

FIG. 21 is a graph showing the sputter rate dependence of the yield rate.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Conventional sputtering apparatus 12 Sputter chamber 14 Wafer holder 16 Cathode magnet 20 Silicon substrate 22 Polysilicon film 24 Co film 26 Side wall 28 Gate oxide film 30 Sputter apparatus of embodiment 32 Collimating plate 34 Position adjusting mechanism 61, 71 Chamber 62, 72 Wafer holder 63, 73 Wafer 65, 74, 76 Target 66 Collimating plate 75, 77, 80, 82, 84 Plasma 79, 81, 83 Holder magnet 101, 201 P-type silicon substrate 102, 202 N well 103, 203 Field oxide film 104, 204 Gate insulating film 105, 205 Gate electrode 106, 206 Side wall 107, 207 N-type source / drain region 108, 208 P-type source / drain region 1 9 and 209 titanium film 110, 210 C49-type titanium silicide layer 111 and 211 of titanium silicide layers 113, 213 N-type impurity diffusion layers 114 and 214 P-type impurity diffusion layer of the titanium nitride film 112, 212 C54 type structure of structure

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/78 21/336 (72) Inventor Minoru Higuchi 7-1, Shiba 5-chome, Minato-ku, Tokyo Inside NEC Corporation

Claims (12)

[Claims] A refractory metal is deposited on the entire surface of a silicon substrate on which a gate electrode of a semiconductor device is formed to form a refractory metal film, and then heat-treated to form a refractory metal silicide at an interface with the refractory metal film. In a method of manufacturing a semiconductor device for forming a layer, the semiconductor is characterized in that the refractory metal film is sputter-deposited by a magnetron sputtering apparatus under a condition that a charge amount Q reaching the gate electrode is 5 C / cm ² or less. Device manufacturing method. 2. The magnetron sputtering apparatus according to claim 1, wherein a target size is set such that a maximum plasma density region is outside the silicon substrate, and the refractory metal film is sputter-deposited. Claim 1
The manufacturing method of the semiconductor device described in the above. 3. The magnetron sputtering apparatus according to claim 1, wherein the refractory metal is sputter-deposited with the holder magnet on the silicon substrate side covering a side surface of a wafer having the silicon substrate. Of manufacturing a semiconductor device. 4. The magnetron sputtering apparatus sets the strength of a holder magnet on the wafer side so that a region having a maximum plasma density is above a wafer having the silicon substrate, and sputter-deposits the refractory metal. 2. The method according to claim 1, wherein the semiconductor device has a configuration. 5. The magnetron sputtering apparatus is characterized in that the high-melting-point metal is sputter-deposited in a space between a target and a wafer having the silicon substrate, with a conductor collimating plate being inserted. 2. The method of manufacturing a semiconductor device according to claim 1, wherein 6. The method according to claim 5, wherein an upper surface of the collimating plate has a net shape. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said high melting point metal is any one of titanium, cobalt and nickel. 8. A sputtering apparatus comprising: a target held by a target holder; and a wafer holder holding a wafer on which a target metal is deposited so as to face the target, wherein the target metal is sputtered on the wafer. A sputtering apparatus characterized in that a collimating plate made of a conductor having a large number of through-holes penetrating from a target to a wafer is interposed between a holder and a wafer holder in a grounded state. 9. A collimating plate is attached to a target holder.
The first interval D ₁The second interval D below_TwoAbove range
9. An arrangement according to claim 8, wherein
On-board sputtering equipment. 10. The first distance D ₁ is 50 mm and the second distance D ₁ is 50 mm.
The distance D2 between the _two is 24 mm.
2. The sputtering apparatus according to 1. 11. The sputtering apparatus according to claim 9, further comprising a position adjusting means for positioning and holding the collimating plate within the range of the range. 12. The sputter according to claim 8, wherein the collimating plate is a net-like plate having an aspect ratio of a through hole of 0.7 or more and 1.3 or less. apparatus.