JP3569133B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS field effect transistor (MOSFET) that lowers resistance by siliciding the surface of a gate, a source, and a drain in a self-aligned manner.It relates to a manufacturing method.
[0002]
[Prior art]
As a conventional salicide process known as one of the methods for manufacturing a semiconductor device, there is a method disclosed in Japanese Patent Application Laid-Open No. 2-45923. This conventional method for manufacturing a semiconductor device will be described with reference to longitudinal sectional views shown in the order of steps of FIGS. 3A to 3D.
[0003]
As shown in FIG. 3A, an N well 302 is formed on a P-type silicon substrate 301 by a known method. Next, a field oxide film 303 is formed as a field insulating film on the surface of the P-type silicon substrate 301 by a selective oxidation method. In the active region surrounded by the field oxide film 303, a gate insulating film 304 such as a silicon oxide film and polycrystalline silicon are sequentially grown, and phosphorus is doped into the polycrystalline silicon by a known method to form an electric resistance of the polycrystalline silicon. Reduction. Next, the gate electrode 305 is formed by patterning the polycrystalline silicon by a known method such as photolithography and dry etching.
[0004]
Next, as shown in FIG. 3A, a low-concentration N-type impurity diffusion layer 313 and a low-concentration P-type impurity diffusion layer 314 are formed by photolithography and ion implantation. Next, a sidewall 306 made of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 305 by using a known chemical vapor deposition (CVD) technique and an etching technique.
[0005]
Next, as shown in FIG. 3B, an N-type impurity diffusion layer 307 and a P-type impurity diffusion layer 308 are formed by photolithography and ion implantation. Thus, an N-type source / drain region 307 and a P-type source / drain region 308 are formed as an LDD structure. Next, the natural oxide film on the surface of the polycrystalline silicon serving as the gate electrode and the surface of the semiconductor substrate is removed, and for example, a titanium film 309 is deposited by sputtering.
[0006]
Next, as shown in FIG. 3C, by performing a rapid thermal treatment (hereinafter, RTA) at 700 ° C. or less in a nitrogen atmosphere, only the titanium film 309 in contact with silicon is silicided to form a titanium silicide layer having a C49 type structure. Form 310. At this time, the titanium film 309 in contact with the field oxide film 303 and the sidewall 306 and a part of the titanium film on the semiconductor substrate are nitrided to form a titanium nitride film 311.
[0007]
Next, as shown in FIG. 3D, wet etching is selectively performed with a mixed solution of ammonia water and hydrogen peroxide water to remove only the unreacted titanium and the titanium nitride film 311. Next, RTA at a higher temperature (800 ° C. or higher) than the above-described RTA is performed to form a titanium silicide layer 312 having a C54 type structure having a lower electrical resistivity than the titanium silicide layer 310 having a C49 type structure.
[0008]
By using the salicide process described above, the surface portions of the polycrystalline silicon 305 and the N-type and P-type impurity diffusion layers 307 and 308 are silicided in a self-aligned manner, thereby lowering the resistance and increasing the speed of the device. Can be achieved. The salicide process has an advantage that it can be selectively silicided only in a necessary region.
[0009]
By the way, the conventional magnetron sputtering apparatus 10 generally includes, as shown in FIG. 8, a wafer holder 14 for mounting a wafer W in a sputtering chamber 12 and a position facing the wafer W at a distance from the wafer holder 14. And a cathode magnet 16 for holding the target T.
For example, when Co is sputtered on a polysilicon gate electrode using a conventional magnetron sputtering apparatus 10 to form a Co silicide electrode, a chip in which insulation failure has occurred in the gate oxide film occurs on the wafer, In particular, it often occurs in the peripheral portion of the wafer, which has been a problem in improving the product yield.
[0010]
Here, using a conventional magnetron sputtering apparatus 10, Co is sputtered on the polysilicon of the gate electrode under the following sputtering conditions to form a Co film, and then RTA is performed to perform Co silicidation. The results of testing whether the dielectric strength of the oxide film is good for each chip of the wafer are shown.
In this test, a Co film 24 was formed by sputtering Co on a polysilicon film 22 of a gate electrode formed on a silicon substrate 20 using a conventional magnetron sputtering apparatus 10 as shown in FIG. Then, RTA is performed to form a Co silicide layer. FIG. 9 shows a state in which a Co film 24 is formed on the polysilicon film 22 of the gate electrode by sputtering. In FIG. 9, 26 is a sidewall made of SiN or the like, and 28 is a gate oxide film.
Sputtering conditions
Chamber pressure: 5 to 15 mTorr
Gas flow rate: Ar / 50-100 scc / m
Sputter power: 1.5kW
However, in the case of Co sputtering using the conventional magnetron sputtering apparatus 10, as shown in FIG. 11, insulation failure occurs particularly in the gate oxide film of the chip around the wafer, and the withstand voltage of the gate oxide film becomes a predetermined value. The percentage of the above good chips with respect to the chips of the whole wafer, that is, the so-called non-defective rate, was about 46% as shown in FIG. 19 together with the results of Experimental Examples 1 and 2.
In FIG. 11, a chip having a severe insulation defect in the gate oxide film is colored black, and a chip having a slight insulation failure is colored gray.
[0011]
[Problems to be solved by the invention]
However, in the above-described conventional method of manufacturing a semiconductor device, after a gate polysilicon is formed, a refractory metal is sputter-deposited on the gate polysilicon, and at that time, the gate electrode 305 is charged up by charges generated from the plasma. However, there is a problem that the gate breakdown voltage is deteriorated.
[0012]
As a method of forming silicide only on the gate electrode and the diffusion layer, a salicide process is an effective method. However, a spontaneous oxide film on the surface of the gate electrode 305 is removed when the refractory metal is sputtered. As a result, the gate electrode 305 is already doped with impurities and serves as a floating gate.
[0013]
Therefore, at the time of sputtering, particularly when the shutter is opened from the discharge during sputter discharge or standby and the sputter deposition is started on the wafer, electric charges are generated in the gate electrode portion, and the electric charges flow through the gate insulating film 304 and the gate There is a problem that the breakdown voltage is deteriorated. This phenomenon becomes more conspicuous as the thickness of the gate insulating film 304 becomes thinner and more highly integrated, and becomes a serious problem as miniaturization progresses.
[0014]
The present invention has been made in view of the above points. In a method of manufacturing a semiconductor device in which a refractory metal silicide layer is formed between insulating films selectively formed on a semiconductor substrate, deterioration of a gate withstand voltage due to a sputtering device is reduced. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a refractory metal is sputtered under conditions that do not occur.
[0015]
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a MOS field effect transistor capable of achieving high reliability and low resistance.
[0016]
Also, as described above, when a high melting point metal such as Co, Ti, Ni, or W is sputtered on a polysilicon film using a conventional magnetron sputtering apparatus, silicidation is performed. However, there was a problem that was reduced. Therefore, a further object of the present invention is to form a high-melting metal silicide film on a gate electrode so that a high-melting metal can be sputtered on a polysilicon film so as not to cause deterioration of the withstand voltage of a gate oxide film. Semiconductor deviceProduction methodIt is to provide.
[0017]
[Means for Solving the Problems]
In order to achieve the further object of the present invention, a method of manufacturing a semiconductor device according to the present invention includes a method of manufacturing a semiconductor device.PolysiliconA refractory metal is deposited on the entire surface of the silicon substrate on which the gate electrode is formed by a magnetron sputtering apparatus to form a refractory metal film, and then heat-treated to form a refractory metal silicide layer at the interface with the refractory metal film. In the method for manufacturing a semiconductor device,The charge amount Q reaching the gate electrode is 5 C / cm ^Two Under the following conditions, the refractory metal film was sputter-deposited by a magnetron sputtering apparatus so that the gate withstand voltage of a gate insulating film formed between the silicon substrate and the gate electrode was not deteriorated.It is characterized by:
[0018]
Here, the above-mentioned magnetron sputtering apparatus has a configuration in which the size of the target is set so that the high-melting-point metal is sputter-deposited such that the maximum plasma density region is outside the silicon substrate.
[0019]
Further, the magnetron sputtering apparatus may have a configuration in which a high melting point metal is sputter-deposited with the holder magnet on the silicon substrate side covering the side surface of the wafer having the silicon substrate, and a region where the plasma density is maximum is above the wafer having the silicon substrate. In such a case, the strength of the holder magnet on the wafer side is set, and a high melting point metal is sputter-deposited.
[0020]
Further, the above-mentioned magnetron sputtering apparatus may have a configuration in which a high-melting-point metal is sputter-deposited in a space between a target and a wafer having a silicon substrate while a collimator plate of a conductor is inserted. The high melting point metal is desirably one of titanium, cobalt and nickel.
[0021]
In the present invention, the charge amount Q reaching the gate electrode is 5 C / cm.²The high-melting-point metal is sputter-deposited under the following conditions to prevent the gate breakdown voltage from deteriorating.
[0022]
The operation of this will be described. FIG. 4 shows a wafer obtained by etching a native oxide film using hydrofluoric acid, depositing titanium by sputtering, and then wet-etching the deposited titanium with a mixed solution of aqueous ammonia and hydrogen peroxide without performing heat treatment. The non-defective rate of gate breakdown voltage is shown. As a comparison, a result measured without performing sputtering is also shown.
[0023]
If titanium is sputtered and wet-etched immediately, the initial withstand voltage of the gate is poor, and the gate withstand voltage is significantly degraded during the sputtering. The non-defective rate is lower than the non-defective rate II in the case where titanium is not sputtered.
[0024]
FIG. 5 shows the good gate breakdown voltage ratio when a collimating plate is inserted between the wafer and the target during sputter deposition, the good gate breakdown voltage ratio when sputtering is deposited without inserting a collimating plate, and the gate breakdown voltage when no sputter deposition is performed. The non-defective rate is shown in comparison. In this case as well, measurement is performed by wet etching without performing heat treatment after sputtering as in FIG.
[0025]
In sputter deposition, the non-defective gate breakdown voltage rate when the collimating plate is inserted between the wafer and the target is 100%, as shown by IV in FIG. As shown by III, the gate breakdown voltage is not deteriorated by sputtering, and a good gate breakdown voltage is obtained, as compared with the good gate breakdown voltage product ratio when titanium is sputtered and immediately wet-etched.
[0026]
In this case, the charge that should reach the wafer because the collimating plate is inserted between the wafer and the target flows to the collimating plate, and the charge-up of the gate electrode is suppressed. Quantity Q is 5C / cm²This is because the following sputter deposition can be performed.
[0027]
Normally, the collimated sputtering is for improving the coverage of the sputtered film by depositing titanium at the bottom of the contact hole with good anisotropy. However, in this case, it is not necessary to use an existing collimating plate, and an electrically grounded plate such as a mesh plate may be inserted between the wafer and the target. A result similar to the obtained result is obtained.
[0028]
As described above, when a high-melting-point metal is sputter-deposited on a floating gate electrode having a salicide structure, a method of controlling the amount of charge reaching the wafer is to prevent unnecessary charge from being generated from the plasma, It is conceivable to prevent the generated charges from reaching the wafer. Therefore, the gate breakdown voltage characteristics can be improved by combining the above two types or a combination thereof.
[0029]
In order to realize a sputtering apparatus that can achieve the above-described object of the present invention, the present inventor has found that the cause of insulation failure of the gate oxide film is that charged particles near the target reach the wafer surface. However, it has been found that the material penetrates the silicon substrate through the polysilicon film and the gate oxide film of the gate electrode. That is, it is speculated that the cause of the deterioration of the withstand voltage of the gate oxide film is due to an increase in the collision probability that charged particles fly from the high charged particle density region existing near the plasma (on the wafer side) and collide with the wafer. did.
As is clear from the erosion measurement of the target, the region having a high plasma density is more concentrated in the peripheral direction than in the center in the diameter direction of the target. The region with high plasma density is located very close to the target when viewed from the target toward the wafer, but the region with high charged particle density is considered to be located on the wafer side of the plasma region. Can be
Therefore, in order to prevent charged particles from flying on the wafer and colliding, a collimator plate is placed at a position close to the target and slightly away from the plasma area to the wafer side. With the idea of capturing particles with a collimating plate, and further studied the positional relationship between the target and the collimating plate, the present invention has been completed.
[0030]
In order to achieve the further object of the present invention described above, based on the above findings, the sputtering apparatus according to the present invention deposits a target metal so as to face the target held by the target holder and the target. A wafer holder that holds a wafer to be sputtered, and a sputtering apparatus that sputters a target metal on the wafer.In the sputtering apparatus, between the target holder and the wafer holder, a conductive material having a large number of through holes penetrating from the target toward the wafer The distance from the target surface is 24 mm or more with the body collimating plate grounded39 mmLess thanWhenIt is characterized by being interposed at a certain position.
[0031]
See belowAs can be seen from the results of Experimental Examples 1 and 2, the effect of the interposition of the collimating plate greatly differs depending on the position of the collimating plate with respect to the target. There is a critical significance. Therefore, in a preferred embodiment of the present invention, the collimating plate is provided with the first distance D with respect to the target holder.₁In the following, the second interval D₂ Arranged at the intervals in the above range, more preferably, the sputtering apparatus includes position adjusting means for positioning and holding the collimator plate within the interval in the range. First interval D₁And the second interval D₂Is different depending on the structure of the sputtering apparatus and the sputtering conditions, but is practically the first distance D for the reason described later.₁But39 mmAnd the second interval D₂ Is 24 mm.
[0032]
In addition, the ratio of the sum of the opening areas of all the through holes to the surface area of the collimating plate, the opening ratio is preferably higher, and the shape and dimensions of the through holes of the collimating plate are not limited. And a net-like plate having an aspect ratio of the through hole of 0.7 or more and 1.3 or less.
[0033]
The present invention can be applied to a sputtering device that performs sputtering by glow discharge without any limitation on the type and type of the sputtering device, and can be applied to, for example, a DC sputtering device, a high frequency (RF) sputtering device, and a magnetron sputtering device.
[0034]
When the collimating plate is interposed between the target and the wafer, it is considered that the degree of the initial breakdown voltage degradation of the gate insulating film depends on the distance between the collimating plate and the target holder, the aspect ratio of the collimating plate, and the sputtering rate.
[0035]
In the absence of a collimating plate, the probability that charged particles coming from the highly charged particle region directly collide with the wafer is higher at the wafer periphery, and therefore the degree of initial withstand voltage degradation of the gate insulating film at the wafer periphery is lower at the wafer center. Intense compared to the department.
For example, in the case of a magnetron sputtering apparatus, the shape and dimensions of the cathode magnet differ for each magnetron sputtering apparatus, and as a result, the plasma density distribution in the target diameter direction and, consequently, the distribution of charged particles are different. However, as a general tendency, the deterioration is more severe in the peripheral portion of the wafer.
In addition, when no collimating plate is interposed, an increase in leakage current between the gate, source and drain is measured at the center of the wafer as compared with the case where the collimating plate is interposed, and the gate oxide film is damaged during sputtering. Is clearly given.
[0036]
The distance between the collimator plate and the target holder (distance between T / C) is a factor to be determined so as to increase the probability of capturing charged particles directly flying from the high charged particle density region, and as described above. In addition, the interposition effect of the collimating plate greatly depends on the position of the collimating plate with respect to the target, and the position of the collimating plate with respect to the target has a critical significance. For example, if the T / C distance is 50 mm or more, the effect of the interposition of the collimating plate is significantly reduced.
If the T / C distance is shortened and the angle of incidence of the charged particles on the collimator plate is increased, the probability of capturing the charged particles on the collimator plate can be increased. Deterioration of the withstand voltage can be effectively prevented. However, conversely, if the T / C distance is too short, the collimating plate comes into contact with the high-density plasma existing region, and the collimating plate may be sputtered and cut off, which is extremely dangerous. , The allowable minimum distance (for example, 24 mm) is set as the distance between T / C.
[0037]
Increasing the aspect ratio of the collimating plate increases the probability of capturing charged particles from the high charged particle density region described above, and is effective in preventing the initial dielectric breakdown voltage of the gate oxide film from deteriorating. However, if the aspect ratio is too large, the sputtered metal is captured, and the sputter rate is reduced.
[0038]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
First Embodiment of Semiconductor Device Manufacturing Method According to the Present Invention
FIG. 1 is a sectional view of an element in each step of a first embodiment of a method of manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1A, an N well 102 is formed on a P-type silicon substrate 101 by a known method. Next, a field oxide film 103 is formed as a field insulating film on the surface of the P-type silicon substrate 101 by a selective oxidation method. In the active region surrounded by the field oxide film 103, a gate insulating film 104 such as a silicon oxide film and polycrystalline silicon are sequentially grown, and phosphorus is doped into the polycrystalline silicon by a known method to form an electric resistance of the polycrystalline silicon. Reduction.
[0039]
Next, the gate electrode 105 is formed by patterning the polycrystalline silicon by photolithography and dry etching, which are known methods, as shown in FIG. Next, a low concentration N-type impurity diffusion layer 113 and a low concentration P-type impurity diffusion layer 114 are formed by photolithography and ion implantation. Next, a sidewall 106 composed of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 105 by using a known CVD technique and an etching technique.
[0040]
Next, as shown in FIG. 1B, a source / drain region 107 of an N-type impurity diffusion layer and a source / drain region 108 of a P-type impurity diffusion layer are formed by photolithography and ion implantation. Thus, an N-type source / drain region 107 and a P-type source / drain region 108 are formed as an LDD structure.
[0041]
Next, the surface of the polycrystalline silicon which is the gate electrode 105 and the natural oxide film on the surface of the semiconductor substrate are removed, and for example, the charge amount Q reaching the gate electrode 105 is 5 C / cm.²Using a magnetron sputtering apparatus under the following conditions, titanium, which is a high melting point metal, is sputter deposited to form a titanium film 109. At this time, in the magnetron sputtering apparatus used, for example, a net-like conductor such as a collimator plate is inserted between the wafer and the target to perform sputtering.
[0042]
FIG. 6 shows a configuration diagram of an example of a magnetron sputtering apparatus used in the first embodiment of the method of the present invention. In the magnetron sputtering apparatus shown in FIG. 6A, a wafer 63 is placed on a wafer holder 62 in a chamber 61, and a cathode magnet 64 and a target 65 are arranged at positions opposed to and separated from the wafer 63. A collimating plate 66 is arranged at a spatial position between the two.
[0043]
A commonly used collimating plate enhances the anisotropy of sputtered particles and has an aspect ratio of a net of about 1. The collimating plate 66 used in this sputtering apparatus has a top view shown in FIG. As shown, the structure is made of a net-like conductor. The collimating plate 66 may simply be a conductive plate inserted between the wafer and the target. The aspect ratio, size, and shape of the collimating plate 66 are arbitrary, and cover the entire surface of the wafer 63. It is not necessary to cover only the region where the plasma intensity distribution is high or the charge is easily generated.
[0044]
Further, the shape and shape of the collimating plate 66 may be adjusted by a sputtering device. The reticulated conductor of the collimating plate 66 may be used as a ground potential, but the effect is further improved by applying a potential corresponding to the plasma state. Further, in the first embodiment, the example in which the titanium film 109 is deposited is shown. However, the same effect can be obtained by depositing another refractory metal such as cobalt or nickel. It is.
[0045]
Next, as shown in FIG. 1C, the surface of the gate electrode 105, which is polycrystalline silicon, and the source / drain regions 107 and 108 are brought into contact by rapid thermal processing (RTA) at 700 ° C. or less in a nitriding atmosphere. A titanium silicide layer 110 having a C49 type structure is formed only at the interface of the titanium film 109. At this time, the titanium film 109 in contact with the field oxide film 103 and the sidewall 106 and a part of the titanium film 109 on the semiconductor substrate are nitrided to form a titanium nitride film 111.
[0046]
Next, as shown in FIG. 1D, wet etching is selectively performed using a mixed solution of ammonia water and hydrogen peroxide solution to remove only the unreacted titanium and the titanium nitride film 111. Next, RTA at a higher temperature (800 ° C. or higher) than the above-described RTA is performed to form a titanium silicide 112 having a C54 type structure having lower electric resistivity than the titanium silicide layer 110 having a C49 type structure.
[0047]
In the MOS type field effect transistor manufactured in this manner, the gate withstand voltage is not deteriorated by sputtering, and a good gate withstand voltage is obtained. This is because, since the collimating plate 66 is inserted between the wafer 63 and the target 65, charges that should reach the wafer 63 flow to the collimating plate 66, and the charge-up of the gate electrode 105 is suppressed.
[0048]
When a refractory metal is sputter-deposited on a floating gate electrode having a salicide structure as described above, as a method of controlling the amount of charge reaching the wafer, the generated charge is prevented from reaching the wafer. Withstand voltage characteristics can be improved.
Second embodiment of a method for manufacturing a semiconductor device according to the present invention
As shown in FIG. 2A, an N well 202 is formed on a P-type silicon substrate 201 by a known method. Next, a field oxide film 203 is formed as a field insulating film on the surface of the P-type silicon substrate 201 by a selective oxidation method. In the active region surrounded by the field oxide film 203, a gate insulating film 204 such as a silicon oxide film and polycrystalline silicon are sequentially grown, and the polycrystalline silicon is doped with phosphorus by a known method to form an electric resistance of the polycrystalline silicon. Reduction. Next, the polycrystalline silicon is patterned by a known method such as photolithography and dry etching to form a gate electrode 205 as shown in FIG. 2A.
[0049]
Next, a low-concentration N-type impurity diffusion layer 213 and a low-concentration P-type impurity diffusion layer 214 are formed by photolithography and ion implantation. Next, a sidewall 206 made of a silicon oxide film or a silicon nitride film is formed on the side surface of the gate electrode 205 by using a known CVD technique and an etching technique.
[0050]
Next, as shown in FIG. 2B, a source / drain region 207 of an N-type impurity diffusion layer and a source / drain region 208 of a P-type impurity diffusion layer are formed by photolithography and ion implantation. Next, the surface of the polycrystalline silicon that is the gate electrode 205 and the natural oxide film on the surface of the semiconductor substrate are removed, and for example, the charge amount Q reaching the gate electrode is 5 C / cm.²A titanium film 209 is formed by sputtering and depositing titanium, which is a high melting point metal, using a magnetron sputtering apparatus under the following conditions.
[0051]
The configuration of the magnetron sputtering apparatus used at this time is shown in FIG. 7 (b), (d) or (e). As a conventional sputtering apparatus, as shown in FIG. 7A, a wafer 73 is placed on a wafer holder 72 in a chamber 71, and a target 74 is arranged at a position facing and away from the wafer 73, and there is no holder magnet. Although a sputtering apparatus having a structure is known, according to the detailed experimental results of the present inventors, in the region where the plasma density of the plasma 75 is the highest, the gate initial breakdown voltage deterioration was most observed.
[0052]
On the other hand, the magnetron sputtering apparatus shown in FIG. 7B has a size such that a region where the plasma density of the plasma 77 is maximum is outside the substrate (wafer) in a magnetron sputtering apparatus having no holder magnet. This is a magnetron sputtering apparatus having a structure using the set target 76. When the above-described titanium film 209 is sputter-deposited, electric charges generated from the plasma 77 can be prevented from reaching the wafer 73. Obtained.
[0053]
Further, the magnetron sputtering apparatus shown in FIGS. 7A and 7B has a structure in which the plasmas 75 and 77 are in direct contact with the wafer 73, whereas the conventional magnetron sputtering apparatus has the structure shown in FIG. As shown, a magnetron sputtering apparatus having a structure in which a holder magnet 79 is mounted in a state where the plasma 80 does not contact the wafer 73 is also known. That is, in this conventional magnetron sputtering apparatus, the wafer 73 is placed on the wafer holder 72 via the holder magnet 79 in the chamber 71, and the plasma 80 from the target 74 does not contact the wafer 73.
[0054]
However, even in this conventional magnetron sputtering apparatus, the charge (Ar⁺Alternatively, the electron) arrives at the wafer 73, so that a gate initial withstand voltage defect similarly occurs. According to the detailed experimental results of the inventor, a portion where the gate initial withstand voltage has deteriorated is found around the wafer 73.
[0055]
In this embodiment, a titanium film 209 is used as a gate electrode by using a magnetron sputtering apparatus having a structure shown in FIG. 7D or FIG. 7E as a magnetron sputtering apparatus having a structure having the holder magnet. The charge amount Q that reaches 5 C / cm²Sputter deposition is performed under the following conditions. The magnetron sputtering apparatus shown in FIG. 7D is characterized in that the holder magnet 81 attached for stabilizing the plasma is shaped to cover the side surface of the wafer 73, thereby generating the plasma 82. The trapped charge is trapped by the magnetic field of the holder magnet 81, so that a gate initial breakdown voltage defect can be suppressed.
[0056]
In the magnetron sputtering apparatus shown in FIG. 7E, the magnetic field strength of the holder magnet 83 attached for stabilizing the plasma is set such that the maximum plasma area of the plasma 84 is above the wafer 83. The feature is that the charge generated from the plasma 84 is trapped by the magnetic field of the holder magnet 83, so that the gate initial breakdown voltage defect can be suppressed.
[0057]
In the case of the magnetron sputtering apparatus having the structure shown in FIG. 7D or FIG. 7E, since the electric charge is trapped by the magnetic field generated from the holder magnets 81 and 83, the deteriorated portion is not seen in the peripheral part. Good electrical characteristics were obtained. Actually, the degree of deterioration of the gate initial withstand voltage changes depending on the structure of the magnetron sputtering apparatus. Therefore, optimization is performed by a combination of the method of changing the maximum plasma area described above and the method of trapping by the magnetic field generated by the holder magnet on the wafer side. It is also conceivable.
[0058]
Although the second embodiment shows an example in which titanium is deposited, it is a matter of course that the same effect can be obtained by depositing another refractory metal such as cobalt or nickel.
[0059]
Returning to FIG. 2 again, as shown in FIG. 2 (c), the surface of the gate electrode 205 made of polycrystalline silicon and the A titanium silicide 210 having a C49 type structure is formed only at the interface of the titanium film 109 in contact with the source / drain regions 107 and 108. At this time, as shown in FIG. 2C, the titanium film 209 in contact with the field oxide film 203 and the sidewall 206 and a part of the titanium film 209 on the semiconductor substrate are nitrided to form a titanium nitride film 211. .
[0060]
Next, as shown in FIG. 2D, wet etching is selectively performed using a mixed solution of aqueous ammonia and aqueous hydrogen peroxide to remove only the unreacted titanium and the titanium nitride film 211. Next, RTA at a higher temperature (800 ° C. or higher) than the above-described RTA is performed to form a titanium silicide 212 having a C54 type structure having a lower electric resistivity than the titanium silicide 210 having a C49 type structure.
[0061]
In this embodiment, by making the configuration of the magnetron sputtering apparatus as shown in FIG. 7B, FIG. 7D or FIG. 7E, the charge generated from the plasma does not reach the wafer, and the gate initial withstand voltage degradation is reduced. Can be suppressed. Further, in the magnetron sputtering apparatus used in the first embodiment, since a conductive net-like collimating plate is inserted, the sputtered film is deposited on the conductive net-like collimating plate, so that the sputtered film is deposited on the wafer. The collimator plate needs to be replaced due to a problem such as a decrease in the sputter rate or particles. On the other hand, the magnetron sputtering device used in the second embodiment does not include a conductive net-like collimator plate. Therefore, there is an advantage that it is not necessary to replace the collimating plate, and it is easy to maintain the apparatus stably.
[0062]
In the first and second embodiments, the method of forming silicide on the gate and the diffusion layer at the same time has been described. However, the polycide gate (WSix / Poly-Si), the polytamel gate (W / WNx) / Poly-Si) or metal gate (W / SiO)₂The present invention can of course be applied to the case where a refractory metal is sputtered on a floating gate having a structure or the like to form silicide on a diffusion layer.
[0063]
Embodiment of the sputtering apparatus according to the present invention
This embodiment is an example of an embodiment in which the sputtering apparatus according to the present invention is applied to a magnetron sputtering apparatus. FIG. 10A is a schematic cross-sectional view illustrating the configuration of the magnetron sputtering apparatus according to the embodiment. FIG. 10B is a plan view of the collimator plate, and FIG. 10C is a side view of the collimator plate. 10, the same components and parts as those in FIG. 8 are denoted by the same reference numerals.
As shown in FIG. 10, the magnetron sputtering apparatus 30 of the present embodiment basically has the same configuration as the magnetron sputtering apparatus shown in FIG. 6 described above. , A cathode magnet 16 for holding a target T at a position facing away from and facing the wafer W, and a net-plate-like collimating plate provided between the wafer holder 14 and the cathode magnet 16 32.
[0064]
The collimating plate 32 is provided to increase the anisotropy of the sputtered particles and to capture the charged particles, and as shown in FIG. 10B, is made of a net-shaped conductor in which regular hexagons are continuous. It is configured as a mesh plate and is grounded. The regular hexagonal mesh or hole of the collimating plate 32 penetrates from the target T toward the wafer W, and the mesh or hole has an aspect ratio of 1. That is, the thickness t of the collimating plate (see FIG. 10C) and the diameter D of the mesh or hole (the maximum diameter of the mesh or hole, see FIG. 10B) are the same length.
The collimator plate 32 is moved by a position adjusting mechanism 34 from the surface of the collimator plate 32 to the target holding surface of the cathode magnet 16 (distance between T / C, L in FIG. 10A).₁) Is changed and held at that position. The position adjusting mechanism 34 is a known mechanism, and moves the collimating plate 32 up and down freely by a driving device such as a hydraulic cylinder or an air cylinder.
The size of the collimator plate 32 does not need to cover the entire surface of the wafer W, and it is sufficient that the collimator plate 32 covers only a region where the plasma intensity distribution is high or charged particles are easily generated.
[0065]
Experimental example 1
A sputtering experiment was performed using an experimental apparatus having the same configuration as the magnetron sputtering apparatus 30 of the present embodiment, in which a collimator plate was attached to Model No. I-1060 manufactured by Anelva Co., Ltd. The specifications of the experimental device are briefly described below.
target
Thickness: 3mm
Diameter: 12 inches
Wafer holder
Wafer size: 6 inch diameter or 8 inch diameter
Chuck type: Clamp chuck
Collimating plate
Hole diameter D: 23 mm
Thickness t: 23 mm
Hole shape: Continuous hexagonal shape
Aspect ratio: 1
Material: stainless steel
[0066]
In the experimental apparatus described above, the distance between the target holding surface of the cathode magnet 16 and the surface of the wafer W (distance between T / S; in FIG.₂Is adjusted to 103 mm, and the distance L between the target holding surface of the cathode magnet 16 and the opposing surface of the collimating plate 32 is adjusted.₁Was adjusted to 34 mm, and the sputter power applied between the wafer holder 14 and the cathode magnet 16 was changed to 1.0 kW, 1.5 kW and 2.0 kW, and Co was sputtered under the following sputtering conditions to form a film. A 100 ° thick Co film was formed on the polysilicon film shown in FIG.
Sputtering conditions
Holder temperature: Room temperature
Chamber pressure: 3 to 8 mTorr
Next, the quality of the withstand voltage of the gate oxide film is examined for each chip, and as shown in FIGS. 12A to 12C, the chip with a severe insulation failure of the gate oxide film is black, and the chip with a slight insulation failure is gray. It was painted.
[0067]
Experimental example 2
Using the same experimental apparatus as in Experimental Example 1, the distance L between the target holding surface of the cathode magnet 16 and the surface of the wafer W was determined.₂Is adjusted to 113 mm, and the distance L between the target holding surface of the cathode magnet 16 and the opposing surface of the collimating plate 32 is adjusted.₁To 24 mm, 29 mm, 34 mm, 39 mm, 44 mm and 56 mm and the same L₁The sputtering power applied between the wafer holder 14 and the cathode magnet 16 was changed to 1.0 kW, 1.5 kW and 2.0 kW, and Co sputtering was performed a total of 18 times under different conditions. The other conditions were the same as the sputtering conditions used in Experimental Example 1.
Next, the quality of the withstand voltage of the gate oxide film is checked for each chip, and as shown in FIGS. 13 (a) to 13 (c) to FIGS. Black and slightly insulated chips were colored gray.
[0068]
As shown in FIG. 19, the experimental results of Experimental Examples 1 and 2 were totaled using the sputtering power as a parameter. In FIG. 19, L is plotted on the horizontal axis.₁The vertical axis represents the yield rate (%) of the gate oxide film.
As can be seen from FIG. 19, regardless of the magnitude of the sputtering power, L₁Is 39 mm or less, the non-defective rate reaches almost 100%.₁Is 44 mm or more, the non-defective rate drops sharply to 60% or less. In other words, regarding the yield rate of the gate oxide film, that is, the effect of the interposition of the collimating plate 32, it is understood that a clear critical position of the collimating plate 32 with respect to the target or the cathode magnet exists between 39 mm and 44 mm.
The bar graph on the left end of FIG. 19 is a numerical value of the non-defective rate when no collimating plate is interposed,₁Is almost the same as the non-defective product ratio when is 56 mm.
[0069]
Experimental example 3
Using the same experimental apparatus as in Experimental Example 1, the distance L between the collimator plate and the cathode magnet was measured.₁Is 29 mm, and the distance L between the cathode magnet and the wafer holder is L₂Was set to 68 mm, and the relationship between the sputtering power (kW) and the yield rate of the gate oxide film was examined under the following sputtering conditions. The results are shown in FIG. For comparison, sputtering was performed using a magnetron sputtering apparatus having the same configuration as the experimental apparatus except that the collimator plate was not provided, and the results are also shown in FIG.
Sputtering conditions
Chamber pressure: 8 to 10 mTorr
Gas flow rate: 80-100 scc / m
Sputter power: 1.5kW
As can be seen from FIG. 20, by providing the collimating plate with the distance relationship specified in the present invention, the magnetron sputtering device of the present embodiment has a lower gate oxide film yield than the magnetron sputtering device without the collimating plate. Extremely low sputter power dependence.
[0070]
Experimental example 4
Using the same experimental apparatus as in Experimental Example 1, the distance L between the collimator plate and the cathode magnet was measured.₁Is 29 mm, and the distance L between the cathode magnet and the wafer holder is L₂Was set to 68 mm, and the relationship between the sputter rate (Å / sec) and the yield rate of the gate oxide film was examined under the following sputtering conditions. The results are shown in FIG. For comparison, sputtering was performed using a magnetron sputtering apparatus having the same configuration of this embodiment except that no collimating plate was provided, and the results are also shown in FIG.
Sputtering conditions
Chamber pressure: 8 to 10 mTorr
Gas flow rate: 80-100 scc / m
Sputter power: 1.5kW
As can be seen from FIG. 21, by providing the collimating plate with the distance relationship specified in the present invention, the magnetron sputtering device of the present embodiment has a higher yield rate dependency on the sputtering rate than the magnetron sputtering device without the collimating plate. Is low.
[0071]
By increasing the sputter rate, the conductive metal (or metal silicide) quickly covers the wafer surface, so that the charged particles travel more in the horizontal direction of the wafer than in the depth direction of the gate, resulting in gate oxidation. The initial withstand voltage degradation probability of the film is reduced.
Therefore, increasing the sputtering rate is effective in preventing the initial withstand voltage of the gate oxide film from deteriorating as shown in FIG. However, if the sputter rate is too high, the difference in the in-plane film thickness distribution of the wafer increases, and there is a concern that the amount of silicidation reaction during high-temperature sputtering may decrease. Not preferred. When the sputter rate was increased by setting the sputter power of Experimental Example 3 to 2.6 kW, the non-defective rate was verified to be 98% even when the distance between the collimator plate and the cathode holding surface of the cathode magnet 16 was 50 mm. Was done.
In addition, even if an attempt is made to prevent the deterioration of the withstand voltage of the gate oxide film by increasing the sputter rate, immediately after the start of the sputtering, the conductive metal film that blocks the flying of the charged particles to the gate is not formed. Therefore, the effect of preventing the initial breakdown voltage of the gate oxide film from deteriorating is lower than when the collimating plate is interposed.
In addition, as for the results obtained with different end manufacturers (AMAT ENDURA), satisfactory results were obtained even at 46.5 mm.
[0072]
Experimental example 5
Using the magnetron sputtering apparatus of the present embodiment used in Experimental Examples 1 and 2, the distance L between the collimator plate and the cathode magnet was L.₁Is 34 mm, the distance L between the cathode magnet and the wafer holder₂Is set to 103 mm, the applied voltage is fixed to 1.5 kW, and the gas pressure is set to 5 mTorr, 8 mmTorr, 10 mTorr, and 15 mTorr, and Co sputtering is performed, respectively, and the yield rate of the gate oxide film depends on the gas pressure. The relationship was examined for gender.
As a result, at a gas pressure of 5 mTorr, 8 mmTorr, 10 mTorr, and 15 mTorr, the non-defective rate of the gate oxide film is 100%, and the non-defective rate of the gate oxide film is reduced in the magnetron sputtering apparatus provided with the collimating plate. It was found that there was no gas pressure dependency.
[0073]
From the results of Experimental Examples 1 to 5 described above, the sputtering apparatus of the present embodiment provides a gate by disposing the collimator plate 32 within a range of 24 mm or more and 50 mm or less with respect to the cathode holding surface of the cathode magnet 16. It has been proved that the sputtering apparatus is capable of sputtering a high melting point metal on a polysilicon film while preventing the gate oxide film from deteriorating in forming a high melting point metal silicide film on an electrode.
In addition, the sputtering apparatus of this embodiment has a low sputter power dependency, a sputter rate dependency, and a gas pressure dependency with respect to the non-defective rate of the gate oxide film, and can set a wide range of sputtering conditions.
[0074]
【The invention's effect】
As described above, according to the present invention, in a method of manufacturing a semiconductor device in which a high-melting-point metal silicide layer is formed between insulating films selectively formed on a semiconductor substrate, under a condition where deterioration of a gate withstand voltage does not occur. The MOS field-effect transistor (MOSFET), which achieves low resistance by forming a high-melting metal silicide layer because a high-melting-point metal is deposited by sputtering, has been miniaturized by making the gate insulating film thinner and more highly integrated. Even in this case, it can be manufactured with higher reliability.
[0075]
According to the sputtering apparatus of the present invention, a collimator plate made of a conductor having a large number of through holes penetrating from the target toward the wafer is interposed between the target holder and the wafer holder in a grounded state. Preferably, the collimating plate is placed at a first distance D with respect to the target holder.₁In the following, the second interval D₂By forming the refractory metal silicide film on the gate electrode, the refractory metal can be sputtered on the polysilicon film by preventing the deterioration of the dielectric strength of the gate oxide film when the refractory metal silicide film is formed on the gate electrode. A sputter device has been realized.
Further, the sputtering apparatus according to the present invention has low sputter power dependency, sputter rate dependency, and gas pressure dependency with respect to the yield rate of the gate oxide film, and can set sputtering conditions in a wide range.
[Brief description of the drawings]
FIG. 1 is a sectional view of an element in each step of a first embodiment of the present invention.
FIG. 2 is a sectional view of an element in each step of a second embodiment of the present invention.
FIG. 3 is a sectional view of an element in each step of an example of a conventional method.
FIG. 4 is a diagram showing a non-defective product ratio of a gate withstand voltage when the sputtering is performed under the conventional sputtering conditions.
FIG. 5 is a diagram showing a non-defective product ratio and the like of a gate withstand voltage characteristic when a collimating plate is inserted.
FIG. 6 is a configuration diagram of a sputtering apparatus used in the first embodiment of the present invention.
FIG. 7 is a configuration diagram of a sputtering apparatus of each example used in the second embodiment of the present invention and a conventional sputtering apparatus.
FIG. 8 is a schematic diagram showing a configuration of a conventional sputtering apparatus.
FIG. 9 is an explanatory diagram of silicidation.
FIG. 10A is a schematic diagram illustrating a configuration of a sputtering apparatus according to an embodiment, FIG. 10B is a plan view of a collimator plate, and FIG. 10C is a side view of the collimator plate.
FIG. 11 is a wafer map showing gate oxide film deterioration when sputtering is performed using a conventional sputtering apparatus.
FIGS. 12 (a) to 12 (c) are wafer maps showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.
FIGS. 13A to 13C are wafer maps showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.
FIGS. 14A to 14C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under mutually different conditions using the sputtering apparatus of the present embodiment.
FIGS. 15A to 15C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under mutually different conditions using the sputtering apparatus of the present embodiment.
FIGS. 16A to 16C are wafer maps each showing deterioration of a gate oxide film when sputtering is performed under different conditions using the sputtering apparatus of the embodiment.
FIGS. 17A to 17C are wafer maps showing deterioration of a gate oxide film when sputtering is performed under mutually different conditions using the sputtering apparatus of the embodiment.
FIGS. 18A to 18C are wafer maps showing deterioration of a gate oxide film when sputtering is performed under mutually different conditions using the sputtering apparatus of the present embodiment.
FIG. 19 is a graph summarizing the experimental results of Experimental Examples 1 and 2 using the sputtering power as a parameter.
FIG. 20 is a graph showing sputter power dependence of the yield rate.
FIG. 21 is a graph showing the sputter rate dependence of the yield rate.
[Explanation of symbols]
10 Conventional sputtering equipment
12 Sputter chamber
14 Wafer holder
16 Cathode magnet
20 Silicon substrate
22 polysilicon film
24 Co film
26 Sidewall
28 Gate oxide film
30 Sputtering apparatus of embodiment example
32 collimating plate
34 Position adjustment mechanism
61, 71 chambers
62, 72 Wafer holder
63, 73 wafer
65, 74, 76 targets
66 Collimating plate
75, 77, 80, 82, 84 Plasma
79, 81, 83 Holder magnet
101, 201 P-type silicon substrate
102, 202 N well
103, 203 Field oxide film
104, 204 Gate insulating film
105, 205 Gate electrode
106, 206 Side wall
107, 207 N-type source / drain regions
108, 208 P-type source / drain regions
109, 209 Titanium film
110, 210 C49 type titanium silicide layer
111, 211 titanium nitride film
112,212 Titanium silicide layer of C54 type structure
113, 213 N-type impurity diffusion layer
114, 214 P-type impurity diffusion layer

Claims (8)

A high melting point metal is deposited by a magnetron sputtering apparatus on the silicon substrate on which the polysilicon gate electrode of the semiconductor element is formed, and a high melting point metal film is formed. In a method of manufacturing a semiconductor device for forming a refractory metal silicide layer,
The refractory metal film is sputter-deposited by a magnetron sputtering apparatus under the condition that the charge amount Q reaching the gate electrode is 5 C / cm ² or less, and a gate insulation formed between the silicon substrate and the gate electrode is formed. A method of manufacturing a semiconductor device, wherein a gate withstand voltage of a film is not deteriorated . The magnetron sputtering apparatus is configured to set a size of a target and a cathode magnet so as to sputter deposit the refractory metal film so that a maximum plasma density region is outside the silicon substrate. Item 2. A method for manufacturing a semiconductor device according to Item 1. 2. The semiconductor device according to claim 1, wherein the magnetron sputtering apparatus is configured to sputter deposit the refractory metal in a state where the holder magnet on the silicon substrate side covers a side surface of a wafer having the silicon substrate. Method. The magnetron sputtering apparatus reduces the strength of the holder magnet on the wafer side so that the charged particles from the high charged particle density area near the plasma density maximum area are trapped by the magnetic field of the holder magnet and do not reach the wafer. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the method is configured to set the high melting point metal by sputtering. The magnetron sputtering apparatus, a space between the target and the wafer having the silicon substrate, in a region where the charged particle density is higher on the wafer side than the plasma density maximum region, insert a collimator plate of a conductor, 2. The method according to claim 1, wherein the charged particles are captured by a collimating plate. 6. The method according to claim 5, wherein the collimating plate is inserted at a position where the distance from the target surface is 24 mm or more and 39 mm or less. 7. The method according to claim 6, wherein an upper surface of the collimating plate has a net shape. 8. The method according to claim 1, wherein the refractory metal is any one of titanium, cobalt, and nickel.

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