JP2006074071A - Forming method of silicide film - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a forming method of a silicide film capable of suppressing a thin line effect even if the silicide film is thinned. <P>SOLUTION: After an argon ion is implanted into an entire SOI substrate, the substrate is controlled at about 300°C, and a titanium film 21 (thickness: 15 nm) is formed by using a Long Throw Sputtering Process. A titanium nitride film 23 (thickness: 30 nm) is continuously formed without exposing the substrate to the atmosphere. First thermal treatment (750°C) is performed in a nitrogen atmosphere to self-aligningly form silicide films 31, 32 and 33 (thickness: 30 nm each) on a gate region, a source region, and a drain region, respectively. After a titanium film unreacted with the titanium nitride film is removed, second thermal treatment (850°C) is performed. The silicide films 31, 32 and 33 each having a crystal structure C49 of high resistance is phase-changed to a silicide film of a crystal structure C54 of low resistance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for forming a silicide film.

  In recent years, semiconductor devices have achieved tremendous integration due to advances in various microfabrication technologies. However, nowadays when the design rule is in the sub-micron region, an increase in parasitic resistance becomes an obstacle, and even if the circuit pattern is miniaturized, the performance of the semiconductor device is not necessarily improved. Therefore, research and development of new technologies to solve the problems that occur with miniaturization are ongoing. In particular, much attention has been focused on the SALICIDE (Self-Aligned Silicide) process technology that can keep the resistance of the gate electrode and impurity diffusion layer low. The salicide process technology and related technologies are disclosed in the following patent documents and non-patent documents.

  On the other hand, the “SOI (Silicon-On-Insulator) structure”, which has an insulating film (silicon oxide film) on a silicon substrate and a thin silicon single crystal layer on it Is progressing. By forming the transistor in this silicon single crystal layer, the parasitic capacitance of the source / drain region is reduced, so that low-loss / high-speed operation of the transistor is realized. Also, according to the SOI structure, each element can be electrically isolated, and thus problems such as current leakage do not occur even if the elements are arranged at a narrow interval.

  As described above, the salicide process and the SOI structure are extremely effective techniques in semiconductor devices that will be further miniaturized in the future, and research on these combinations is also actively conducted.

  In the case of a fully depleted SOI transistor, the silicon single crystal layer serving as an active region is extremely thin, and is generally 50 nm or less. When the thickness of the metal film (titanium film or the like) deposited on the surface of the silicon single crystal layer is 25 nm, the active region (source region) is generated by a chemical reaction between the metal contained in the metal film and the silicon contained in the silicon single crystal layer. And the thickness of the silicide film formed in the drain region) is about 50 nm. In other words, in a fully depleted SOI transistor, unless the thickness of the metal film is accurately adjusted to form a thin silicide film, the silicide film contacts the insulating film located under the silicon single crystal layer. become. In this case, the contact area between the silicide film and the silicon single crystal layer is reduced, and the contact resistance between them is increased. In addition, if the metal film is too thick relative to the silicon single crystal layer, the supply of silicon from the silicon single crystal layer side is insufficient in the chemical reaction for forming the silicide film, and voids are formed in the drain and source regions. It will occur.

  As described above, when a silicide process is applied to manufacture a semiconductor device having a thin active region such as a fully depleted SOI device or a fine semiconductor device in which a source / drain region must be shallow, a metal film is thinned. It was necessary to deposit and form a thin silicide film.

Japanese Patent Laid-Open No. 10-335261 JP 2000-82811 A "Sub-Quarter Micron Titanium Salicide Technology With In-SituSilicidation Using High-Temperature Sputtering" NEC Corporation, 1995 Symposium on VLSI Technology Digest of Technical Papers, p.57-58 "The Orientation of Blanket W-CVD on the underlayer Ti / TiNstudied by XRD" Toshiba Corporation Semiconductor Company, ADMETA2000: Asian Session, PS-210, p71-72.

  However, in the conventional salicide process, the existence of the so-called fine line effect has been confirmed, in which the sheet resistance increases when the pattern width of the silicide film becomes narrow, and the thin line effect becomes remarkable when the silicide film becomes thin. . The dependence of the sheet resistance on the pattern width that becomes apparent when the silicide film becomes thinner hinders the application of the salicide process to a semiconductor device having a thin active region.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of forming a silicide film capable of suppressing the fine line effect even if the silicide film is thinned.

  In order to solve the above problems, according to a first aspect of the present invention, a method of manufacturing a semiconductor device having a silicide film is provided. In this manufacturing method, ions are implanted into the silicon region to make the surface portion of the silicon region amorphous, a substrate temperature adjusting step for adjusting the temperature of the substrate including the silicon region, A metal film forming step of forming a metal film (film thickness t1) by depositing a metal on the upper surface of the adjusted and amorphized silicon region, and a metal film on the upper surface of the metal film in succession to the metal film forming step. A protective film forming step for forming a protective film (film thickness t2, t2> t1) for protecting the substrate from the atmosphere, and heat treatment is performed on the metal film, the protective film, and the silicon region, and the metal contained in the metal film And a heat treatment step of reacting silicon contained in the silicon region to form a silicide film on the silicon region. According to such a manufacturing method, even if the silicide film is thin, the fine line effect does not appear in the silicide film.

  In addition, according to the second aspect of the present invention, a semiconductor device including a silicide film on the surface of a silicon region is provided. This silicide film is formed as follows. That is, first, ions are implanted into the silicon region to make the surface of the silicon region amorphous, and the silicon region is adjusted to a predetermined temperature. Thereafter, a metal film (film thickness t1) and a protective film (film thickness t2, t2> t1) for protecting the metal film from the atmosphere are continuously formed on the silicon region, and further, the metal film, the protective film, and A heat treatment is performed on the silicon region. As a result, the metal contained in the metal film reacts with the silicon contained in the silicon region to form a silicide film. This silicide film has the characteristics that the sheet resistance value is small and the pattern width dependency is small. Therefore, in the semiconductor device provided with this silicide film, excellent performance such as small size, low loss, and high speed operation can be obtained.

  In the ion implantation process, argon ions are implanted into the silicon region. Even if argon ions are implanted into the silicon region, they are unlikely to become either P-type impurities or N-type impurities there. Therefore, the surface of the silicon region, which is the purpose of ion implantation, can be made amorphous without significantly affecting the electrical characteristics of the silicon region.

  In the substrate temperature adjusting step, the substrate is adjusted to any temperature from 200 ° C. to 400 ° C., and in the metal film forming step, a metal film is formed using a long throw sputtering method or a collimated sputtering method. As a result, a metal film having good film quality can be obtained.

  By using any one of titanium, cobalt, and nickel as a metal for forming the metal film, a silicide film having a small sheet resistance value and a small pattern width dependency is formed.

  By forming a protective film mainly composed of titanium nitride or tungsten, the metal film can be protected from an external atmosphere such as oxygen.

  By adjusting the thickness t1 of the metal film to 15 nm or less, it is possible to form a silicide film having a very thin film thickness (30 nm or less). Further, in order to protect the metal film from the external atmosphere, the film thickness t2 of the protective film is adjusted to 30 nm or more.

  By including the source region and the drain region in the silicon region, a silicide film having a small sheet resistance value and a small pattern width dependency is formed in each of the source region and the drain region.

  Even when the substrate has an SOI structure and the silicon region is a silicon single crystal layer formed on an insulating film, a silicide film having a small sheet resistance value and a small pattern width dependency is formed in each region. .

  It is preferable not to perform an etching process for removing the exposed surface including the surface of the silicon region after the semiconductor device is loaded in the film forming apparatus for forming the metal film until the metal film forming process is performed. This is because when this etching process is performed, the material scraped off by the etching may contaminate the atmosphere in the film forming apparatus and adversely affect the formation of the metal film.

  As described above, according to the present invention, it is possible to form a silicide film in which the fine line effect is suppressed even when the film thickness is small. In addition, according to the present invention, it is possible to improve performance such as high integration of semiconductor devices, reduction of operation loss, and improvement of operation speed.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

  First, a basic configuration of a transistor having a silicide film and a basic manufacturing method when the transistor is formed on a bulk wafer will be described with reference to FIGS.

[Step 0-1] An element isolation film 7, a gate oxide film 9, a gate electrode 11, and a sidewall 13 are formed on the silicon substrate 1 (FIG. 1). For example, the element isolation film 7 is patterned with a silicon oxide film (film thickness 400 nm), the gate oxide film 9 is patterned with a silicon oxide film (film thickness 10 nm), and the gate electrode 11 is patterned with a polysilicon film (film thickness 200 nm). Formed by. Next, although illustration is omitted, the resistance of the gate electrode is reduced and the source / drain regions are formed by implanting P-type or N-type ions. Subsequently, arsenic ions are implanted into the entire surface of the silicon substrate 1 (ion implantation). The ion implantation conditions are, for example, an energy of 30 keV and a dose of 3 × 10 ¹⁴ cm ⁻² . Thereby, the region from the exposed surface to a predetermined depth of the silicon substrate 1 is made amorphous.

[Step 0-2] A metal film is formed. Here, titanium is deposited as a metal to form a titanium film 121 (thickness 30 nm) (FIG. 2).

[Step 0-3] First heat treatment (750 ° C.) is performed in a nitrogen atmosphere. As a result, titanium in the titanium film 121 reacts with silicon in the gate electrode 11 and the silicon substrate 1 to form silicide films 131, 132, 133 (films) in a self-aligned manner in the gate region, the source region, and the drain region, respectively. 60 nm thick) is formed (FIG. 3). These silicide films 131, 132, 133 have a high-resistance crystal structure C49.

[Step 0-4] The unreacted titanium film 121 is removed with a mixed solution of ammonia water and hydrogen peroxide solution (FIG. 4).

[Step 0-5] A second heat treatment (850 ° C.) is performed. As a result, the silicide films 131, 132, 133 having the high-resistance crystal structure C49 undergo phase transition to the silicide films 141, 142, 143 having the low-resistance crystal structure C54, respectively (FIG. 5).

[Step 0-6] After that, the MOS transistor is completed by forming an insulating film, a contact hole, a metal wiring, and the like.

  As described above, according to the steps 0-1 to 0-6, the low resistance silicide films 141, 142, 143 are formed in the gate region, the source region, and the drain region. These silicide films 141, 142, and 143 have a small pattern width dependency with respect to sheet resistance, and contribute to miniaturization and high speed of the transistor. However, since the film thickness is 60 nm, the silicide films 141, 142, and 143 cannot be applied to a fully depleted SOI transistor with the same film thickness. As described above, in the case of a fully depleted SOI transistor, since the thickness of the active region is 50 nm or less, the thickness of the silicide films 142 and 143 formed in the source region and the drain region is 50 nm which is thinner than the active region. Must be:

  If the titanium film 121 is thinly formed in the process 0-2, the silicide films 142 and 143 are also thinned according to the thickness. However, if the titanium film 121 is simply formed thinly, a thin line effect is produced in the silicide films 142 and 143. It becomes obvious. According to the present invention, it is possible to form a silicide film having a small film thickness and a small dependence of the sheet resistance on the pattern width. In addition, a semiconductor device having a silicide film with a thin film thickness and a reduced thin line effect is provided.

  A fully depleted SOI transistor as a semiconductor device according to an embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS.

[Step 1-1] A so-called SOI substrate comprising a silicon substrate 1, a silicon oxide film 3, and a silicon single crystal layer 5 is prepared. Then, an element isolation film 7, a gate oxide film 9, a gate electrode 11, and a sidewall 13 are formed on the silicon single crystal layer 5 (FIG. 6). For example, the element isolation film 7 is patterned with a silicon oxide film (thickness 100 nm), the gate oxide film 9 is patterned with a silicon oxide film (thickness 10 nm), and the gate electrode 11 is patterned with a polysilicon film (thickness 200 nm). Formed by. Next, although illustration is omitted, the resistance of the gate electrode is reduced and the source / drain regions are formed by implanting P-type or N-type ions. Subsequently, arsenic ions are implanted into the entire surface of the SOI substrate (ion implantation). The ion implantation conditions are, for example, an energy of 30 keV and a dose of 3 × 10 ¹⁴ cm ⁻² . As a result, the region from the exposed surface to a predetermined depth of the silicon single crystal layer 5 is amorphized.

[Step 1-2] Titanium is deposited to form a titanium film 21 (film thickness: 15 nm) (FIG. 7).

  Conventionally, a step of removing the surface layer portions of the silicon single crystal layer 5 and the gate electrode 11 by a dry etching (sputter etching) method is performed immediately before forming the titanium film 21. This dry etching process is performed for the purpose of removing dirt on the surfaces of the silicon single crystal layer 5 and the gate electrode 11. However, even if impurities are actually present, the amount thereof is extremely small. On the contrary, by performing this process, oxygen is ejected from the element isolation region 7 and the like, the atmosphere is contaminated, and the film quality of the titanium film 21 is deteriorated. There is also a risk. Therefore, the dry etching process is not carried out here.

  The thickness of the titanium film 21 is set according to the thickness of the active region, that is, the thickness of the silicon single crystal layer 5. In general, the thickness of the active region in a fully depleted SOI transistor is 50 nm or less, and the thickness of the silicide film formed in the active region must be less than that. Since the thickness of the silicide film is approximately 2.5 times the thickness of the titanium film 21, the thickness of the titanium film 21 is adjusted to 15 nm in consideration of manufacturing errors and the like here.

  The titanium film 21 is formed by using a collimate / sputtering method or a long throw / sputtering method. According to these sputtering methods, high straightness can be obtained in the metal sputtered from the metal target.

  As shown in FIG. 11, the collimating / sputtering method is characterized in that a collimating plate is disposed between a metal target and a wafer. By this collimating plate, only metal particles having a small incident angle on the wafer surface among the sputtered metal particles reach the wafer surface.

  On the other hand, the long throw sputtering method is characterized in that the distance between the metal target and the wafer is wider than the general sputtering method. For example, in the general sputtering method, the distance between the metal target and the wafer is adjusted to 60 mm, whereas in the long throw sputtering method, the distance is adjusted to 340 mm. Furthermore, in order to further improve the straightness of the sputtered metal particles, the degree of vacuum in the chamber is adjusted higher than in the case of general sputtering. According to this long throw sputtering method, among the sputtered metal particles, metal particles having a large oblique direction component (metal particles having an incident angle with respect to the wafer larger than θ) do not adhere to the wafer. In addition, the high degree of vacuum increases the mean free path of the sputtered metal particles and suppresses the scattering of the metal particles.

  The SOI substrate is adjusted to about 300 ° C. during the formation of the titanium film 21 by the collimated sputtering method or the long throw sputtering method.

  Here, FIG. 12 shows the X-ray diffraction result of the titanium film formed by using the long throw sputtering method on the substrate adjusted to room temperature, 200 ° C., 300 ° C., and 400 ° C. As is apparent from the measurement results, the orientation of the titanium (200) plane increases with increasing substrate temperature up to 300 ° C., and the orientation of the (200) plane weakens at 400 ° C. That is, it can be said that the titanium film formed under the substrate temperature condition of 200 ° C. to 400 ° C. has a different crystal structure from the titanium film formed under the temperature range or above.

  After the titanium film 21 is formed, a titanium nitride film 23 (thickness 30 nm) is continuously formed without exposing the SOI substrate to the atmosphere. Although the titanium film 21 has the property of being easily oxidized, a titanium nitride film (protective film) 23 that completely covers the upper surface of the titanium film 21 after it is formed is continuously formed. Is prevented. Thus, the titanium nitride film 23 plays a role of shielding the titanium film 21 from the oxygen atmosphere, and its film thickness is also important.

  As described above, in order to obtain a thin silicide film, the titanium film 21 needs to be formed thin. However, when the titanium film 21 is extremely thin with a thickness of 15 nm, oxygen may pass through the titanium nitride film 23 and reach the titanium film 21 unless the titanium nitride film 23 is formed thicker than that. The present invention has been devised so that predetermined characteristics can be obtained in a silicide film even when the silicide film is extremely thin. Considering the antioxidant function that the protective film (titanium nitride film) should have, it is preferable that the protective film is thicker than the metal film (titanium film) and has a thickness of 30 nm or more.

[Step 1-3] First heat treatment (750 ° C.) is performed in a nitrogen atmosphere. As a result, titanium in the titanium film 21 reacts with silicon in the gate electrode 11 and the silicon single crystal layer 5 to form silicide films 31, 32, 33 in a self-aligned manner in the gate region, the source region, and the drain region, respectively. (Film thickness 30 nm) is formed (FIG. 8). These silicide films 31, 32, and 33 have a high-resistance crystal structure C49.

[Step 1-4] The titanium nitride film 23 and the unreacted titanium film 21 are removed by a mixed solution of ammonia water and hydrogen peroxide solution (FIG. 9).

[Step 1-5] A second heat treatment (850 ° C.) is performed. As a result, the silicide films 31, 32, and 33 having the high-resistance crystal structure C49 respectively undergo phase transition to the silicide films 41, 42, and 43 having the low-resistance crystal structure C54 (FIG. 10). Since the thickness of the silicide films 42 and 43 formed in the source region and the drain region is 30 nm, even if the thickness of the silicon single crystal layer 5 is 50 nm, the bottom of the silicide films 42 and 43 is the silicon oxide film. 3 is not in contact with the upper surface.

[Step 1-6] After that, an MOS transistor is completed by forming an insulating film, a contact hole, a metal wiring, and the like.

  According to the above steps 1-1 to 1-6, low resistance silicide films 41, 42, and 43 are formed in the gate region, the source region, and the drain region. These silicide films 41, 42, and 43 have a sheet resistance of 10Ω / sq. As shown in FIG. In addition, the sheet resistance of the silicide films 41, 42, and 43 is substantially constant even if the pattern width changes (the pattern width dependency is extremely small). Therefore, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, it is possible to apply the salicide process even to a fully depleted SOI device. For reference, a characteristic curve of a silicide film (thickness 30 nm) formed by the prior art is shown in FIG. According to the prior art, the sheet resistance is 100Ω / sq. It can be seen that the silicide film is not at a practical level.

By the way, it is also possible to employ argon ions instead of arsenic ions as ions implanted into the entire surface of the SOI substrate in step 1-1. When argon ions are selected, the ion implantation conditions are, for example, an energy of 15 keV and a dose of 5 × 10 ¹⁴ cm ⁻² . As a result, the region from the exposed surface to a predetermined depth of the silicon single crystal layer 5 is amorphized.

  Advantages of using argon ions instead of arsenic ions are as follows. Arsenic ions become N-type impurities when implanted into the silicon single crystal layer 5. When an N-channel transistor is formed, there is no particular problem, but when a P-channel transistor is formed, an impurity diffusion layer is present if an N-type impurity exists in the impurity diffusion layer (source region, drain region). The resistance value of the transistor becomes large, which is not preferable in terms of transistor characteristics. In this regard, argon ions are unlikely to become either P-type impurities or N-type impurities even when implanted into the silicon single crystal layer 5. Therefore, if argon is selected as an ion to be implanted into the silicon single crystal layer 5, the resistance value of the impurity diffusion layer does not increase regardless of whether a P-channel transistor or an N-channel transistor is manufactured. . As a result, low loss and high speed operation of the transistor is realized.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, this invention is not limited to this example. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are of course within the technical scope of the present invention. Understood.

  For example, although the embodiment of the present invention has been described in connection with the case where the metal film (titanium film 21) is formed of titanium, the metal film may be formed using cobalt or nickel. In addition to the titanium nitride film 23, a tungsten film may be used as a protective film for preventing oxidation of the metal film.

It is sectional drawing (1) which shows the basic manufacturing method of the transistor which has a silicide film | membrane. It is sectional drawing (2) which shows the basic manufacturing method of the transistor which has a silicide film | membrane. It is sectional drawing (3) which shows the basic manufacturing method of the transistor which has a silicide film | membrane. It is sectional drawing (4) which shows the basic manufacturing method of the transistor which has a silicide film | membrane. It is sectional drawing (5) which shows the basic manufacturing method of the transistor which has a silicide film | membrane. It is sectional drawing (1) which shows the manufacturing method of the transistor which has a silicide film | membrane concerning embodiment of this invention. It is sectional drawing (2) which shows the manufacturing method of the transistor which has a silicide film | membrane concerning embodiment of this invention. It is sectional drawing (3) which shows the manufacturing method of the transistor which has a silicide film | membrane concerning embodiment of this invention. It is sectional drawing (4) which shows the manufacturing method of the transistor which has a silicide film | membrane concerning embodiment of this invention. It is sectional drawing (5) which shows the manufacturing method of the transistor which has a silicide film | membrane concerning embodiment of this invention. It is a schematic diagram for demonstrating the difference of various sputtering methods. It is a characteristic curve figure which shows the X-ray-diffraction result of a titanium film. It is a characteristic curve figure which shows the pattern width dependence of the sheet resistance of a silicide film | membrane. It is sectional drawing which shows the manufacturing method of the transistor which has a silicide film | membrane concerning other embodiment of this invention.

Explanation of symbols

1: Silicon substrate 3: Silicon oxide film 5: Silicon single crystal layer 7: Element isolation film 9: Gate oxide film 11: Gate electrode 13: Side wall 21: Titanium film 23: Titanium nitride films 31, 32, 33: Silicide film 41, 42, 43: Silicide film

Claims (11)

A silicide film forming method for forming a silicide film on the surface of a silicon region having a thickness of 50 nm or less,
The silicide film is
Ions are implanted into the silicon region to make the surface of the silicon region amorphous, and after adjusting the silicon region to a first temperature, a metal film (film thickness t1) and the metal film are exposed to the silicon region. A protective film (thickness t2, t2> t1) is formed continuously, and further, a second temperature higher than the first temperature with respect to the metal film, the protective film, and the silicon region. A method for forming a silicide film, wherein the silicide film is formed by reacting the metal contained in the metal film with the silicon contained in the silicon region. 2. The method of forming a silicide film according to claim 1, wherein the ions implanted into the silicon region are argon ions. 3. The method of forming a silicide film according to claim 1, wherein the first temperature adjusted when forming the metal film is any one of 200 ° C. to 400 ° C. 4. The method for forming a silicide film according to claim 1, wherein the metal film is formed by a long throw sputtering method or a collimated sputtering method. The method for forming a silicide film according to claim 1, wherein the metal is titanium, cobalt, or nickel. The method for forming a silicide film according to claim 1, wherein the silicon region is thicker than the metal film. The method for forming a silicide film according to claim 1, wherein the protective film contains titanium nitride or tungsten as a main component. The method for forming a silicide film according to claim 1, wherein a film thickness t <b> 1 of the metal film is 15 nm or less. The method for forming a silicide film according to claim 1, wherein a thickness t2 of the protective film is 30 nm or more. The silicon region includes a source region and a drain region,
The method for forming a silicide film according to claim 1, wherein a gate electrode is formed on the silicon region. 11. The method of forming a silicide film according to claim 1, wherein the silicon region is a silicon single crystal layer formed on an insulating film in a substrate having an SOI structure.

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