JPH11186907A - Frequency synthesizer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a frequency synthesizer circuit by adding a counter as the components of a conventional frequency synthesizer so that a variable range of a frequency oscillated by VCO is limited within an operating range of a PLL circuit, thereby reducing the number of VCOs and filter circuits. SOLUTION: A phase detector 12 of the frequency synthesizer circuit detects a phase, based on a signal resulting from frequency-dividing (1/a) a reference frequency f0 at a first counter 14. A signal resulting from frequency-dividing (1/b) an oscillated frequency obtained from a voltage controlled oscillator 11 by a second counter 15 is fed back to the voltage controlled oscillator 11, so that the frequency oscillated in the voltage controlled oscillator 11 is equal to (b/a) f0 . A third counter 16 having a frequency division ratio optimal for setting the variable range of the oscillation frequency of the voltage controlled oscillator 11 within a range from 1/2 to 1 is interposed between a second counter 15 and the voltage controlled oscillator 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention particularly relates to a frequency synthesizer circuit used in the field of wireless communication.

[0002]

2. Description of the Related Art In the field of radio communication equipment, a local oscillator circuit is generally a frequency synthesizer using a PLL (Phase Locked Loop). By configuring the frequency synthesizer with the PLL, the frequency of many channels can be easily switched with one reference oscillator.

As shown in FIG. 3, a PLL circuit basically includes a voltage controlled oscillator 31 (VCO).
ed Oscillator), phase detector 32 (Phase Detecto)
r) and a low-pass filter 33 (Low Pass Filter).

In the example shown in FIG. 3, phase detection is performed on a signal obtained by dividing the reference frequency fo into 1 / a by the counter 34 and a signal obtained by dividing the oscillation frequency by the VCO 31 into 1 / b by the counter 35. In this method, feedback is performed so that the oscillation frequency of the VCO 31 becomes (b / a) × fo. Here, the values of a and b are arbitrary (however, b /
By setting a ≦ 1), an appropriate frequency can be generated.

The conventional example shown in FIG. 3 is used when the output frequency is constant. As described above, when the output frequency is one or the variable range of the output frequency is small, such a circuit configuration is used. However, when the output frequency is greatly different or the output frequency variable range is increased, a plurality of VCOs and filters are provided as shown in FIG. 4 (in the example shown in FIG. 4, the VCO 31n and the filter 31n are provided).
Need to be prepared). In this example, 2
The output frequency is determined by setting the frequency division ratio of the three counters 34 and 35, and at the same time, the VCOs 31,.
1n, filters 33,... 33n are selected. As a result, the output frequency fn becomes (bn / an) fo. As described above, when the output frequency range is wide, a plurality of VCOs and filters are required as shown in FIG.

[0006]

Empirically, the variable range of the output frequency can be realized up to a high frequency / low frequency ≦ 3, but if the variable range becomes wider than that, the filter characteristic of the feedback circuit becomes wider. Since the setting cannot be properly made over the whole, it cannot be realized by one VCO.
The VCO and the filter circuit make it difficult to adjust the frequency characteristics and gain, and not only take time to adjust, but also increase the number of components, resulting in an increase in cost.

The present invention has been made in view of the above circumstances, and by adding a small amount of hardware to the components of a frequency synthesizer conventionally, it is possible to vary the oscillation frequency of a VCO even when the output frequency range is wide. An object of the present invention is to provide a frequency synthesizer circuit in which the range can be suppressed within a range in which a PLL circuit operates and the number of VCOs can be reduced.

[0008]

According to the frequency synthesizer circuit of the present invention, a signal obtained by dividing a reference frequency (fo) by a first counter (1 / a) and an oscillating frequency by a voltage controlled oscillator are used. The phase detection is performed by the signal divided (1 / b) by the counter 2 and feedback is performed so that the oscillation frequency of the voltage controlled oscillator becomes (b / a) fo. A third counter having an optimum frequency division ratio for specifying the variable range of the frequency in a range from 1/2 to 1 is interposed between the second counter and the voltage controlled oscillator. Also, the third
The frequency division ratio of the counter is 1 ≧ (b / a) × 2 × X ≧ 1
/ 2 is also set.

As a result, the number of VCOs and filter circuits can be reduced, so that the time required for adjustment can be reduced. In addition, since the number of components is reduced, the board area for mounting components is reduced, and layout design is facilitated. Cost reduction can be expected.

[0010]

FIG. 1 is a block diagram showing an embodiment of the present invention.

In the drawing, reference numeral 11 denotes a VCO, and reference numeral 12 denotes a VCO.
Is a phase detector, 13 is a low-pass filter, 14 and 1
Reference numeral 5 denotes a counter, which is a basic component of a conventional frequency synthesizer. That is, a signal obtained by dividing the reference frequency fo into 1 / a by the counter 14 and V
The oscillation frequency of CO11 is calculated as 1 / b
, And performs feedback so that the oscillation frequency of the VCO 11 becomes (b / a) × fo. In the present invention, furthermore, a counter 16 of 2 X (1 / n) is additionally connected between the phase detector 12 and the counter 15, so that the oscillation frequency of the VCO 11 is higher / lower frequency ≦ 2. Even if the output frequency is set over a wide range, one VCO 1
1 is configured to be able to handle.

The operation will be described below.

Here, when 1 ≧ b / a ≧ 1/2, 1
/ N, the frequency division ratio of the counter 16 is 1, 1/2> b / a ≧ 1
At / 4, the frequency division ratio of the 1 / n counter 16 is set to 1/2. Similarly, multiplying b / a by 2 to the power of X gives 1 ≧ (b / a)
The frequency division ratio of the 1 / n counter 16 is determined so that × 2 × power ≧ 1/2. The division ratio of the 1 / n counter 16 is b /
The value is set under the above conditions according to the value of a.

Thus, the output frequency f becomes f = (n ×
b / a) fo, but the oscillation frequency of the VCO 11 is f ×
The division ratio of the X counter 16 is obtained, and always 1 ≧ VCO11
Oscillating frequency ≧ 1/2, and one VCO 11 can perform wide frequency conversion.

When b / a is smaller than 1/2, the oscillation frequency range of the VCO 11 can be narrowed if the 1 / n counter 16 uses an appropriate frequency division ratio instead of 2 to the power of X. When b / a is larger than 1/2 and there is no value near 1/2, the oscillation frequency of the VCO 11 is similarly determined by using an appropriate frequency division ratio other than 2 to the power of n. Can be narrowed. Empirically, high frequency / low frequency ≧
A value of 3 is feasible, but the closer this ratio is to 1, the higher the stability and the easier the design.

FIG. 2 shows 1/20 to 20/2 of the reference frequency fo.
5 is a table showing the relationship between the 1 / n counter 16 and the frequency of the VCO 11 when generating a frequency f of 0. As is clear from the table, the output frequency is (high frequency / low frequency) = 20, but the oscillation frequency of the VCO 11 is (high frequency / low frequency) = 1 / 0.55 = about 1.8, This can be realized by one VCO.

As described above, the frequency synthesizer of the present invention uses the signal obtained by dividing (1 / a) the reference frequency (fo) by the first counter and the oscillation frequency of the voltage controlled oscillator in the second frequency. Phase detection is performed by the signal divided by the counter (1 / b), and the feedback is performed so that the oscillation frequency of the voltage controlled oscillator becomes (b / a) fo. A third counter having an optimum frequency division ratio for specifying the range from 1/2 to 1 is interposed between the second counter and the voltage controlled oscillator. When the output frequency is set widely, the number of parts can be reduced.

[0018]

According to the present invention, by adding a counter to the conventional components of a frequency synthesizer, even if the output frequency range is wide, the VCO
Can be suppressed within the range in which the PLL circuit operates, and the number of VCOs and the number of filter circuits can be reduced. As a result, the adjustment time can be reduced, the price can be reduced, the reliability can be improved, and further, the layout design can be simplified due to the reduced component mounting density.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 2 shows an output frequency, a division ratio of a counter, and a VCO.
Diagram showing the relationship with frequency in a table format,

FIG. 3 is a diagram showing a configuration of a first conventional example of a frequency synthesizer;

FIG. 4 is a diagram showing a configuration of a conventional example 2 of a frequency synthesizer;

[Explanation of symbols]

11: voltage controlled oscillator (VCO), 12: phase detector,
13 low-pass filter, 14 1 / a counter, 15 1
/ B counter, 16 ... 1 / n counter

Claims (2)

[Claims] 1. A signal obtained by dividing a reference frequency (fo) by a first counter (1 / a) by a first counter and an oscillation frequency by a voltage control oscillator are divided by a second counter (1 / b). The signal is subjected to phase detection, and the feedback control is performed so that the oscillation frequency of the voltage controlled oscillator becomes (b / a) fo. The variable range of the oscillation frequency of the voltage controlled oscillator is specified in the range of 1/2 to 1. A frequency synthesizer circuit, wherein a third counter having an optimum frequency division ratio is inserted between the second counter and the voltage controlled oscillator. 2. The division ratio of the third counter is 1 ≧
2. The frequency synthesizer circuit according to claim 1, wherein (b / a) .times.2 raised to the power of X.gtoreq.1 / 2.