JPH11186318A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the expansion of a bump in the lateral direction in the bump connection, and reduce the electrode part size by arranging divided bumps so as to be separated by a specific distance from the edge of an aperture part. SOLUTION: An electrode part 12 and a protective film 13 are formed on a semiconductor chip 11. A bump 15 composed of conductive material is formed as a block on a board wiring of a board 14 arranged facing the chip. Bump segments 16 which are divided into small parts are formed on the electrode part 12. The bump segments 16 are arranged in a matrix form having specific intervals in the longitudinal and the transversal directions, while being separated by a specific distance from the edge of an aperture part 12a on the electrode part 12. After the semiconductor chip 11 has been aligned with board 14, by giving heat, load and ultrasonic wave energies are applied to the board, the bump 15 and the bump segments 16 are welded and are made into an unified body. In this case, gaps exist between bump segments 16, so that the welded and unified volume can be reduced as compared with that in the case that the bump segments 16 are made as a block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor device in which a semiconductor chip and a substrate are connected by a wireless bonding method.

[0002]

2. Description of the Related Art Conventionally, as a bonding method of a semiconductor device, a wire bonding method in which a thin wire is connected between an electrode portion (bonding pad) on a semiconductor chip and an external lead, and a method of facing an electrode portion on a semiconductor chip. There is a wireless bonding method in which an electrode terminal on a substrate is connected to a metal block called a bump.

FIG. 5 is an explanatory diagram of a semiconductor device using a conventional wireless bonding method. FIG. 5 shows one of the assembling processes, in which (a) is a schematic sectional view,
(B) has shown the schematic plan view when it looked from arrow A, respectively. In FIG. 5, an electrode portion 2 and a protective film 3 covering the outer periphery thereof are formed on a semiconductor chip 1, and a substrate wiring (not shown) is formed on a substrate 4 which is disposed to face the electrode portion. On the electrode portion 2 and a substrate wiring (not shown),
Bumps 5 made of a conductive material (PbSn, Au, etc.),
6 are formed as a single unit. When the semiconductor chip 1 on which such bumps are formed is aligned with the substrate 4 and heat, load and ultrasonic energy are applied, the bumps 5 and 6 are welded to each other and integrated, and the semiconductor chip 1 and the substrate 4 are integrated. 4 are electrically connected.

[0004]

In the conventional bump shape as described above, as shown in FIG. 6, the bumps 5 + 6 welded at the time of bump connection swell in the horizontal direction, and the stress area on the semiconductor chip 1 increases. Would. For this reason, the electrode section 2
If the size of the bump is smaller than the swollen bump, the protective film 3 formed on the outer periphery of the electrode portion may be damaged, and further, a crack may be generated on the silicon substrate on the chip side, which may cause a malfunction. In the drawing, B indicates a range where stress is applied.

Conventionally, in order to eliminate such an adverse effect on the protective film and the substrate, the size of the electrode portion 2 has been set in consideration of the size of the opening 2a. For example, when one side of the opening 2a of the electrode portion 2 is 90 μm, the length of one side of the electrode portion 2 is set to 100 μm, which is obtained by adding 5 μm required as an overlap portion with the protective film 3.

Incidentally, in recent years, high integration of semiconductor devices,
The reduction in size has progressed rapidly, and the increase in the number of signals due to the increase in the number of bits has increased the number of electrode portions on a semiconductor device, and the influence on the size cannot be ignored. That is, at present, it is required to reduce the size of the electrode unit. It is not technically difficult to reduce the size of the electrode portion. For example, when one side of the opening 2a of the electrode portion 2 is 50 μm as shown in FIG. The length of one side of the electrode portion 2 can be 60 μm, which is obtained by adding 5 μm. In this case, the length of one side of the electrode portion is 10
The size occupation ratio can be reduced to 36% as compared with the case of 0 μm. Also, the amount of the bumps 5 and 6 can be reduced.

However, even if the size of the electrode portion 2 is reduced, the bumps 5 + 6 swell in the horizontal direction at the time of bump connection as in the case of FIG. 6, so that damage to the protective film and the substrate must be avoided. Also, the length of one side of the electrode portion needs to be about 100 μm.

[0008] As a prior art related to such a bump structure, for example, Japanese Patent Application Laid-Open Nos. 59-232432 and 55-8044 disclose a semiconductor device in which the surface of a bonding pad is divided and formed. Japanese Unexamined Patent Publication No. Hei 5-13418 proposes a semiconductor device in which a plating layer inside a bump is divided into required shapes. Japanese Patent Application Laid-Open No. Sho 60-7758 proposes a semiconductor device in which a lower layer portion of a bump is divided into a plurality of small bumps and an upper layer portion is integrated. Furthermore, Japanese Patent Application Laid-Open Nos. Hei 7-58112 and Hei 3-56136 propose semiconductor devices in which bumps on electrode portions are separately formed.

[0009] However, Japanese Patent Application Laid-Open No.
The semiconductor device proposed in Japanese Unexamined Patent Application Publication No. 55-8044 relates to the structure of a bonding pad (electrode portion), and the effect of a bump formed on the bonding pad swelling in the lateral direction due to welding. Is not considered at all. Similarly, JP-A-5-13418
In the semiconductor device proposed in the above publication, no consideration is given to the effect of the case where the bump formed on the plating layer divided and formed on the bonding pad expands in the horizontal direction. Therefore, in these semiconductor devices, it has been difficult to reduce the size of the electrode portion.

In the semiconductor device proposed in Japanese Patent Application Laid-Open No. Sho 60-7758, local stress concentration is avoided, but the effect of bumps bulging in the horizontal direction is not taken into account. It was difficult to reduce the size of the part. Further, JP-A-5-13418, JP-A-7-58112, and JP-A-3-56.
In the semiconductor device proposed in Japanese Patent Publication No. 136, although the swelling of the bump in the horizontal direction is reduced, the divided bump is formed along the edge of the opening, so that the edge of the swelling bump corresponds to the outer periphery of the electrode portion. There is a risk of damaging the protective film formed on the substrate.

Japanese Utility Model Laid-Open Publication No. 3-56136 discloses another example in which a gold bump is formed at a position separated by a predetermined distance from an end of a pedestal. However, in this case, the prisms forming the gold bumps and the prisms disclosed in Japanese Patent Application Laid-Open Nos.
The divided bumps proposed in JP-A-8112 are
Since both are arranged in a matrix when viewed in a plan view, there is a problem that nests are easily generated in the bumps when the bumps are integrated.

A first object of the present invention is to provide a semiconductor device which can be reduced in size without damaging a protective film or a silicon substrate.

It is a second object of the present invention to provide a semiconductor device in which no burrs are formed inside a bump, in addition to the first object.

[0014]

According to a first aspect of the present invention, there is provided a semiconductor device in which a bump divided into small pieces is arranged on an opening of an electrode portion of a semiconductor chip. The divided bumps are arranged at a predetermined distance from an end of the opening.

In order to achieve the second object, a semiconductor device according to a second aspect is characterized in that the divided bumps are arranged in a staggered manner in a plane.

[0016]

Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram of a semiconductor device according to this embodiment. 1A and 1B show one of the assembling processes. FIG. 1A is a schematic sectional view, and FIG. 1B is a schematic plan view as viewed from an arrow A. In FIG. 1, an electrode portion 12 and a protective film 13 are formed on a semiconductor chip 11, and a substrate wiring (not shown) is formed on a substrate 14 arranged to face the semiconductor chip 11. The substrate 1
On the substrate wiring of No. 4, bumps 15 made of a conductive material are formed as a single lump. On the other hand, a plurality of bumps 16 divided into small pieces
Are formed. The plurality of bump pieces 16 are shown in FIG.
As shown in the schematic plan view of (b), they are arranged in a matrix at predetermined intervals both vertically and horizontally, and are arranged at a predetermined distance from the end of the opening 12a on the electrode section 12.

Here, an example of the arrangement of the bumps 16 is shown in FIG. FIG. 2 is a schematic plan view corresponding to FIG.
Equivalent parts are indicated by the same reference numerals. Also, in FIG.
The figure shows a state in which a total of 12 bumps of rows × six rows are arranged. As shown in FIG. 2, one side of the opening 12a is 5
In the case of 0 μm, the length of one side of the electrode portion 12 can be set to 60 μm including 5 μm required as an overlapping portion with the protective film 13. Although the dimensions of each part are shown as an example, the width of one bump is set to 5 μm.
, At least 5 μm from the end of the opening 12a.
It is preferable that they are arranged apart from each other.

In the configuration shown in FIG. 1, when the semiconductor chip 11 and the substrate 14 are aligned and then heat, load and ultrasonic energy are applied, the bumps 15 and 16 are welded to each other and integrated. At this time, since there is a gap between the bumps 16, the volume when the adjacent bumps 16 are welded and integrated is smaller than when the bumps 16 are formed into a single lump. . Moreover, since the bumps 16 are arranged at a predetermined distance from the end of the opening 12a, the swelling of the integrated bumps 15 + 16 in the lateral direction greatly exceeds the width of the electrode portion 12 as shown in FIG. Never. Therefore, the bumps 15 + 16 integrated by welding do not damage the protective film 13 formed on the outer periphery of the electrode portion, and further, do not cause cracks on the silicon substrate on the chip side.

According to the above configuration, the swelling of the bumps 15 + 16 integrated by welding can be reduced in the lateral direction, so that the length of one side of the electrode portion 12 can be reduced to avoid damage to the protective film and the substrate. Is not required to be increased, so that the size of the electrode section 12 can be reduced.

When heat, load, or the like is applied to the bumps 16 divided into small pieces, the bumps 16 are deformed while spreading concentrically in a plane, and gradually become adjacent to the bumps 1.
Unify while melting with each other. At this time, if the bumps 16 are arranged in a matrix, a gap is formed in a central portion between the bumps (for example, a portion indicated by C in FIG. 1).
Even when the entire bump is integrated, nests may be generated inside the bump.

FIG. 4 shows another embodiment of the bump arrangement for solving this problem. As shown in FIG.
Are arranged in a zigzag pattern in the plane, the central part between the bumps,
That is, since the bump 16 is present in a portion corresponding to C in FIG. 1, even when the bump 16 is deformed while expanding concentrically in a plane, no gap is formed in the central portion between the bumps. The occurrence of nests inside the bumps when the bumps are integrated can be prevented.

In the above embodiment, an example in which the shape of the bump is a quadrangular prism as shown in FIG. 1B has been described. However, the bump is formed of a circular column, a triangular column, or another prism having a polygonal shape. It may be.

[0024]

As described above, in the semiconductor device according to the first and second aspects of the present invention, the divided bumps are arranged at a predetermined distance from the end of the opening. The swelling of the bump in the lateral direction is reduced, and the width of the bump does not greatly exceed the width of the electrode portion. Therefore, it is not necessary to increase the length of one side of the electrode portion in order to avoid damage to the protective film and the substrate, so that the size of the electrode portion can be reduced.

In particular, in the semiconductor device according to the second aspect, since the bumps are arranged in a staggered manner in a plane, no gap is formed at the center between the bumps when the bumps are connected, and the bumps are integrated. In this case, the occurrence of nests inside the bumps can be prevented.

[Brief description of the drawings]

FIG. 1A is a schematic cross-sectional view of a semiconductor device according to an embodiment, and FIG. 1B is a schematic plan view when viewed from an arrow A.

FIG. 2 is a schematic plan view showing an example of the arrangement of bumps.

FIG. 3 is a schematic cross-sectional view showing a state where bumps are integrated by bump connection.

FIG. 4 is a schematic plan view when the bumps are arranged in a staggered manner.

5A is a schematic cross-sectional view of a conventional semiconductor device, and FIG. 5B is a schematic plan view when viewed from an arrow A.

FIG. 6 is a schematic cross-sectional view showing a state where bumps are integrated by bump connection.

FIG. 7 is a schematic cross-sectional view showing a bump when the size of an electrode portion is reduced in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Semiconductor chip 12 Electrode part (bonding pad) 12a Opening 13 Protective film 14 Substrate 15, 16 Bump

Claims (2)

[Claims] 1. A semiconductor device in which a bump divided into small pieces is arranged on an opening of an electrode portion of a semiconductor chip, wherein the divided bump is arranged at a predetermined distance from an end of the opening. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the divided bumps are arranged in a staggered manner in a plane.