JPH11185495A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage of which a subtle cutting failure of a fuse can be detected when cutting the fuse for replacing a redundant address. SOLUTION: A fuse 12 for testing is provided which is wider than a fuse 14 for setting used for replacing an address normally. The fuse 12 testing is cut when the fuse for setting is cut, and the cutting of the fuse 12 for testing is confirmed when operation is confirmed. The fuse 12 for testing has a small cutting margin, thus easily detecting cutting failure when a subtle cutting failure is generated by the position deviation of the fuse 14 for setting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a fuse that can be cut from the outside by using a laser beam or the like.

[0002]

2. Description of the Related Art In recent years, as the capacity of semiconductor memory devices has increased, a spare sub-array has generally been provided on a chip so that even if a defect occurs in a part of a memory cell array, it can be remedied. It has become. A plurality of fuses are provided on the semiconductor memory device, and the fuse corresponding to the defective address is selectively cut with a laser beam or the like, thereby replacing the spare sub-array with a part of the defective memory cell array. .

Hereinafter, replacement of the redundant circuit will be described. FIG. 11 is a circuit diagram showing a replacement control circuit section of a conventional semiconductor memory device.

Referring to FIG. 11, a replacement control circuit portion of a conventional semiconductor memory device receives a charge node N3, a precharge signal / PC at its gate, a power supply node and a charge node N3.
And a pre-decode signal ADR0, / ADR0, ADR1, / ADR1
And a fuse group 114 connecting the address decode circuit 116 and the charging node N3.

Address decode circuit 116 has an N-channel transistor 132 having a gate receiving predecode signal ADR1 and having a source connected to the ground node, and an N channel transistor having a gate receiving predecode signal ADR0 and connected in series with N channel transistor 132. Channel transistor 1
30 and an N-channel transistor 1 having a gate receiving predecode signal ADR1 and having a source connected to the ground node.
36 and the predecode signal / ADR0
An N-channel transistor 134 connected in series with a channel transistor 136;
An N-channel transistor 140 whose source is connected to the ground node and a precharge signal ADR
0, the N-channel transistor 138 connected in series with the N-channel transistor 140, the N-channel transistor 144 having the gate receiving the predecode signal / ADR1, the source connected to the ground node, and the predecode signal / ADR0. An N-channel transistor 142 connected in series with a receiving N-channel transistor 144 at the gate is included.

The fuse group 114 includes a fuse 122 connecting the drain of the N-channel transistor 130 to the charging node N3, a fuse 124 connecting the drain of the N-channel transistor 134 to the charging node N3, and a drain connecting the N-channel transistor 138. Node N3
And a fuse 128 connecting the drain of the N-channel transistor 142 and the charging node N3.

If none of the fuses 122 to 128 has been blown, the predecode signals ADR0, / A
When DR0, ADR1, and / ADR1 become inputs corresponding to memory access, the potential of the charging node N3 becomes low (L) level, and replacement of the redundant circuit is not performed.

If any one of fuses 122 to 128 is blown, after completion of charging of node N3 by precharge signal / PC, predecode signals ADR0, / DR0
When ADR0, ADR1, and / ADR1 become inputs corresponding to the replacement address, a high (H) level output signal OUT is output from the charging node N3. Then, the replacement of the redundant circuit is performed.

The method of cutting the fuses 122 to 128 for relief is not particularly limited as long as the beam has energy, but a method of cutting the wiring using a laser beam is often used. However, even if the irradiation position of the laser beam is slightly deviated, there is a possibility that a defective fuse is cut.

FIG. 12 is a diagram for explaining a state at the time of defective disconnection of a fuse. Referring to FIG. 12, in this figure, wirings 176 and 178 formed by the second wiring layer
172 formed by a cutting wiring layer
The wiring 176 and the fuse part 172 are connected by a contact 180, and the wiring 178 and the fuse part 172 are connected by a contact 182.

When the fuse portion 172 is cut by a laser beam, a positional shift occurs, and a laser spot 174 is formed.
Are shifted from the central portion of the fuse portion 172. Due to this shift, the fuse portion 172 is not completely cut, and a thin wiring layer for cutting remains. The remaining thin wiring layer may cause a leak failure at the charging node.

FIG. 13 is an operation waveform diagram for explaining the operation of the conventional redundant circuit. Referring to FIGS. 11, 12, and 13, at time t1, precharge signal / PC falls from H level to L level. Thereby, the charging node N
The potential of the output signal OUT output from 3 starts rising from L level to H level.

At time t2, after charging of charging node N3 is completed and output signal OUT attains H level, precharge signal / PC rises from L level to H level.

Next, at time t3, a predecode signal is input to the redundant circuit portion in response to an external access to the memory cell. In the case of FIG. 13, the predecode signal ADR0 goes high and the predecode ADR1 goes low.
Indicates a level. When the fuse is not blown, N-channel transistors 138 and 140 are turned on at time t3 in accordance with the input of the predecode signal. Then, the potential of the charging node N3 is H via the fuse 126.
The level is lowered from the level to the L level, and the output signal OUT falls from the H level to the L level as shown in a waveform B.

On the other hand, considering that a failure occurs in a corresponding memory cell array and fuse 126 is cut to replace a memory cell array portion corresponding to this address with a redundant circuit portion, N channels 138 and 140 are turned on. The charging node N3 is the N-channel transistor 1
38 and 140 are separated by cutting the fuse 126, so that the output signal OUT maintains the state shown in the waveform A while keeping the H level.

At time t4, the input of the predecode signal ends, and all the predecode signals become L level.

At time t5, the output signal OUT
A predetermined circuit in the receiving chip determines whether or not to replace the corresponding address. When the output signal OUT is at L level, the corresponding address is not replaced, and when the output signal OUT is at H level, the corresponding address is replaced.

Here, as shown in FIG. 11, considering the case where the disconnection of the fuse portion is insufficient due to the positional deviation, the discharge of the charging node N3 occurs at time t3 in an incomplete connection state. As shown in the waveform C, the level of the output signal OUT is the waveform B when the level is not disconnected.
It falls to the L level in a state where extra time is required.

In this case, at time t5, the output signal OUT
Is determined whether or not to replace the address. However, since the potential of the output signal OUT is at an intermediate level, it may be recognized as H level or L level depending on the operating conditions. At present, addresses are normally replaced during a normal test, but when operating conditions deteriorate, the address may not be replaced and a malfunction may occur. There is a problem that it is necessary to take measures such as lengthening the waiting time after charging.

[0020]

As described above,
In the replacement control circuit in the conventional semiconductor memory device, when the fuse is not sufficiently cut as shown in FIG. 12, the potential of the charging node becomes an incomplete value. Therefore, even if the operation is normal at the time of confirming the operation under normal conditions, the replacement of the redundant circuit does not work properly and malfunctions depending on the operation conditions. It took a lot.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of easily detecting a disconnection failure when a fuse is short-circuited in a state where a fuse for replacement in a redundant circuit is insufficiently cut and a minute leak remains. It is to provide a storage device.

[0022]

According to a first aspect of the present invention, there is provided a semiconductor memory device including replacement control means for instructing replacement of a defective address with a redundant address, the replacement control means for setting a defective address to be replaced. An output terminal including a fuse, for outputting a test output signal to the outside during a test, and first test means for detecting a disconnection of the setting fuse, the first test means outputting a test output signal A first node that conducts according to a precharge period with the test output node and couples the test output node with the first potential;
And a first test fuse which is larger than the setting fuse and couples the test output node to the second potential.

According to a second aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the first aspect, a test output node and a second potential which are arranged in a direction different from that of the first test fuse are provided. And a second test fuse thicker than the setting fuse for coupling the second fuse.

According to a third aspect of the present invention, there is provided a semiconductor memory device including replacement control means for instructing replacement of a defective address with a redundant address, wherein the replacement control means includes a setting fuse for setting a replacement address, and a test output is provided during a test. An output terminal for outputting a signal to the outside; and first test means for detecting a disconnection of the setting fuse, wherein the first test means includes a test output node for outputting a test output signal, and a precharge period. And a first switch for connecting the test output node to the first potential and a first test having a width equal to or less than the width of the setting fuse for connecting the test output node to the second potential. The first test fuse includes a fuse, and the first test fuse is located in a short side direction of the first test fuse from an irradiation target position of a beam irradiated for cutting the fuse. It is arranged offset by a first distance.

According to a fourth aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the third aspect, the first test means connects the test output node and the second potential with each other. A second test fuse having a width equal to or less than the width, wherein the second test fuse has a direction opposite to the first direction by 180 degrees from an irradiation target position of a beam irradiated for fuse cutting. They are displaced by a second distance in the second direction.

According to a fifth aspect of the present invention, in addition to the configuration of the semiconductor memory device according to the third aspect, the first test means includes a test output arranged in a different direction from the first test fuse. And a third test fuse having a width equal to or less than a width of the setting fuse, which couples the node and the second potential, wherein the third test fuse is an irradiation target position of a beam irradiated for cutting the fuse. Are shifted by a third distance in the third direction, which is the short side direction of the third test fuse.

According to a sixth aspect of the present invention, in addition to the configuration of the semiconductor memory device of the first aspect, the semiconductor memory device further includes a second test means for detecting a disconnection of the setting fuse. , A second test means, a second test output node outputting a test output signal, and a second switch means which conducts according to a precharge period and couples the second test output node to the first potential. And a fourth test fuse that couples the second test output node to the second potential and that is arranged at a fixed distance from the first test fuse.

A semiconductor memory device according to a seventh aspect of the present invention includes replacement control means for instructing replacement of a defective address with a redundant address, wherein the replacement control means outputs a signal indicating that the defective address has been input from outside. Decoding means for receiving and decoding an address, a setting fuse for setting a replacement address for connecting the charging node and the decoding means, and charging for charging the charging node for a predetermined time before the address is input Means for setting the charging potential of the charging node in two stages according to an external signal.

According to the semiconductor memory device of the eighth aspect, in addition to the configuration of the semiconductor memory device of the seventh aspect, the charging means includes:
The switch further includes first switch means that conducts in accordance with the precharge period and connects the power supply potential and the setting means, wherein the setting means is non-conductive when the operation is confirmed, and is conductive when the operation is not confirmed. , Voltage drop means connected in parallel with the switch means.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the eighth aspect, the first switch is a first MOS transistor and the second switch is a second MOS transistor. A MOS transistor, and the voltage drop means includes a third MOS transistor having a gate connected to the drain.
It is an S transistor.

[0031]

[First Embodiment] FIG. 1 is a block diagram showing a configuration of a fuse cutting test circuit section in a semiconductor memory device according to a first embodiment of the present invention.

Referring to FIG. 1, a fuse cutting test circuit section includes a test signal TEST and a precharge signal / PC.
Charging circuit 2 that receives a current from a power supply node to charge charging node N1, a test fuse 4 that connects charging node N1 to a ground node, and an output that receives output signal OUT output from charging node N1. Terminal 6.

FIG. 2 is a diagram for comparing and explaining the structures of a test fuse used in the test circuit of FIG. 1 and a normally used replacement fuse.

FIG. 2 shows the test fuse 12 and the setting fuse 14. The size of the laser spot 16 is shown superimposed on the center of the test fuse 12. On the other hand, a laser spot 18 having the same size as the laser spot 16 is superimposed at the center of the setting fuse 14.

The width of the test fuse 12 is wider than that of the setting fuse 14 and is substantially equal in size to the laser spot. Therefore, the margin for displacement is smaller in the test fuse 12 than in the setting fuse 14.

Normally, when a positional shift occurs in the same chip, it is considered that all the shifts of the cut portions of the fuses included in the same chip are substantially equal. Therefore, when a disconnection failure that causes a minute leak in the setting fuse 14 occurs due to a positional deviation, the test fuse 12
Since the portion which remains without being cut is larger than that of the setting fuse 14, the flowing current value is larger than that of the setting fuse.

FIG. 3 is a circuit diagram showing an example of a specific configuration of the charging circuit 2 in FIG. Referring to FIG. 3, charging circuit 2 includes an inverter 32 receiving test signal TEST.
P-channel transistor 34 receiving the output of inverter 32 at its gate and having its source connected to the power supply node, and P-channel transistor 36 receiving its precharge signal / PC at its gate and connecting the drain of P-channel transistor 34 and charging node N1. And

FIG. 4 is an operation waveform diagram for describing a test operation for confirming fuse cutting in the semiconductor memory device of the first embodiment.

Referring to FIGS. 3 and 4, when the setting fuse is cut with a laser to replace the address of the semiconductor memory device, after the chip is aligned on the cutting device, the test fuse is set. 4 is cut. If the alignment is inadequate, the test fuse 4 is made thicker than a normal setting fuse, so that the cutting is insufficient.

After cutting the test fuse and the setting fuse, a test is performed to confirm whether the cutting has been performed normally.

At time t1, test mode signal TES
T goes to H level, and P-channel transistor 34 conducts.

At time t2, precharge signal / PC
Becomes L level. Between time t2 and t3, precharge signal / PC maintains L level. Then, P-channel transistor 36 is rendered conductive only for that section, and charging node N1 is coupled to the power supply node. At time t3, output signal OUT output from charging node N1 is at H level. At time t3, precharge signal / P
C rises from L level to H level. The P-channel transistor 36 is turned off, and the output signal OUT can be maintained at the H level for a long time if the operation of cutting the test fuse 4 is performed normally.

However, if there is an abnormality in the cutting operation and the test fuse 4 is not cut safely and remains thin, the level of OUT gradually decreases and becomes the L level at time t4. By determining the level of the output signal OUT at the time t4, it is possible to detect a cutting abnormality such as a position shift.

During normal operation of the semiconductor memory device, test mode signal TEST is at L level, P-channel transistor 34 is off, and this circuit does not operate and no operating current flows.

As described above, in the semiconductor memory device of the first embodiment, a test fuse thicker than the setting fuse is provided, and when the setting fuse is cut, the test fuse is also cut at the same time. By confirming the disconnection of the test fuse at the time of operation confirmation, it becomes easy to detect a defect in which the disconnection of the setting fuse is insufficient.

[Second Embodiment] FIG. 5 is a diagram showing an arrangement of test fuses used in a semiconductor memory device according to a second embodiment of the present invention.

The semiconductor memory device of the second embodiment differs from the first embodiment in that the structure of the test fuse is a test fuse shown in FIG. 5 instead of the test fuse shown in FIG. In the first embodiment, the detection capability for positional deviation is increased by making the test fuse thicker than the setting fuse. However, even if a fuse having the same thickness as the setting fuse is used, the detection capability for positional deviation is improved. Can be similarly increased.

Referring to FIG. 5, wirings 56 and 58 formed in the second wiring layer are connected to test fuses 52 and 54.
Connected by The wiring 56 and the test fuse 52 are connected by a contact 64, and the wiring 56 and the test fuse 54 are connected by a contact 68. Wiring 5
8 and the test fuse 52 are connected by a contact 66, and the wiring 58 and the test fuse 54 are connected to the contact 7.
Linked by 0. The sizes of the laser spots 60 and 62 are shown at the center of the test fuses 52 and 54, respectively. As can be seen from FIG. 5, the test fuse 52 is provided slightly to the left with respect to the laser spot 60 which is the target cutting value.
Is provided slightly to the right of the laser spot 62 set at the cutting target position. That is, the center line X 'of the test fuse 52 is slightly leftward of the center line X of the laser spot 60, and the center line Y' of the test fuse 54 is formed.
Is slightly to the right of the center line Y of the laser spot 62.

Although not particularly limited, the deviation from the cutting target position such as the center line X of the test fuse 52 as described above is caused by the minimum digit (minimum movement) when the position of the laser spot 62 is digitally set. (Unit).

By arranging the test fuses in this arrangement, the test fuses have a smaller margin for positional deviation at the time of cutting by the laser than the setting fuses, and thus are similar to the case where the fuses are thickened as in the first embodiment. In addition, it is easy to detect a cutting defect with respect to misalignment.

The width of the test fuse may be equal to or smaller than the width of the setting fuse. In this case, the same effect can be obtained by further displacing the arrangement of the test fuse with respect to the laser spot.

Third Embodiment FIG. 6 is a diagram showing a structure of a test fuse used in a semiconductor memory device according to a third embodiment.

The semiconductor memory device of the third embodiment differs from the semiconductor device of the first embodiment in that a test fuse shown in FIG. 6 is used instead of the test fuse shown in FIG.

Referring to FIG. 6, wiring 86 and wiring 88 formed in the second wiring layer are connected by test fuses 82 and 84 formed in the wiring layer for cutting. Wiring 8
6 and the test fuse 82 are connected by a contact 94, and the test fuse 82 and the wiring 88 are connected by a contact 96. The wiring 86 and the test fuse 84 are connected by a contact 98, and the wiring 88 and the test fuse 8 are connected.
4 are connected by a contact 100.

The size of the laser spot 90 is shown at the center of the test fuse 82. The size of the laser spot 92 is shown at the center of the test fuse 84.

In the semiconductor memory devices of the first and second embodiments, the displacement of the test fuse in the short side direction can be detected, but the displacement of the test fuse in the long side direction cannot be detected.

In the semiconductor memory device according to the third embodiment, since the test fuse 84 is further arranged in the short side direction of the test fuse 82, not only a deviation in one direction but also a deviation in any direction can be detected.

FIG. 6 shows an example in which the test fuses are configured with the thick test fuses as described in the first embodiment. However, as described in the second embodiment, the test fuses having a width equal to or less than the width of the setting fuses are used. The same effect can be obtained even if the configuration is adopted.

[Fourth Embodiment] FIG. 7 is a schematic diagram showing an arrangement of test fuses on a chip of a semiconductor memory device according to a fourth embodiment.

When the test fuses provided in the semiconductor memory devices of the first, second and third embodiments are arranged at one place on the chip, the displacement of the test fuse portion can be detected. It is difficult to detect a shift in the rotational direction of the entire chip around the fuse.

This problem can be solved by arranging test fuses at a plurality of locations at a certain interval on the chip. Although not particularly limited, in the case of a quadrangular semiconductor memory device, it is effective and desirable to arrange the semiconductor device at two opposing corners of the chip since the longest interval can be obtained.

Referring to FIG. 7, test fuses are arranged at points A and B in the semiconductor memory device of the fourth embodiment. If a chip that should be at the solid line position P0 in the drawing has a rotational displacement around the point A portion as a whole as shown by the dotted line position P1 in the drawing, the displacement at the point A portion is difficult to detect because the displacement width is small. However, at the point B, the fuse is shifted to the position of the point B ', so that the cutting position of the fuse is also largely shifted from the point A.

Therefore, it is possible to easily detect the displacement of the chip in the rotation direction. [Fifth Embodiment] FIG. 8 is a circuit diagram showing a configuration of a replacement control unit of a redundant circuit used in a semiconductor memory device of a fifth embodiment.

Referring to FIG. 8, the replacement control circuit used in the semiconductor memory device of the fifth embodiment includes a charge node N2
, Precharge signal / PC and test mode signal TES
Charging circuit 112 that charges charging node N2 according to T
And the predecode signals ADR0, / ADR0, ADR
1, an address decode circuit 116 that receives and decodes / ADR1, and a fuse group 114 that also connects the address decode circuit 116 and the charging node N2.

Address decode circuit 116 has an N-channel transistor 132 having a gate receiving predecode signal ADR1 and having a ground node connected to the source, and a drain receiving N-channel transistor 132 having a source receiving predecode signal ADR0 and having the source connected. N-channel transistor 130, N-channel transistor 136 having a gate receiving predecode signal ADR1 and having a source connected to the ground node, and a drain receiving N-channel transistor 136 having a source receiving predecode signal / ADR0 at the gate. An N-channel transistor 134;
N-channel transistor 140 having its gate receiving predecode signal / ADR1 and having its source connected to the ground node
An N-channel transistor 138 whose gate receives predecode signal ADR0 and whose source is connected to N-channel transistor 140; an N-channel transistor 144 whose gate receives predecode signal / ADR1 and whose source is connected to the ground node; Decode signal / ADR0
Is received at the gate and the source is an N-channel transistor 144
-Channel transistor 142 connected to the drain of
And

The fuse group 114 includes a fuse 122 connecting the drain of the N-channel transistor 130 and the charging node N2, a fuse 124 connecting the drain of the N-channel transistor 134 and the charging node N2, and a drain connecting the drain of the N-channel transistor 138. Node N2
And a fuse 128 connecting the drain of the N-channel transistor 142 and the charging node N2.

The charging means 112 outputs the precharge signal / P
A P-channel transistor 118 whose gate receives C and whose source is connected to the power supply node;
A level changing circuit 120 for changing the potential of the charging node at the time of precharging according to T.

FIG. 9 is a circuit diagram showing details of the charging means 112. Charging means 112 includes a P-channel transistor 118 whose gate receives precharge signal / PC and whose source is connected to a power supply node, and a level changing circuit 120.

Level change circuit 120 receives test mode signal TEST at its gate, and outputs a P-channel transistor 118.
And a P-channel transistor 152 having a drain connected to the drain of the P-channel transistor 118 and a gate connecting the drain of the P-channel transistor 118 to the charging node N2.

P-channel transistor 154 plays the role of a diode that lowers the voltage of the charging node by the threshold during testing.

FIG. 10 is an operation waveform diagram for explaining the operation of the redundant circuit portion of FIG. Referring to FIGS. 8, 9, and 10, at time t1, precharge signal / PC falls from H level to L level. In response, the potential of output signal OUT rises from L level to H level.

At this time, when test mode signal TEST is at the L level, that is, during normal operation, P-channel transistor 152 is conductive, and the potential of charging node N2 rises to the power supply potential as shown by waveform C0.

However, when test mode signal TEST is at an H level, that is, when a fuse test is being performed, P channel transistor 152 is turned off, and the potential of charging node N 2 is reduced by the threshold voltage of P channel transistor 154. It becomes lower than the potential.

At time t2, precharge signal / PC
Rise from the L level to the H level.

Between times t3 and t4, a signal corresponding to an externally input address is input to the predecode signal. FIG. 10 shows a case where predecode signal ADR0 is at H level and predecode ADR1 is at L level.

In this case, N-channel transistor 138,
When the fuse 140 is not blown and the fuse 140 is not blown, the potential of the charging node falls from the H level to the L level as shown in a waveform B. When the fuse 126 is blown, the potential of the charging node N2 is maintained at the H level lower than the power supply potential by the threshold value of the P-channel transistor 154, as shown by the waveform A.

Here, consider the case where the fuse 126 is insufficiently cut. In the case of the conventional replacement control circuit unit in which the level change circuit 120 is not provided, the voltage gradually decreases as shown by the waveform C0. On the other hand, the level change circuit 12
In the circuit of the fifth embodiment where 0 is provided, the voltage drops as shown in the waveform C.

That is, the time t when the voltage drop starts
Since the initial voltage level of the charging node at 3 is lower by the threshold value of the P-channel transistor 154, the potential of the charging node becomes L level earlier.

Therefore, when it is determined at time t5 whether the corresponding address is replaced by the fuse group, the probability that the potential of the charging node becomes L level is high, and the possibility of detecting an abnormality is increased.

In normal operation, test mode signal TEST
Is L, the charging potential of the charging node is charged to the power supply potential without being affected by the P-channel transistor 154. That is, in the test, the replacement of the redundant circuit portion is checked under stricter conditions.

In FIG. 9, P-channel transistor 154
Although the voltage drop is realized by the above, an N-channel transistor may be diode-connected and used instead. Further, depending on the magnitude of the threshold voltage of the transistor, it is possible to change the width of the voltage drop without using any number of the diode-connected transistors in series.

Although the test fuse used in the first embodiment can detect a displacement, it cannot detect a sudden disconnection of the setting fuse due to a trouble such as a temporary decrease in laser output. In the semiconductor memory device of the fifth embodiment, by providing a test circuit in the replacement control circuit, it is possible to detect a sudden disconnection abnormality. For example, a case where an abnormality occurs only in a specific setting fuse, a case where the diameter of a cutting spot is temporarily reduced, and the like are considered.

[0083]

According to the semiconductor memory device of the present invention, the test fuse wider than the setting fuse is cut off at the same time when the setting fuse is cut off, and the cutoff of the test fuse is confirmed at the time of confirming the operation. It is possible to easily detect a cutting failure due to a minute leak caused by the displacement.

According to the semiconductor memory device of the second aspect, in addition to the effect of the semiconductor memory device of the first aspect, it is possible to detect not only a positional deviation in one direction but also a positional deviation in any direction. Become.

In the semiconductor memory device according to the third aspect, since the test fuse is provided at a position shifted from the target cutting position, even when the setting fuse has caused a small leak defect due to the position shift, it can be easily detected. It is possible to do.

In the semiconductor memory device according to the fourth aspect, in addition to the effect of the semiconductor memory device according to the third aspect, since the second test fuse is further displaced in the opposite direction from the cutting target position, the second test fuse is provided. Even when a test fuse having the same width as that of the fuse is provided, displacement in two directions can be detected.

According to the fifth aspect of the present invention, in addition to the effect of the third aspect of the present invention, the setting fuse is provided because the second test fuse is provided in a direction different from that of the first test fuse. In any direction can be detected.

In the semiconductor memory device according to the present invention, another test fuse is provided at a predetermined interval in addition to the first test fuse, so that the semiconductor memory device shifts in the rotational direction of the chip. Also makes detection easier.

In the semiconductor memory device according to the seventh, eighth, and ninth aspects, the potential of the charging node is set lower during the test, so that the conditions during the test are more severe than during the normal operation. Can be easily detected. In addition, it is possible to detect not only the disconnection failure due to the positional deviation but also the disconnection failure of the setting fuse for the specific portion temporarily.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a configuration of a fuse cutting test circuit used in a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a view for explaining a structure of a test fuse 4 of FIG. 1;

FIG. 3 is a circuit diagram illustrating details of a charging circuit 2 used in the semiconductor memory device according to the first embodiment;

FIG. 4 is an operation waveform diagram for explaining a change in charging node N1 of FIG. 3;

FIG. 5 is a diagram illustrating a structure of a test fuse used in the semiconductor memory device according to the second embodiment;

FIG. 6 is a diagram illustrating a structure of a test fuse used in the semiconductor memory device according to the third embodiment;

FIG. 7 is a diagram illustrating an arrangement of fuses in a semiconductor memory device according to a fourth embodiment;

FIG. 8 is a circuit diagram of a replacement control circuit unit used in the semiconductor memory device according to the fifth embodiment;

9 is a circuit diagram showing details of a configuration of a charging unit 112 in FIG.

FIG. 10 is an operation waveform diagram showing a change in charging node N2 in FIG.

FIG. 11 is a circuit diagram showing details of a configuration of a replacement control circuit section of a conventional semiconductor memory device.

FIG. 12 is a diagram for explaining a state of a disconnection failure of a fuse portion of a conventional semiconductor memory device.

FIG. 13 is an operation waveform diagram for explaining a state when the replacement fuse 126 in FIG. 11 has a disconnection failure.

[Explanation of symbols]

2 Charging circuit, 4, 52, 54, 82, 84, 12 Test fuse, 14, 122, 124, 126, 12
8 Setting fuse, 32 inverters, 34, 36,
118, 162 P-channel transistor, 112 charging circuit, 120 level change circuit, 130 to 144 N-channel transistor, 114 fuse group, 116 address decode circuit, N1, N2, N3 nodes.

Claims (9)

[Claims] 1. A replacement control means for instructing replacement of a defective address with a redundant address, wherein the replacement control means includes a setting fuse for setting the defective address to be replaced, and externally outputs a test output signal during a test. An output terminal for outputting, and a first test means for detecting a disconnection of the setting fuse, wherein the first test means comprises: a test output node for outputting the test output signal; A first switch unit that is electrically connected to couple the test output node to a first potential, and a first test fuse that is larger than the setting fuse and couples the test output node to a second potential. Including,
Semiconductor storage device. 2. The semiconductor device further includes a second test fuse, which is arranged in a different direction from the first test fuse, and is larger than the setting fuse and couples the test output node with the second potential. The semiconductor memory device according to claim 1. 3. A replacement control means for instructing replacement of a defective address with a redundant address, the replacement control means including a setting fuse for setting a replacement address, and an output for outputting a test output signal to the outside during a test. A terminal; and first test means for detecting a disconnection of the setting fuse, wherein the first test means is electrically connected to a test output node for outputting the test output signal in accordance with a precharge period. First switch means for coupling the test output node to a first potential; and a first test fuse having a width equal to or less than the width of the setting fuse for coupling the test output node to a second potential. Wherein the first test fuse is arranged in a short side direction of the first test fuse from an irradiation target position of a beam irradiated for cutting the fuse. A semiconductor memory device which is arranged to be shifted by a first distance in a certain first direction. 4. The first test means further includes a second test fuse having a width equal to or less than a width of the setting fuse, which couples the test output node with the second potential. The test fuse according to claim 1, wherein the test fuse is displaced by a second distance in a second direction, which is a direction 180 degrees opposite to the first direction, from an irradiation target position of a beam irradiated for fuse cutting. 3. The semiconductor memory device according to 3. 5. The configuration according to claim 1, wherein the first test unit couples the test output node and the second potential, which are arranged in a different direction from the first test fuse, and is equal to or less than a width of the setting fuse. A third test fuse having a width, wherein the third test fuse is located in a short side direction of the third test fuse from an irradiation target position of a beam irradiated for cutting the fuse. 4. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is arranged to be shifted by a third distance in the direction. 6. A second test means for detecting a disconnection of the setting fuse, wherein the second test means comprises: a second test output node for outputting the test output signal; and a precharge period. A second switch means that conducts in response to the second test output node and couples the first potential; and couples the second test output node and a second potential.
The semiconductor memory device according to claim 1, further comprising a fourth test fuse arranged at a predetermined interval from said first test fuse. 7. A replacement control unit for instructing replacement of a defective address with a redundant address, wherein the replacement control unit outputs a signal indicating that the defective address has been input from outside, and receives the address. Decoding means for decoding; a setting fuse for connecting the charging node and the decoding means for setting the replacement address; and a charging means for charging the charging node for a predetermined time before the address is input. A semiconductor memory device, wherein the charging unit includes a setting unit that switches a charging potential of the charging node in two stages according to an external signal. 8. The charging unit further includes a first switch unit that is turned on in accordance with a precharge period and connects a power supply potential and the setting unit. The setting unit is turned off when the operation is confirmed, The semiconductor memory device according to claim 7, further comprising: a second switch unit that is turned on when the operation is not confirmed, and a voltage drop unit that is connected in parallel to the second switch unit. 9. The first switch means comprises a first MO.
9. The semiconductor memory device according to claim 8, wherein said semiconductor memory device is an S transistor, said second switch means is a second MOS transistor, and said voltage drop means comprises a third MOS transistor having a gate connected to a drain. .