JP2005141789A - Prom circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PROM circuit in which inspection of a write state of a fuse element can be performed highly accurately and at high speed. <P>SOLUTION: It is inspected whether write of a fuse element 16 is performed normally or not by providing a write inspection mode, detecting potential difference of an operation amplifier output terminal 24 before and after setting of the write inspection mode, and confirming that inversion of a logic is not performed in an output terminal 12 of the ROM circuit. In the write inspection mode, inspection mode data is inputted to an inspection mode data holding part CM of a logic data latch circuit 26 from a logic data input terminal 25, a mode changeover switch 22 is turned on and a wrote terminal 21 is connected to ground, while an output current of a first current source 13 is controlled so as to decrease, and output voltage of the operation amplifier output terminal 24 is measured. And output voltage measured in the write inspection mode is compared with output voltage measured in a normal mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a PROM circuit including a fuse element.

  Electronic devices such as communication devices include a crystal oscillator that generates a frequency or time reference signal. In particular, a communication device such as a mobile phone requires a small and high-precision crystal oscillator, and an oscillator that can obtain a stable oscillation frequency even with a change in temperature is desired. A TCXO (Temperature Compensated Crystal Oscillator) that does not change is often used.

  The oscillation frequency of the crystal oscillator has a temperature characteristic having a cubic function component caused by the crystal oscillator. By compensating for this temperature characteristic, a highly accurate crystal oscillator is realized. As one of the temperature compensation methods for a temperature compensated crystal oscillator, a variable capacitance diode (varactor diode) is connected as a frequency adjustment element to a VCXO (Voltage Compensated Crystal Oscillator), and the temperature characteristics of the crystal oscillator By preparing a function for temperature compensation with the opposite characteristics and applying a control voltage calculated according to the ambient temperature to the variable capacitance diode based on this function, the frequency variation due to temperature change is less than the specified value. There is a way to compensate so.

  When performing such temperature compensation, coefficients and constants of the respective orders of the temperature compensation function are stored in a PROM (Programmable Read Only Memory) circuit, and values are read from this PROM circuit during operation. A configuration that reads and generates a control voltage is often used. Here, the characteristic variation for each element of the crystal oscillator in the TCXO module can be dealt with by changing the value stored in the PROM circuit. Therefore, in a TCXO module equipped with a PROM circuit, a value adjusted in accordance with the characteristics of each element is written in the PROM circuit at the time of shipment or the like.

  One type of PROM circuit includes a fuse element formed of polysilicon or the like. This type of PROM circuit generates a specified output (high level or low level) for a specific input in accordance with the disconnection state of the fuse element, that is, the electrical disconnection state (short circuit / open state) of the circuit. To work. As a method for cutting the fuse element, at present, a laser beam cutting method for cutting by irradiating a laser beam, or an electric cutting method for cutting by blowing a fusing current are typical. As a PROM circuit using the electric cutting method, for example, there is one described in Japanese Patent Application Laid-Open No. 56-169361 (Patent Document 1).

  Hereinafter, an example of a PROM circuit having a conventional fuse element will be described with reference to FIG. This PROM circuit has a plurality of cells 100 corresponding to each bit of data to be output. In addition, a write terminal 111 and a mode changeover switch 112 for writing to each cell 100 are provided. Each cell 100 includes a power supply terminal 101, an output terminal 102, a first current source 103, a diode 104, a fuse element 105, a P-channel MOS transistor 106, a second current source 107, a write voltage source 108, and a write switch 109. Is provided.

  One end of the first current source 103 and the source of the MOS transistor 106 are connected to the power supply terminal 101, and the gate of the MOS transistor 106 and the anode of the diode 104 are connected to the other end of the first current source 103. The power supply terminal 101 is connected in common with other cells 100. One end of a fuse element 105 and one end of a write switch 109 are connected to the cathode of the diode 104, and a write terminal 111 and a mode changeover switch 112 are connected to the other end of the fuse element 105. The other end of the mode switch 112 is grounded. The write switch 109 is turned on / off by input control logic data, and a write voltage source 108 is connected to the other end. The other end of the write voltage source 108 is grounded. Further, one end of the second current source 107 is connected to the drain of the MOS transistor 106, and the other end of the second current source 107 is connected to the other cell 100 in common.

  In the above configuration, when the fuse element 105 is written, the mode switch 112 is turned off, the logic data for control is input to the cell of the bit to be written, and the write switch 109 is turned on by logic control. A voltage is applied from the write terminal 111 to melt the fuse element 105. Here, when the fuse element 105 is in a conductive state (short circuit state), the current of the first current source 103 flows to the fuse element 105 through the diode 104, and the voltage at the point A becomes equal to or higher than a predetermined gate voltage, so that the MOS transistor 106 Is turned on, and a high level voltage is output to the output terminal 102. In addition, when the fuse element 105 is melted and cut (opened), the fuse element 105 is in a high impedance state, so that only a leak current flows while almost no current from the first current source 103 flows. Therefore, the voltage at the point A becomes less than the predetermined gate voltage, the MOS transistor 106 is turned off, and a low level voltage is output to the output terminal 102. By decoding the output of each cell, it is possible to generate a control data signal composed of a plurality of bits.

  In such a PROM circuit, it is necessary to inspect whether the fuse elements of all bits are in a short-circuited state or an open state at the time of shipment or the like, and whether writing is performed normally and the open state is surely made. . As a conventional inspection method, after the mode changeover switch 112 is turned off and the write terminal 111 is opened from the ground (GND), a voltage is applied to the write terminal 111 and the current flowing through the fuse element 105 at that time is changed. By measuring, the cutting state of the fuse element 105 is inspected.

  However, when actually measuring the open resistance of the fuse element blown in the PROM circuit, only a minute level leakage current of several pA or less flows, so it is difficult to directly measure the cut state. Further, when the current flowing in the fuse element is amplified by an amplifier and measured, it takes time to stabilize. For this reason, conventionally, it has been difficult to perform inspection of a high-speed and stable PROM circuit.

JP-A-56-169361

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a PROM circuit capable of performing a high-accuracy and high-speed inspection of a write state of a fuse element.

  The PROM circuit of the present invention includes a fuse element, an output circuit that outputs a high-level or low-level voltage according to a conduction state or a cut-off state of the fuse element, and a high-level or low-level output of the output circuit, respectively. A current source for voltage setting, a current source capable of changing an output current, a write terminal provided at the other end of the fuse element for inputting power for fusing the fuse element, and the write terminal A mode changeover switch that is fixed or opened at a certain voltage, and is configured to be able to control the output current of the current source and the changeover of the mode changeover switch according to an operation mode.

  With the above configuration, for example, when writing a fuse element in a PROM circuit, it is possible to blow a fuse element by inputting a predetermined power from a write terminal to make it into a cut state. When checking the state, it is possible to reliably check the writing state in a short time by controlling the output current of the current source and detecting the difference in the output voltage of the output circuit before and after the current fluctuation of the current source. It becomes possible. Further, when inspecting the write state of the fuse element, for example, by measuring the output voltage of the amplifying unit obtained by amplifying the output voltage from the output circuit, it is possible to inspect with high accuracy.

  According to another aspect of the present invention, in the PROM circuit described above, in the normal mode, the mode switch is turned on and the write terminal is fixed at a certain voltage. In the write mode, the mode switch Is turned off and the write terminal is opened, so that the fusing power can be supplied from the write terminal to the fuse element, and in the write test mode, the mode switch is turned on and the write terminal is at a certain voltage. In addition to being fixed, the output current of the current source is reduced.

  With the above configuration, in the normal mode, the mode switch is turned on and the write terminal is fixed to a certain voltage, and a high level voltage or a low level voltage is output from the output circuit according to the conduction state or the disconnection state of the fuse element, respectively. Is output. In the write mode, it is possible to blow the fuse element into a cut state by turning off the mode switch to open the write terminal and supplying power for fusing to the fuse element from the write terminal. In the write test mode, the mode switch is turned on to fix the write terminal at a certain voltage, and the output current of the current source is reduced to measure the output voltage in this write test mode, and the output voltage in the normal mode. By detecting the difference between the output voltage and the output voltage in the write check mode, it is possible to check with high accuracy in a short time whether or not writing is normally performed. Here, focusing on the fact that the output logic of the PROM circuit is inverted and malfunctions when the leakage current flowing through the fuse element in the normal mode exceeds a predetermined value, the current related to the output voltage setting of the PROM circuit in the write test mode. By reducing the source current arbitrarily, measuring the change in the output voltage of the PROM circuit, and confirming that the output logic of the PROM circuit does not invert, it is equivalent to directly measuring the leakage current of the fuse element It is possible to check whether or not the write state of the fuse element is normal, and a high-precision and high-speed write inspection can be performed.

  According to another aspect of the present invention, the PROM circuit includes a logic data input terminal that inputs logic data for control and a logic data latch circuit that holds the logic data. Also included are those in which inspection mode data input as logic data for setting to the writing inspection mode is input to the mode changeover switch and the current source to enable logic control.

  With the above configuration, by inputting logic data for control to the logic data input terminal, the write inspection mode can be set by logic control, and the write state inspection of the fuse element can be easily executed.

  The present invention is also a method for inspecting a PROM circuit including a fuse element, wherein a current flowing through the fuse element is varied, and a change in the current flowing through the fuse element is detected to determine a write result of the fuse element. Thus, a method for inspecting a PROM circuit for inspecting the impedance of a fuse element before and after writing is provided.

  According to the above procedure, it becomes possible to inspect the writing state of the fuse element with high accuracy and high speed.

  According to the present invention, it is possible to provide an effect of providing a PROM circuit capable of inspecting a writing state of a fuse element with high accuracy and high speed.

  In the present embodiment, a configuration example of a PROM circuit including a fuse element will be described. The PROM circuit of this embodiment is used for a memory circuit that stores a value of a temperature compensation function for generating a temperature compensation control voltage in the TCXO module, for example. The present embodiment is not limited to the TCXO module but can be applied to PROM circuits mounted on various circuits.

  FIG. 1 is a diagram showing a configuration of a main part of a PROM circuit according to an embodiment of the present invention. The PROM circuit of the present embodiment is constituted by an integrated circuit formed on a semiconductor substrate, and has a structure having a plurality of cells 10 corresponding to each bit of data to be output.

  Each cell 10 includes a power supply terminal 11, an output terminal 12, a first current source 13, a diode 14, a parasitic transistor 15, a fuse element 16, a P-channel MOS transistor 17, a second current source 18, a write voltage source 19, A write switch 20 is provided. Further, a write terminal 21 and a mode changeover switch 22 for writing to each cell 10, a logic data input terminal 25 and a logic data latch circuit 26 for logic control at the time of writing to each cell 10, and an output of each cell 10 are amplified. An operational amplifier circuit 23 and an operational amplifier output terminal 24 are provided.

  One end of the first current source 13 and the source of the MOS transistor 17 are connected to the power supply terminal 11, and the gate of the MOS transistor 17 and the anode side of the diode 14 are connected to the other end of the first current source 13. This power supply terminal 11 is connected in common with other cells 10. Further, one end of the fuse element 16 and one end of the write switch 20 are connected to the cathode side of the diode 14, and a write terminal 21 and a mode changeover switch 22 are connected to the other end of the fuse element 16. The other end of the mode switch 22 is grounded. The write switch 20 is turned on / off by input control logic data, and a write voltage source 19 is connected to the other end. The other end of the write voltage source 19 is grounded. The output terminal 12 and one end of the second current source 18 are connected to the drain of the MOS transistor 17, and the other end of the second current source 18 is connected to the other cell 10 in common. The MOS transistor 17 and the second current source 18 have a function of an output circuit.

  The output of the cell 10 per bit of the PROM circuit is connected to the input terminal of an operational amplifier circuit 23 which is an operational amplifier corresponding to an example of an amplifier together with the output terminal 12, and the output of the operational amplifier circuit 23 is connected to the operational amplifier output terminal. 24. Further, a logic data latch circuit 26 is connected to the control input terminal of the write switch 20, and an input of the logic data latch circuit 26 is a logic data input terminal 25. Further, the output of the inspection mode data holding unit (CM) of the logic data latch circuit 26 is connected to the mode changeover switch 22 and the control input terminal of the first current source 13. The logic data input terminal 25 receives logic data for logic control of the selection of a bit to be written and the operation of the cell of each bit. In the present embodiment, in the control logic data, the inspection mode data for controlling the mode changeover switch 22 and the first current source 13 is provided at the time of the writing state inspection, and this inspection mode data is also provided to the logic data latch circuit 26. A holding unit CM for the number of bits is provided.

  When the cell 10 corresponding to 1 bit is mounted on a TCXO module, for example, this PROM circuit gives coefficients and constants of respective orders in a temperature compensation function having a characteristic opposite to the temperature characteristic of a crystal oscillator. As many bits as necessary to generate a control voltage for temperature compensation are provided in parallel.

  The fuse element 16 is formed on a substrate by polysilicon or the like, and is blown by a predetermined applied voltage to short-circuit and open an electrical circuit connection. The diode 14 is configured using an NPN-type high breakdown voltage transistor, and allows the current from the first current source 13 to flow to the fuse element 16 when the fuse element 16 is in a short-circuited state (non-blown state). Instead of the diode 14 formed of the NPN-type high breakdown voltage transistor shown in FIG. 1, a diode constituted by a PN junction diode 31 may be used as in the modification shown in FIG.

  The write switch 20 is composed of a bipolar transistor, a MOS transistor or the like, and the control logic data of the corresponding bit is input to the control input terminal from the respective bit holding portions D1 to Dn of the logic data latch circuit 26 and is controlled to be turned on / off. The The write switch 20 is turned on when a high level is input to the control input terminal. When the mode switch 22 is turned off and a voltage is applied from the write terminal 21, when the write switch 20 is turned on, a current required for writing is drawn by the write voltage source 19 and the fuse element 16 is blown.

  The mode changeover switch 22 switches between a normal mode, a write mode, and a write inspection mode. At the time of a write inspection, the inspection mode data from the inspection mode data holding unit CM of the logic data latch circuit 26 is input to the control input terminal and turned on / off. Be controlled. The mode switch 22 is turned on when a high level is input to the control input terminal.

  The first current source 13 receives the test mode data from the test mode data holding unit CM of the logic data latch circuit 26 at the control input terminal, and the output current value is controlled. For example, the first current source 13 is configured so that the output current value becomes a quarter when a high level is input to the control input terminal.

  FIG. 3 is a circuit diagram showing a configuration example of the first current source 13. The first current source 13 includes a current mirror including a pair of transistors 41 and 42, resistors 43 and 44 connected in series, and a switch 45. One end of the resistor 43 is connected to the collector of one transistor 41 of the current mirror, and the other end of the resistor 44 is grounded. The switch 45 is provided between the connection portion of the resistor 43 and the resistor 44 and the ground, and switches the connection of the resistor 44.

  In the normal mode, when the inspection mode data is not input to the control terminal of the switch 45, the switch 45 is turned on and the resistor 44 is short-circuited. On the other hand, in the write inspection mode, when inspection mode data is input to the control terminal of the switch 45, the switch 45 is turned off and the resistor 44 is inserted. In the write check mode, the resistance 44 increases the ground resistance on the collector side of the transistor 41, and the current I flowing to the point A decreases. In the first current source 13, the current value that is changed by switching the switch 45 can be arbitrarily set by the resistance values of the resistors 43 and 44.

  The operational amplifier circuit 23 amplifies the output of each cell 10 output from the output terminal 12 with a predetermined gain and outputs it from the operational amplifier output terminal 24. The output of each cell 10 from the output terminal 12 can be decoded by a decoding circuit (not shown) to generate a control data signal composed of a plurality of bits.

Next, the operation of each mode of the PROM circuit configured as described above will be described.
First, the operation in the normal mode will be described. In the normal mode, a voltage is applied only to the power supply terminal 11. In this case, the power supply voltage Vcc is applied to the power supply terminal 11. At this time, the mode changeover switch 22 is controlled to be turned on by an inspection mode data signal from the logic data latch circuit 26 or another control signal. As a result, the write terminal 21 is short-circuited and grounded.

  When the fuse element 16 is in a conductive state (short circuit state) before fusing, when a power supply voltage is applied to the power supply terminal 11, the diode 14 becomes conductive, and the current of the first current source 13 flows to the fuse element 16 through the diode 14. At this time, the voltage at the point A becomes a voltage obtained by adding the voltage drop at the fuse element 16 and the voltage drop at the diode 14 to about 0.7 V, and the gate-source voltage of the MOS transistor 17 is the power supply voltage Vcc-. Since the voltage at point A is 0.7 V or higher, the MOS transistor 17 is turned on, and a high level voltage is output to the output terminal 12.

  When the fuse element 16 is in a cut state (open state), the fuse element 16 is in a high impedance state of several tens of GΩ, and only a minute level leak current of several pA or less flows. Thereby, since the current of the first current source 13 hardly flows, the voltage at the point A becomes the same level as the power supply voltage Vcc. Therefore, the MOS transistor 17 is turned off, and a low level voltage is output to the output terminal 12.

  Next, the operation in the write mode will be described. In the write mode in which the fuse element is written, the mode changeover switch 22 is controlled to be switched by the inspection mode data signal from the logic data latch circuit 26 or another control signal, and the control from the logic data latch circuit 26 is performed. The write switch 20 is switched and controlled by logic data. At this time, a voltage is applied to the write terminal 21 with the mode changeover switch 22 turned off and the write switch 20 for the corresponding bit turned on under logic control.

  For example, in the case of one embodiment of a polysilicon fuse, the fuse element has a resistance of 200 to 300Ω, and a temperature of 1300 ° C. or higher is required to blow the fuse element. Therefore, if a cutting current having a peak current value of about 150 mA flows through the fuse element 16, the fuse element 16 can be blown at a temperature generated by the cutting current. In a state where a predetermined voltage is applied to the write terminal 21 and the write switch 20 is turned on, a cutting current having a peak current value of about 150 mA is obtained, and the fuse element 16 is configured to be blown by this cutting current.

  The operation in the write check mode will be described. First, the output voltage of the operational amplifier output terminal 24 is measured in the normal mode in which only the power supply voltage Vcc is applied to the power supply terminal 11. Next, the writing inspection mode of this embodiment is set. In the write check mode in which the write state of the fuse element 16 is checked, control logic data of all “0” is transferred to each bit holding unit D1 to D1 of the logic data latch circuit 26 so as to turn off the write switches 20 of all bits. Dn is input to the write switch 20 and the test mode data “1” for the write test is input from the logic data input terminal 25 to the test mode data holding unit CM of the logic data latch circuit 26.

  According to the setting of the inspection mode data, a control signal is input from the inspection mode data holding unit CM of the logic data latch circuit 26 to the mode changeover switch 22 and the first current source 13 to perform logic control. In this case, the mode switch 22 is turned on, the write terminal 21 is connected to the ground, and the output current of the first current source 13 is controlled to decrease.

  Subsequently, in this write test mode, the output voltage of the operational amplifier output terminal 24 is measured. Here, by comparing the output voltage measured in the write inspection mode with the output voltage measured in the normal mode, it can be determined whether or not the fuse element 16 has blown. That is, the output voltage of the operational amplifier output terminal 24 is measured before and after setting the write test mode, and if no voltage difference occurs, the logic is inverted (change from high level to low level) at the output of the cell 10 by the fuse element 16. Therefore, it is determined that the fuse element 16 is normally written and disconnected. On the other hand, when a voltage difference occurs, logic inversion occurs at the output of the cell 10, and it is determined that writing of the fuse element 16 is not performed normally and the cut state is incomplete.

  Here, the relationship between the change in the output voltage of the operational amplifier output terminal 24 and the write state of the fuse element 16 will be described. In the present embodiment, in the normal mode, for example, when a leak current of 10 nA or more flows through the fuse element 16, the output logic of the output terminal 12 is inverted, and the circuit design is such that a malfunction occurs. Further, in the write check mode, the output current of the first current source 13 is reduced to a quarter.

  In the state where the fuse element 16 is normally written and there is no malfunction, the logic of the output terminal 12 is not inverted, so the leakage current flowing through the fuse element 16 in the open state in the normal mode is considered to be less than 10 nA. At this time, if the voltage at point A is set to 1.4V, the voltage drop of the diode 14 is 0.7V, so the voltage applied to the fuse element 16 is 1.4V−0.7V = 0.7V, and the fuse element The open resistance of 16 is 0.7 V / 10 nA = 70 MΩ or more.

  When the output current of the first current source 13 is reduced to a quarter in the write inspection mode, the current flowing through the fuse element 16 becomes a quarter, less than 2.5 nA, and the open resistance of the fuse element 16 is 280 MΩ. That's it. Therefore, when the output voltage of the cell 10 is measured before and after the setting of the write inspection mode and no voltage difference occurs, the output logic is not inverted, and the fuse element 16 is normally written. It is judged. Therefore, the write inspection method using the configuration of the present embodiment is the same as the conventional case where a leakage current of less than 2.5 nA is measured from the write terminal to inspect whether there is a problem in writing. . Further, by amplifying the output of the output terminal 12 by the operational amplifier circuit 23 and detecting the voltage change by the output voltage of the operational amplifier output terminal 24, even a minute voltage difference can be detected.

  As described above, in this embodiment, instead of checking the write state by measuring the leakage current of the fuse element, a write check mode is provided to provide a current related to output logic setting (in the above example, the current of the first current source 13). Can be arbitrarily reduced, and it can be confirmed that there is no logic inversion in the output of the PROM circuit, so that the writing state can be inspected at high speed and stably. Further, the output of the PROM circuit is amplified by an amplifying unit such as an operational amplifier circuit, and by detecting whether or not there is a potential difference before and after setting of the write test mode, a high-precision write test can be performed.

  When the PROM circuit of this embodiment is used in a memory circuit that stores a value of a temperature compensation function for generating a temperature compensation control voltage in the TCXO module, when writing a compensation value adjusted for each module, Writing inspection at the time of shipment or the like can be performed with high accuracy and in a short time.

  INDUSTRIAL APPLICABILITY The present invention has an effect that inspection of a write state of a fuse element in a PROM circuit can be performed with high accuracy and high speed, and is useful for inspection at the time of shipping of a PROM circuit including a fuse element.

The figure which shows the structure of the principal part of the PROM circuit which concerns on embodiment of this invention. The figure which shows the modification of the PROM circuit of this embodiment shown in FIG. The circuit diagram which shows the structural example of the 1st current source in the PROM circuit of this embodiment The figure which shows the structural example of the conventional PROM circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Cell 11 Power supply terminal 12 Output terminal 13 1st current source 14 Diode 15 Parasitic transistor 16 Fuse element 17 MOS transistor 18 2nd current source 19 Write voltage source 20 Write switch 21 Write terminal 22 Mode switch 23 Operational amplifier circuit 24 Operational amplifier Output terminal 25 Logic data input terminal 26 Logic data latch circuit

Claims (4)

A fuse element;
An output circuit that outputs a high-level or low-level voltage, respectively, according to the conduction state and the cutting state of the fuse element;
A current source for supplying a high-level or low-level output voltage setting of the output circuit, and a current source capable of changing the output current;
A write terminal which is provided at the other end of the fuse element and inputs power for fusing the fuse element;
A mode switch for fixing or releasing the write terminal at a certain voltage,
A PROM circuit configured to be able to control output current of the current source and switching of the mode switch according to an operation mode. The PROM circuit according to claim 1,
In the normal mode, the mode switch is turned on and the write terminal is fixed at a certain voltage, and in the write mode, the mode switch is turned off and the write terminal is opened, and the fuse is connected to the fuse from the write terminal. The device is in a state in which power for fusing can be supplied to the device, and in the write inspection mode, the mode switch is turned on and the write terminal is fixed at a certain voltage, and the output current of the current source is reduced. PROM circuit. A PROM circuit according to claim 1 or 2,
A test mode having a logic data input terminal for inputting control logic data and a logic data latch circuit for holding the logic data, and being input as logic data for setting the write test mode in the write test mode A PROM circuit in which data can be controlled by inputting data to the mode switch and the current source. A method for inspecting a PROM circuit including a fuse element,
A PROM circuit inspection method for inspecting the impedance of a fuse element before and after writing by varying a current flowing through the fuse element and detecting a change in the current flowing through the fuse element to determine a write result of the fuse element.

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