JPH11184734A - Mutual monitor device for cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly detect failure by another CPU when failure is generated in one CPU. SOLUTION: A monitoring circuit 20-1 is provided corresponding to a CPU 10, and the state of the CPU 10 is monitored. A detecting circuit 22-1 is provided corresponding to a CPU 12, and when the state change of the CPU 10 is present, it is communicated to the CPU 12 based on the monitored result of the monitoring circuit 20-1. In the same way, a monitoring circuit 20-2 for monitoring the state of the CPU 12 is provided corresponding to the CPU 12, and a detecting circuit 22-2 for communicating the state change of the CPU 12 to the CPU 10 based on the monitored result of the monitoring circuit 20-2 is provided corresponding to the CPU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mutual monitoring device for CPUs, and more particularly, to a device having a plurality of CPUs for mutually transmitting and receiving data via a memory, and a secondary device for performing quick detection when a failure occurs. The present invention relates to a mutual monitoring device for a CPU applied to a communication device that requires prevention of a temporary failure.

[0002]

2. Description of the Prior Art FIG. 4 is a block diagram showing a configuration of a conventional CPU mutual monitoring device. In FIG. 4, 10, 1
2 is a CPU (Central Processing Unit), and 14 is a memory. The CPU 10 is connected to the memory 14 by a CPU bus B1, and the CPU 12 is connected to the memory 14 by a CPU bus B2. Here, the CPU bus includes both an address bus for specifying a write address of a memory and a data bus for transmitting and receiving data.

When the CPU 10 writes data to the memory 14, an interrupt signal line I1 for transmitting an interrupt signal indicating that the CPU 10 has written data to the memory 14 is connected to the CPU 10 and the memory 14. Similarly, an interrupt signal line I2 for transmitting an interrupt signal indicating that the CPU 12 has written data to the memory 14 is provided between the CPU 12 and the memory 14.

In the above configuration, when the CPU 10 transmits data to the memory 14 via the CPU bus B1 and writes data to the memory 14, the memory 14 receives and writes the data, Signal line I
An interrupt signal is generated to the connection-destination CPU 12 via the CPU 2 to notify that data has been received from the CPU 10. Upon receiving this interrupt signal, the CPU 12
2 for receiving data.

[0005]

SUMMARY OF THE INVENTION The CPU 12 has a CPU
10 that the data sent from 10 has been received normally.
In an apparatus that is not designed to respond to the CPU 10, the CPU 10 generates an
In a state where the data transmitted by U10 cannot be normally received, C
The presence of the PU 12 cannot be determined.

In a device designed to return a reception response to the CPU 10 when the CPU 12 receives data, a timer is provided for the CPU 10 and the CPU 10
After transmitting data to the memory 14, this timer is started, and if there is no response from the CPU 12 within a predetermined time, C
It is determined that some abnormality has occurred in the PU 12. However, in the case of this device, it is not possible to determine what state the CPU 12 is in, and the recovery process after the occurrence of the failure is independently performed by the CPU 10. However, CP
Since the cause of the abnormality of U12 cannot be determined, appropriate measures cannot be taken.

[0007] As a procedure for recovering from the occurrence of a failure in the CPU 12, the administrator of the apparatus removes the failure in the CPU 12, resets both the CPU 10 and the CPU 12, and returns the states of the CPUs 10 and 12 to the initial state. Do with. As another recovery method, an administrator of the apparatus removes a fault in the CPU 12, generates an interrupt signal from the CPU 12 to the CPU 10, and notifies the CPU 10 that the fault has been removed.

In such a conventional apparatus, as described above, in order to determine whether or not a failure has occurred in the CPU 12, it is necessary to provide a timer in the CPU 10, transmit data, and measure the time. is there. CPU
The time required for the CPU 10 to determine that a failure has occurred in the CPU 12 is the time required for the timer to measure a preset time after the CPU 10 transmits data to the CPU 12. The time preset in the timer is
The time is usually set to several tens of seconds with a margin in consideration of the time until the CPU 10 completes another process.

For this reason, it is difficult for the CPU 10 to detect the failure immediately after the failure has occurred in the CPU 12. Further, the time from the occurrence of a failure to the detection cannot be predicted. Periodically between the CPUs 10 and 12, the CPU
Although an apparatus configuration for transmitting and receiving signals indicating the states of the statuses 10 and 12 and checking the normality can be considered, a part of the processing capability of the CPUs 10 and 12 is required for this processing, and the processing capability of the device is reduced. There is a problem that there is a limit to frequent performances because of inviting. Further, in such a device,
There is a problem that there is a risk of inducing a secondary failure before the occurrence of the failure is detected.

In a communication device having a plurality of CPUs as shown in FIG. 4, it is necessary to detect a fault within one second after the fault has occurred, and to perform secondary detection caused by the fault. It is necessary to suppress the occurrence of a major obstacle as much as possible,
There is a problem that it cannot be realized by the conventional method.

The present invention has been made in view of the above circumstances, and when one CPU fails, the other C
A main object of the present invention is to provide a mutual monitoring device for CPUs in which a PU can quickly detect a failure. In addition, the present invention provides a method in which when one CPU fails, another C
It is an object of the present invention to provide a CPU mutual monitoring device capable of accurately detecting the state of a failed CPU in a PU.

[0012]

In order to solve the above problems, the present invention is provided for each of two or more CPUs,
Monitoring means for monitoring the state of the CPU; and C provided for each of the CPUs, except for the corresponding CPU.
Detecting means for detecting a state change of the CPU based on a monitoring result of the monitoring means provided for the PU, and notifying that the corresponding CPU has changed state. Features. Further, according to the present invention, the detecting means compares a register storing the monitoring result output from the monitoring means, a storage content of the register, and a monitoring result output from the monitoring means, And a comparator for notifying the CPU corresponding to the case where the state is different that the state has changed. Further, the present invention is characterized in that the CPU reads out the stored contents of the register and the monitoring result output from the monitoring means when the corresponding detection means notifies that the state has changed, and Is determined. Further, according to the present invention, the monitoring circuit has a watchdog timer for monitoring a state of the CPU, a reset circuit for resetting the CPU, and a register for storing an operation state of the CPU, Comprises the output of the watchdog timer and the NAND output of the outputs of the reset circuit and the register. Also, in the present invention, the CPU is mounted on a different unit, and the output of the watchdog timer and the NAND output are pulled up by a resistor.
It is characterized in that it is determined whether or not the unit mounted with is connected.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a mutual monitoring device for CPUs according to an embodiment of the present invention. In FIG. 1, reference numerals 10 and 12 denote CPUs (central processing units), and reference numeral 14 denotes a memory. CPU 10 is a CP
The CPU 14 is connected to the memory 14 by the U bus B10.
2 is connected to the memory 14 by the CPU bus B12. Here, the CPU bus includes both an address bus for specifying a write address of a memory and a data bus for transmitting and receiving data.

When the CPU 10 writes data to the memory 14, an interrupt signal line I1 for sending an interrupt signal indicating that the CPU 10 has written to the memory 14 is connected to the CPU 10 and the memory 14. Similarly, an interrupt signal line I2 for transmitting an interrupt signal indicating that the CPU 12 has written data to the memory 14 is provided between the CPU 12 and the memory 14.

In the figure, reference numeral 20-1 denotes a monitoring circuit for monitoring the state of the CPU 10, which is connected to the CPU 10 via a CPU bus B10.
10 is connected. Reference numeral 22-1 denotes a detection circuit for detecting a failure. The detection circuit 22-1 is connected to the CPU 12 via the CPU bus B12, and further connected to the CPU 12 via an interrupt signal line 32-1. The detection circuit 22-1 is connected to the signal lines 24-1,
26-1 is connected to the monitoring circuit 20-1.
The signal lines 24-1 and 26-1 are 1-bit signal lines, respectively, and the resistors 28-1 and 30-1 are connected to the respective signal lines. 1 is connected to a power supply.

In the drawing, reference numeral 20-2 denotes a monitoring circuit for monitoring the state of the CPU 12, which is connected to the CPU 12 via the CPU bus B12.
12 is connected. Reference numeral 22-2 denotes a detection circuit for detecting a failure. The detection circuit 22-2 is connected to the CPU 10 via the CPU bus B10, and further connected to the CPU 10 via an interrupt signal line 32-2. The detection circuit 22-2 includes a signal line 24-2,
It is connected to the monitoring circuit 20-2 via 26-2.
The signal lines 24-2 and 26-2 are 1-bit signal lines, respectively, and the resistors 28-2 and 30-2 are connected to the respective signal lines. 2 is connected to a power supply.

Next, the monitoring circuit 20-1 and the detection circuit 22
-1 will be described in detail. FIG. 2 shows the monitoring circuit 20-
FIG. 2 is a block diagram illustrating an internal configuration of a first detection circuit and a detection circuit. As shown in FIG. 2, the monitoring circuit 20-1 includes a watchdog timer 50, a reset circuit 52, a register 54, and a NAND circuit 56. In the following description, the high level of the logic level is represented as “1”,
The low level is represented as “0”.

The watch dog timer 50 is a CPU
If a failure has not occurred in the CPU 10, an output signal of "0" is output, and if a failure has occurred in the CPU 10, an output signal of "1" is output. The watch dog timer 50 is connected to the signal line 24. The reset circuit 52 outputs an output signal of “0” for a predetermined time after the power is turned on, and outputs an output signal of “1” when the predetermined time has elapsed.

The register 54 is for writing the operation status of the CPU 10. For example, when the CPU 10 is in a reset state and the reset state is released, the CP 10
U10 writes "1" into the register 54. The reset circuit 52 and the register 54 include a NAND circuit 56
, And the output terminal of the NAND circuit 56 is connected to the signal line 26-1.

Next, the internal configuration of the detection circuit 22-1 will be described. The detection circuit 22-1 includes a register 60 and a comparator 62, as shown in FIG. The register 60 and the comparator 62 are connected by a read signal line 70 to C
It is connected to PU12. Note that the read signal line 70 is not shown in FIG.

The register 60 includes signal lines 24-1 and 24-26.
1 and temporarily holds the logic state of the signal lines 24-1 and 26-1. The comparator 62 has two pairs of input terminals, and outputs an interrupt signal for notifying the CPU 12 via the interrupt signal line 32-1 when the signals input to each of the pair of input terminals are different. Output.

Signal lines 24-1 and 26-1 are connected to one pair of input terminals (hereinafter, referred to as A input terminals), and to the other pair of input terminals (hereinafter, referred to as B input terminals). Is connected to the output terminal of the register 60. This comparator 62 is C
It is connected to the CPU 12 via the PU bus B12. That is, the detection circuit 22-1 is connected to the signal line 24-1 or 26-1.
When the logical level of a signal transmitted through the CPU changes, the CPU 12 is notified of the change, and the CPU 12 issues a read signal, so that the logical level of the signal before and after the change can be grasped. . The internal configuration of the monitoring circuit 20-1 and the detection circuit 22-2 has been described above. However, the monitoring circuit 20-2 has the same configuration as the monitoring circuit 20-1, and the detection circuit 22-1 has the detection circuit 22-2. This is the same configuration as.

In FIGS. 1 and 2, a line denoted by a symbol S indicates a dividing point when the CPU 10 and the CPU 12 are provided on different units, for example, when the CPU 10 and the CPU 12 are provided on different substrates. Is shown. When the CPU 10 and the CPU 12 are separately mounted on different boards as described above, one monitoring circuit and one detection circuit are provided on the same board. For example, a monitoring circuit 20-1 and a detection circuit 22-2 are provided for the CPU 10, and the CPU 10
For 12, a monitoring circuit 20-2 and a detection circuit 22-1 are provided.

Next, the operation of the mutual monitoring device of the CPU having the above configuration will be described in detail with reference to FIGS. FIG. 3 is a chart for explaining a failure situation when the logic levels of the signal lines 24-1 and 26-1 change. In the following description, a case where a failure or the like occurs in the CPU 10 and the CPU 12 detects the failure will be described.

In FIG. 3, the rows and columns denoted by the symbol a mean that the logic levels of the signal lines 24-1 and 26-1 are both "1". Further, the row and column denoted by the symbol “b” mean that the logical level of the signal line 24-1 is “0” and the logical level of the signal line 26-1 is “1”. In the rows and columns to which the symbol c is attached, the logic level of the signal line 24-1 is "1", and the signal line 26-1
Is "0". The rows and columns denoted by the symbol d are the signal lines 24-1 and 26-1.
Are both "0". Hereinafter, the signal lines 24-1 and 26 indicated by the reference numerals a to d will be described.
The states of the logic level 1 are referred to as states a to d, respectively.

First, when the power is turned on, the initial value of the detection circuit 22-1 after the power is turned on is "0".
The PU 12 captures the values of the signal lines 24-1 and 26-1 by outputting a read signal via the read signal line 70.

If the monitoring circuit 20-1 is mounted on another unit and is not connected to the detection circuit 22-1, the logic levels of the signals input to the detection circuit 22-1 are all It becomes “1”. This is because the signal line 24-
1 and 26-1 are connected to the power supply via the resistors 28-1 and 30-1, that is, pulled up.

Also, when the monitoring circuit 20-1 is mounted on another unit and is connected to the detection circuit 22-1, or when the monitoring circuit 20-1 and the detection circuit 22-1 are in the same unit. When the power supply is mounted inside the power supply, the reset circuit 52 in the monitoring circuit 20-1 operates immediately after the power is turned on, and its output becomes "0", so that the logical level of the signal line 26-1 becomes "1". . While the reset circuit 52 is operating,
Since the output of the watchdog timer 50 is fixed at "0", the logical level of the signal line 24-1 becomes "0".

Signal lines 24-1 and 26-1 immediately after power-on
Is stored in the register 60 and the comparator 62
Is output to the B input terminal. When the logical level of the signal line 24-1 or the signal line 26-1 changes, the logical level of the signal input to the A input terminal and the logical level of the signal input to the B input terminal change. An interrupt signal is output to the CPU 12 via the interrupt signal line 32-1.

An interrupt signal is sent from the comparator 62 to the CPU 12
The CPU 12 outputs a read signal via the read signal line 70 to read the signals input to the A input terminal and the B input terminal of the comparator 62. In the above case, before the logical level changes, the signal lines 24-1 and 26-2
The logical levels of -1 are both "0", and after the change, the logical level of the signal line 24-1 is "0" and the logical level of the signal line 26-1 is "1". That is, the state has changed from the state d to the state b. In this case, based on the chart shown in FIG. 3, the CPU 12 determines that the connected CPU 10 is being reset, that is, being initialized.

Next, when the reset in the reset circuit 52 is released, first, the output of the reset circuit 52 becomes "1". Next, the CPU 10 starts operating, and the register 5
4 is written with "1". Writing “1” to the register 54 is performed when the initial setting in the normal unit is completed. In this case, the logic level of the signal line 24-1 is "0".
And the logic level of the signal line 26-1 is "0",
That is, the state changes to the state d.

At this time, in the detection circuit 22-1, the state held by the register 60 is the state b, and the signal of the state b is input to the B input terminal of the comparator 62. When the reset is released, the signal of the state d is input to the A input terminal of the comparator 62, so that the comparator 62 outputs an interrupt signal to the CPU 12 via the interrupt signal line 32-1.

When this interrupt signal is received, the CPU 1
Reference numeral 2 outputs a read signal via a read signal line, and reads a signal input to the A input terminal and the B input terminal of the comparator 62. In the read signal, the signal before the change is in the state b and the signal after the change is in the d state. Therefore, the CPU 12 determines that the connected CPU 10 has completed initialization and is operating normally.

While the CPU 10 is operating normally, the logic levels of the signal lines 24-1 and 26-1 are both "0", and the state d is maintained. When a failure occurs in the CPU 10, the watchdog timer 50 operates, and its output is set to "1", so that the logical level of the signal line 24-1 becomes "1". Therefore, the state changes to state c.

Since the register 60 stores the state c and the signal of the state d is input to the B input terminal of the comparator 62, the signal of the state c is input to the A input terminal of the comparator 62. , The comparator 62 outputs an interrupt signal to the CPU 12 via the interrupt signal line 32-1. When the CPU 12 reads the signals input to the A input terminal and the B input terminal of the comparator 62, the signal before the change is in the d state and the signal after the change is in the c state.
0 is determined to have failed.

As described above, the CPU 10 is provided with the monitoring circuit 20-1 for monitoring whether or not a failure has occurred, and the detection circuit 22-1 for detecting the monitoring result output from the monitoring circuit 20-1. Since it is provided on the CPU 12 side, the CP
The U12 can immediately detect the occurrence of a failure in the CPU 10 when there is a change in the state of the connected CPU 10. Also, C
The PU 12 can accurately determine the state of the connected CPU 10 by reading the monitoring result output from the monitoring circuit 20-1, and can appropriately select a process in each state.

In the above embodiment, the CPU 1
2 has been described, the monitoring circuit 20-2 is provided for the CPU 12 and the detection circuit 2 is provided for the CPU 10 as shown in FIG.
2-2 is provided, so that the CPU 10
When the state of the PU 12 changes, the CPU 12
Can be detected. Further, the CPU 10 can accurately determine the state of the connected CPU 12 by reading the monitoring result output from the monitoring circuit 20-2, and can appropriately select a process in each state.

In the above embodiment, the CPU 1
Although a case has been described where 0 and the CPU 12 monitor each other on a one-to-one basis, the present invention is not limited to this and can be freely changed within the scope of the present invention. For example, CPU 10,
By providing a plurality of CPUs other than 12 and arranging the memory 14 between these CPUs and further providing a detection circuit and a monitoring circuit for each CPU, it is also possible to perform one-to-many monitoring.

[0039]

As described above, according to the CPU mutual monitoring apparatus of the present invention, monitoring means provided for each of two or more CPUs for monitoring the state of the CPU, The CPU provided and supported
Detecting means for detecting a change in the state of the CPU based on the monitoring result of the monitoring means provided for the other CPUs, and notifying that the corresponding CPU has changed state. Therefore, when the state of the connected CPU changes, it is possible to detect the failure of the CPU immediately after the occurrence of the failure. Specifically, it can be detected within several steps of the number of programs executed by the CPU. Further, the CPU reads the state before and after the state change and compares the values before and after the state change when notified of the state change from the corresponding detecting means, so that the state of the connected CPU is accurately determined. There is an effect that the judgment can be made.
Therefore, there is an effect that the subsequent processing can be executed accurately and the occurrence of a secondary failure can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a mutual monitoring device for CPUs according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a monitoring circuit 20-1 and a detection circuit 22-1.

FIG. 3 is a chart for explaining a failure situation when the logic levels of the signal lines 24-1 and 26-1 change.

FIG. 4 is a block diagram showing a configuration of a conventional mutual monitoring device for CPUs.

[Explanation of symbols]

 10, 12 CPU 20-1, 20-2 Monitoring circuit (monitoring means) 22-1, 22-2 Detection circuit (detection means) 28-1, 28-2, 30-1, 30-2 Resistor 50 Watchdog Timer 52 Reset circuit 54 Register 56 NAND circuit 60 Register 62 Comparator

Claims (5)

[Claims] A plurality of CPUs provided for each of the plurality of CPUs;
Monitoring means for monitoring the state of the CPU; and C
Detecting a state change of the CPU based on a monitoring result of the monitoring unit provided for the CPU other than the PU,
A mutual monitoring device for CPUs, comprising: detection means for notifying that the corresponding CPU has changed state. 2. The detection means, comprising: a register for storing a monitoring result output from the monitoring means; a storage content of the register; and a monitoring result output from the monitoring means. 2. The C according to claim 1, further comprising a comparator for notifying the CPU corresponding to a different case that the state has changed.
PU mutual monitoring device. 3. The CPU reads the storage contents of the register and the monitoring result output from the monitoring means when notified of a state change from the corresponding detecting means, and reads the monitoring result of the CPU. 3. The mutual monitoring device for CPU according to claim 2, wherein the status is determined. 4. The monitoring circuit includes: a watchdog timer for monitoring a state of the CPU; a reset circuit for resetting the CPU; and a register for storing an operation state of the CPU. The output of the watchdog timer,
2. The mutual monitoring device for a CPU according to claim 1, comprising a NAND output of the reset circuit and a register output. 5. The CPU is mounted on a different unit, the output of the watchdog timer and the NAND output are pulled up by a resistor, and the CPU is mounted on the CPU based on the monitoring result. 5. The CPU mutual monitoring device according to claim 4, wherein it is determined whether said unit is connected.