JPH11184646A - Printer interface device and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printer interface device and a control method in which configuration changes are reduced both on printer unit side and on controller side and any dedicated software is not required as well. SOLUTION: In a controller 30, print data stored in a dynamic random access memory(DRAM) 301 are transferred to a copy machine 20 just for one line by a direct memory access controller (DMAC) 303 by performing burst transfer plural times while defining the burst transfer for the arbitrary number of bytes (for the unit of 8 words at a maximum) as one unit. In order to guarantee the transfer completion of all the print data for one line within the transfer time for one line specified at the copy machine 20, a DRAM controller 302 variably sets the priority of access so as to increase the DRAM access frequency of the DMAC 303 while the DMAC 303 transfers print data from the DRAM 301 to the copy machine 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printer interface device for performing control for transferring print data (print data) from an information processing device to a printer device, and more particularly, to using a copying machine or the like as the printer device. In this case, the present invention relates to an improvement in a configuration and a control method for enabling a versatile operation with few new design requirements.

[0002]

2. Description of the Related Art When a document file or the like created by an information processing system is printed out, an operation method using a copying machine that outputs multivalued data as a printer device is known. In such an application, a controller is usually installed outside the copying machine, and the controller is used to control an interface with the copying machine.

Here, the controller is a RIP (Raster
Image Processor (image data generation) process, and transfers the rasterized data provided from the information processing device to the copying machine via the external interface. In this case, the interface between the controller and the copying machine has its own specification, and the signals and timings are specified by the ROS (Rast
er Output Scanner).

FIG. 6 shows an example of a printer interface device in such a conventional system.
In this printer interface device, the controller 30 has a dynamic random access memory (DRAM).
y) 311, DRAM controller 312, DMAC (D
irect Memory Access Controller) 313, FIFO
(First-In First-Out) memory 314 and an output timing controller 315. The copying machine 20 has an input timing controller 211 and a synchronous FIFO.
An O memory 212 is provided.

In this printer interface device, interface specifications between the controller 30 and the copying machine 20 are defined as shown in the following 1 to 6.

(1) The following signals are used for controlling the interface between the controller 30 and the copying machine 20.

PERQ: Start signal of one page (transfer starts when controller 30 inputs PERQ and LREQ) LREQ: Start signal of one line [controller 30 bursts print data (DATA) for one line in accordance with this signal Transfer] VALID: Indicates that the controller 30 is performing burst transfer of DATA to the copying machine 20.

VCLK: The controller 30 performs a burst transfer of DATA to the copying machine 20 in synchronization with this signal.

DATA: Print data from the controller 30 to the copying machine 20 (2) LREQ is always input from the copying machine 20 to the controller 30.

(3) PREQ is transferred to the controller 30 when the copying machine 20 prints out.

(4) When LREQ is asserted after PREQ is asserted, the controller 30 immediately asserts VALID and transfers one line of DATA to the copying machine 20 in bursts.

(5) While VALID is asserted, the controller 30 performs burst transfer of one line of DATA in synchronization with VCLK.

(6) When PREQ is negated, the controller 30 ends the transfer of DATA.

FIG. 7 shows print data to be transferred in data transfer based on the above interface specifications.
FIG. 4 is a diagram illustrating a relationship between each signal of LREQ, VALID, and PREQ.
In the figure, [H _- WIDTH] indicates the number of pixels of one line of the print data, and [V _- HEIGHT] indicates the number of lines of the print data.

FIG. 8 is a flowchart showing the processing operation of the control software of the controller 30 based on the above interface specifications. Hereinafter, referring to this flowchart, the transfer of print data from the controller 30 to the copying machine 20 will be described. The transfer procedure will be described.

In FIG. 6, a controller 30 sends print data to be sent to the copying machine 20 to a DRAM 311.
(Step 801). After the storage of the print data is completed, the start address of the print data is set in the DMAC 313 (step 802), and the number of transfer bytes is set (step 803). Print data 1
[H _- WIDTH] indicating the number of pixels of the line and [V _- HEIGHT] indicating the number of lines for one page are set (see FIG. 7).
(Step 804).

Next, the controller 30 includes a DMAC 31
3 is started (step 805). DMAC 313 is
The print data stored in the DRAM 311 is sequentially
It is stored in the FO memory 314.

Next, the controller 30 activates an output timing controller 315 for controlling the output timing of the print data. PREQ and LREQ from copier 20
Is input to the controller 30, the operation of the output timing controller 315 is started (step 806). The output timing controller 315 outputs F
The print data stored in the IFO memory 314 is transferred to the copying machine 20 at the timing indicated in the interface specification.

After that, the DMAC 313 finishes transferring the print data to the FIFO memory 314 to monitor whether there is an end interrupt from the DMAC 313 (step 807). If there is an end interrupt (step 807 YES), the print data area of the DRAM 311 is checked. Is released (step 808), and the output data controller 315 monitors the print data transfer operation.

During this time, the output timing controller 31
When the PREQ is negated, a termination interrupt is generated (YES in step 809), and the process proceeds to preparation for terminating the process.

At this time, the controller 30 controls the DMAC 3
13, the print data amount output to the FIFO memory 314, and the output timing controller 315 sets [H _- WIDTH].
Is set as [V _- HEIGHT], and the amount of print data transferred to the copying machine 20 is compared to determine whether or not the processing is completed normally (step 810). If the two data do not match (step 810 NO), the process ends as an error has occurred (step 811).

[0022]

As described above, in a conventional printer interface device in which a copier that outputs multi-value data is used as a printer, a unique interface specification is provided between an externally installed controller and the copier. The signal and timing are specified based on the ROS control of the copying machine. As a result, for the copying machine, as long as the interface specifications are satisfied, the hardware is simplified and the processing load is reduced.

On the other hand, on the controller side, in order to satisfy the data transfer in accordance with the above interface specification,
Dedicated output timing controller (315) and FIF
It was necessary to provide an O memory (314) and the like, and the hardware configuration was inevitably complicated, and software for controlling the hardware was also required.

As described above, in this type of conventional device, the interface specifications between the controller and the printer device place a heavy burden on the controller side. In development, both the hardware and software of the controller side are required. There has been a problem that the development man-hour has to be increased, and as a result, the cost of the apparatus is inevitable.

Therefore, the present invention solves the above-mentioned problems, reduces the number of development steps in terms of both hardware and software on the controller side and hardly reduces the apparatus cost without changing the interface circuit on the printer side. An object of the present invention is to provide a printer interface device and a control method that can be implemented.

[0026]

According to a first aspect of the present invention, there is provided a printer interface apparatus for controlling transfer of print data from an information processing apparatus to a printer apparatus. And a memory for accessing the storage means in response to a print request from the printer apparatus, and transferring the print data to the printer apparatus by a plurality of burst transfers in units of an arbitrary data amount per line. Transfer control means for performing an access (DMA) transfer, and access priority control means for controlling access to the storage means from the transfer control means to be prioritized during a transfer period of one line of the print data. It is characterized by doing.

According to a second aspect of the present invention, in the first aspect of the present invention, the access priority control means determines that the one-line print data is specified by the printer device during the transfer of the one-line print data. Access frequency setting means for setting the access frequency so as to complete the transfer within a transfer acceptable time of one line of print data, and until the number of accesses from the transfer control means to the storage means reaches the set value. And an access rejecting means for rejecting another access to the storage means.

According to a third aspect of the present invention, in the first aspect of the present invention, a timing control means for providing the print request to the transfer control means, the timing control means being provided on the printer device side, respectively, A first-in first-out storage means for temporarily storing print data.

According to a fourth aspect of the present invention, in the first aspect of the invention, the transfer control means sets a data amount of one line of the print data and a number of lines of one page prior to the DMA transfer. Means for executing the DMA transfer in page units based on the setting information.

According to a fifth aspect of the present invention, in the first aspect of the invention, the transfer control means includes a line configuration requirement setting means for setting a data amount for one line of the print data prior to the DMA transfer. The DM based on the setting information
It is characterized in that A-transfer is executed for each line.

According to a sixth aspect of the present invention, there is provided a printer interface control method for transferring print data from an information processing device to a printer device, wherein the print data is stored in a storage means, and then a print request is sent from the printer device. In response to this, the storage unit is accessed, and the print data is transferred to the printer device by direct memory access (DMA) by a plurality of burst transfers in units of an arbitrary data amount per line. During the transfer period of one minute, the access to the storage unit for the DMA transfer is controlled so as to be prioritized.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the one-line print data is transferred during the transfer period.
The access frequency is set so that the transfer of the print data for one line is completed within the transfer acceptable time of the print data for one line specified by the printer device, and the number of accesses to the storage means reaches the set value. Until the above, the access priority control is performed by rejecting another access to the storage unit.

According to an eighth aspect of the present invention, in the invention of the sixth aspect, the printer device controls the timing at which the print request is issued, and stores the DMA-transferred print data by a first-in first-out storage means. It is characterized by temporarily storing.

According to a ninth aspect of the present invention, in the invention of the sixth aspect, prior to the DMA transfer, the data amount of one line of the print data and the number of lines of one page are set, and the DMA transfer is performed based on the setting information. It is characterized in that it is executed for each page.

According to a tenth aspect of the present invention, in the sixth aspect of the present invention, a data amount for one line of the print data is set before the DMA transfer, and the D amount is set based on the setting information.
It is characterized in that the MA transfer is executed for each line.

[0036]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing an overall configuration of an information processing system according to an embodiment of the present invention. The information processing system includes an information processing apparatus 10, a copying machine 20 for printing out print data provided from the information processing apparatus 10, and a controller 30 for controlling an interface between the information processing apparatus 10 and the copying machine 20. Is done.

The information processing apparatus 10 has an input unit 101, a display unit 102, and a data reading unit 103. For example, a data file input from a data reading unit 103 is input by an information editing unit 111 in the main unit. After performing an editing process in response to a key input from the unit 101, the input unit 1
In response to a print instruction from the printer controller 01, the print data generator 112 generates print data (print data) based on the document file edited by the information editor 111, and the controller 3
Send to 0. The controller 30 transfers the print data to the copier 20 under the interface control described later based on the print instruction, and the copier 20 prints out the print data transferred from the controller 30.

FIG. 2 is a block diagram showing the configuration of a printer interface device in this information processing system. The controller 30 has a DRAM 301 for storing print data from the information processing device 10, and a DRAM 301.
The DRAM controller 302, which controls access to write / read or refresh operations of the DRAM 301, has a function of changing the priority of the access, and print data stored in the DRAM 301 to the copier 20 in a direct memory format. Access (D
MA) is provided with a DMAC 303 for performing transfer control, and on the copying machine 20 side, an input timing controller 201 for controlling the timing of inputting print data from the controller 30, and the print transferred from the controller 30 by this timing control. Asynchronous FIF for temporarily storing data and sending it to the print processing unit of the copying machine 20 in a first-in first-out manner and asynchronously
An O memory 202 is provided.

In the interface control between the controller 30 and the copying machine 20 in the printer interface apparatus, the idea to specify the signals and timing on the basis of the ROS control of the copying machine to minimize the burden on the copying machine 20 is as follows. It is the same as the conventional system. However, according to the present invention, the copier 20 can cope with the above-described printer operation by controlling according to a general-purpose DMAC. On the other hand, the configuration of the controller 30 can be further simplified by a configuration according to a general-purpose DMAC, and a dedicated In order to eliminate the need for software, the following improvements have been added to the interface specifications.

(A) As an interface signal to the copying machine 20, a signal equivalent to that of a general-purpose DMAC is adopted instead of a signal which has been conventionally a dedicated signal.

(B) Conventionally, data transfer to the copying machine 20 has been performed by burst transfer of data for one line at a time. On the other hand, an arbitrary number of bytes (for example, up to 8 bytes) adopted by a general-purpose DMAC is used. A method is used in which one line of data is DMA-transferred by performing burst transfer a plurality of times (in units of words) as one unit.

(C) DMA multiple times per line
At the time of transfer, in order to prevent the circuit scale on the copying machine 20 side from increasing, one transfer is performed within one line transfer time specified by the copying machine 20.
Control is performed so as to end the DMA transfer of all print data for the line.

(D) The DMAC 303 sends the print data stored in the DRAM 301 to the copying machine 20 in order to guarantee the completion of transfer of all print data for one line within the transfer time of one line specified by the copying machine 20. During the transfer period, a DRAM controller 302 capable of variably setting the priority of the access frequency so as to increase the DRAM access frequency of the DMAC 303 is provided.

(E) DR being accessed by DMAC 303
The access frequency (PDMAC) of the AM 301 is set according to the following equation.

PDMAC> TD / (TC + TR) (1) TD = TDDMAC * (LineCount + R) / 32 (2) TC = THVALID-TD-TR (3) TR = TREF * RefCount ( RefCount ≧ THVALID / TRREF) (4) PDDMA: the CPU 113 or the DRAM 302 can access once after the DMAC 303 is operated by this number TD: Total time required for DMA transfer of data for one line TC: Transfer time for one line CPU 113 in DRAM
30 Total access time TR: Total time of DRAM refresh occurring within transfer time of 1 line TDMAC: Time required for 8-word transfer of DMAC 303 LineCount: Total number of pixels of 1 line (multiple of 32) R: 1 line The number of error pixels that cannot be divided by 32 by the total number of pixels THVALID: Transfer time of one line TREF: Time required for one DRAM refresh RefCount: DRAM generated within transfer time of one line
Number of refreshes TRREF: Refresh interval of DRAM 301 On the interface between controller 30 and copying machine 20, according to the printer interface apparatus (see FIG. 2) adopting the above-described configurations (a) to (e), the copying machine 20 side Without significantly changing the circuit configuration of the controller 30.
The interface circuit on the side can be constituted only by a general-purpose DMAC. Since the circuit on the controller 30 side can be configured only with a general-purpose DMAC, dedicated driver software is not required. That is, the copying machine 20 on the controller 30 side
The transfer of print data to can be performed only by software processing equivalent to the conventional file transfer. Therefore, when developing the interface between the controller 30 and the copying machine 20, both the hardware and software of the controller 30 can be significantly reduced in the number of development steps, and the hardware cost can be significantly reduced.

A specific configuration for satisfying the above requirement (a), that is, the requirement that the interface signal to the copying machine 20 be equivalent to that of the general-purpose DMAC will be described with reference to FIG. In the figure, changes from the conventional device are as follows.

In the prior art (see FIG. 6), the controller 30 constantly outputs VCLK to the copying machine 20.
Although D indicates the period during which DATA from the controller 30 is asserted, according to the present invention, VCLK is not always output, but is output only during the period when VALID is asserted, and the signal name is strobed. (STB). Thereby, the VALID signal is deleted. Also, DMAC30
3 sends DATA to the copying machine 20 in synchronization with the STB signal.

In the prior art (see FIG. 6), LREQ is
0 is always input to the controller 30, and only the LREQ when the PREQ is input from the copier 20 to the controller 30 is valid. On the other hand, in the present invention, LREQ is not always output, but a signal that is output only while PREQ is asserted. As a result, the PREQ signal is deleted. The LREQ signal is input to the DRAM controller 302.

Next, in the apparatus of the present invention shown in FIG. 2, the requirement (b) relating to the interface specifications, that is, the processing for transferring one line of print data from the controller 30 to the copying machine 20 by burst transfer of an arbitrary size is realized. The main points of the method are shown below.

DMAC 303 is a DMA of up to 8 words
Perform a transfer.

The DRAM controller 302 changes the DRAM access priority of the DMAC 303 after inputting LREQ. The DMAC 303 performs n times [n = (number of pixels in one line) according to the above formulas (1) to (4). / 32 + (remainder)].

The DMAC 303 outputs a LineEnd signal and stops DMA each time data transfer for one line is completed (see FIGS. 3 and 4).

When the LREQ is input again from the copying machine 20, the DMA is restarted.

When the data transfer of all the lines is completed, a DmaIrq signal (interrupt signal) is generated to end the DMA transfer.

On the copying machine 20 side, in order to be able to accept transfer of print data of an arbitrary size, an asynchronous FIFO memory 20 capable of asynchronously inputting data for one line is provided.
Use 2.

Next, the functional configuration of the DRAM controller 302 for guaranteeing the requirements (c) to (e) relating to the interface specifications, that is, ensuring that the transfer of one line of transfer data is completed within the transfer time of one line. The main points of are described below.

During the assertion period of LREQ during which the DMAC 303 is executing the DMA transfer, the DRAM controller 3
At 02, the priority of access to the DRAM 301 by the DMAC 303 is increased.

When the LineEnd is detected, the DRAM 301
Access priority to normal.

The access priority to the DRAM 301 is based on the value calculated by the above equation (1). In particular, in this embodiment, the PDMA
C = 6, and the DRAM controller 302
01, the number of accesses to the DRAM 301 is detected six times.
301 is permitted to be accessed.

FIG. 3 is a timing chart of each interface signal relating to the print data transfer processing based on the above interface specifications. (N PREQ) shown in FIG. 3A is a one-page unit synchronization signal generated inside the copying machine 20. (N LREQ) shown in FIG. 2B is a one-line unit synchronization signal input from the copying machine 20 to the controller 30, and is output only during the period when the PREQ is asserted. (N DmaIrq) shown in FIG. 9C is an internal signal of the controller 30 indicating a DMA end interrupt, which is output when data transfer of all lines is completed, and is used for DMA transfer end processing.

FIG. 7B is an enlarged view of the signal (n LREQ) shown in FIG. Of the enlarged signals on the time axis, (n STB) shown in FIG. 3D is a strobe signal of print data, and the DMAC 303 sends the print data to the copying machine 20 in synchronization with this signal. . In particular, in the present invention, the print data is DMA-transferred to the copying machine 20 by a plurality of burst transfers of an arbitrary data amount unit per line. Similarly, (n LineEnd) shown in FIG. 5E is an internal signal of the controller 30 indicating the end of data transfer of one line, and is output every time data transfer of one line is completed, and is used for DMA interruption processing. Can be

A procedure for transferring print data from the controller 30 to the copying machine 20 based on the interface specifications in the interface apparatus of the present invention shown in FIG. 2 will be described below with reference to FIGS.

In FIG. 2, the controller 30 sends print data to be sent to the copying machine 20 to the DRAM 301.
(Step 401). After the storage of the print data is completed, the start address of the print data is set in the DMAC 303 (step 402), and the number of words per line of the print data and the number of lines per page are set (step 4).
03, 404) Next, the controller 30 activates the DMAC 303 (step 405). Thereafter, the DMAC 303 monitors whether LREQ has been input from the copying machine 20 (step 406), and when LREQ has been input (step 406Y).
ES), the DRAM 301 is accessed to read out the print data therein in units of eight words, and the print data in units of eight words is burst-transferred to the copying machine 20 (step 407).

After the completion of the burst transfer, the DMAC 30
No. 3 completes the access to the DRAM 301 once, requests the access to the DRAM 301 again, and starts the burst transfer of the next 8-word print data. This process is repeated until the DMA transfer of the print data for one line is completed. When the transfer of the print data for one line is completed, LineEnd is output and the DMA transfer is interrupted.
Wait for REQ. Then, when LREQ is asserted again, the DMA transfer is restarted as described above.

In response to this processing, the DMAC 303 determines whether or not LineEnd is asserted after the completion of the burst transfer in step 407, that is, the D of the print data for one line.
It is determined whether or not the MA transfer has been completed (step 40).
8) If the DMA transfer of the print data for one line has not been completed (step 408 NO), the print data of the next eight words is read out from the DRAM 301 and burst-transferred to the copier 20 in the same manner as described above.

Then, the print data D for one line
When the MA transfer is completed and LineEnd is asserted (step 408 YES), the DMAC 303 determines whether DmaIrq has been asserted, that is, whether the DMA transfer of one page of print data has been completed (step 408). 4
09) If the DMA transfer of the print data for one page is not completed (NO in step 409), the DMA transfer of the print data of each line is continued by the above-described processing.

In this way, the DMAC 303 burst-transfers one line of print data to the copier 20 in units of eight words in a plurality of times, and every time the transfer of one line of print data is completed. , Temporarily suspends the DMA transfer and shifts to waiting for LREQ reception (step 40).
6). Here, when LREQ is asserted again, DMA transfer is restarted in the same manner as described above (step 407). When the above operation is repeated and the DMA transfer of the last line is completed, DmaIrq is generated (step 409YE).
S), end the DMA.

It should be noted that the processing in steps 403 and 404 in FIG.
This is a process in which the DMAC 303 that can set the number of lines of a page is used. However, a DMAC that cannot set such information may be used, and the DMA transfer may be changed to be performed in line units instead of page units. That is, in this modified example, the size of one line of print data is set as a unit of DMA, and every time the transfer operation of one line of print data is completed, the DMA is terminated and an interrupt is generated. Then, again, the DMAC 303
At the start of DMA, and waits for the input of LREQ. In this configuration, the LineEnd signal is not required. Thus, the circuit of the DMAC 303 can be simpler than that of the above embodiment, and the hardware cost can be further reduced.

By the way, as shown in the requirements (c) to (e) of the interface specifications, in the printer interface apparatus of the present invention, the DMAC 303
Upon transfer, the DRAM controller 302
By increasing the access frequency from 303 to the DRAM 301 more than the access frequency from other modules, the control is performed so that the DMA transfer is completed within the processing time for one line specified in the copying machine 20.

The priority order changing operation in DRAM controller 302 and the related operation of DMAC 303 will be described with reference to FIG. Here, FIG. 9A shows a state transition diagram in a process of raising the priority of the DRAM access of the DMAC 303 during the assertion period of the LREQ indicating the execution period of the DMA transfer. In particular, FIG. It is assumed that 6 is set. Also,
FIG. 3B shows the input form of each interface signal causing the state transition to the DRAM controller 302.

First, the operation when there is no DMA transfer to the copying machine 20 will be described. In the figure, [IDLE] of the DRAM controller 302 indicates a state where no access is made to the DRAM 301. Further, since the copier 20 has not requested the print data, the DMA is not activated. Here, if a refresh request for the DRAM 301 occurs, the state shifts to [REF],
Upon completion of the refresh process, the process returns to [IDLE].

If there is no refresh request, the CPU
If the 113 attempts to access the DRAM 301, the state moves to [CPU]. Here, when the CPU processing ends, the process returns to [IDLE]. When refresh and CPU access occur at the same time, refresh [REF] is performed first, and once the refresh ends, [IDL
After returning to [E], the DRAM access right is transferred to the CPU 113.

Next, DMA transfer to the copying machine 20 (DMA
(C operation) will be described. Copier 20
Is input to the DRAM controller 302, the state shifts to [IOT].

If the DMAC 303 requests data transfer (DmacReq), the state shifts to [DMAC]. If there is no data transfer request (DmacReq), refresh and CPU access are accepted as in [IDLE].
Refresh and CPU access priorities are the same as in [IDLE]. In the [ITO] state, the DRA
A value of Count = 0 is set in an internal counter of the M controller 302. When DmacReq occurs, the state moves to [DMAC]. DMAC 303 is 8-word DM
When the operation A is completed, the above-mentioned Count is incremented by one.
At this time, the state remains DDMARe
Wait for q. During this time, refresh and CPU access cannot be executed.

While repeating the processing operation in the [DMAC] state, when the value of the above Count matches the value of PDMAC, the DR
The AM controller 302 permits refresh or CPU access. In this embodiment, when DmacReq is processed six times, refresh or CPU access is permitted.

If both refresh and CPU access are requested, refresh is allowed. When either the refresh or the CPU access is completed, the state returns to [IOT], and C
ount = 0 is set. In the [DMAC] state,
If there is no request for both refresh and CPU access when t = PDMAC is detected, the state is reflected in [IOT] and Count = 0 is set.

By repeatedly performing the above processing,
When the data transfer for one line is completed, the DMAC 303
Outputs the LineEnd to the DRAM controller 302.
When this signal is input in the [DMAC] state, the DRAM controller 302 detects that the processing of one line has been completed, returns the state to [IDLE], and waits for LREQ to be input again.

[0078]

As described above, according to the present invention,
The storage device is accessed in response to a print request from the printer device, and the print data stored in the storage device is DMA-transferred to the printer device by burst transmission a plurality of times per line, and the print data for one line of the print data is transferred. During the transfer period, the access from the transfer control means to the storage means is controlled so as to be prioritized, so that the print data is stored in a FIFO or the like and then transferred according to the processing capability of the printer device. In addition, not only hardware such as a FIFO and transfer timing control means but also software for controlling the hardware and software are not required, so that development man-hours for both hardware and software can be reduced, and hardware cost can be significantly reduced.

Further, according to the present invention, by controlling the transfer control means to give priority to the access to the storage means during the DMA transfer, the print data can be completely transferred within the transfer reception processing time of the one line of print data in the printer device. An operation that completes the transfer can be guaranteed, and the reliability of the data transfer can be improved.

Further, according to the present invention, the printer device temporarily stores data burst-transferred from the transfer control means, in addition to the timing control means for issuing a print request to the transfer control means in the same manner as the general-purpose DMAC. This can be realized with a slight change by only adding a first-in first-out type storage means, and it is possible to minimize an obstacle to hardware simplification.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an information processing system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a printer interface device of the information processing system in FIG. 1;

FIG. 3 is a timing chart of each interface signal related to a data transfer operation of the printer interface device.

FIG. 4 is a flowchart illustrating a data transfer operation of the printer interface device.

FIG. 5 is a diagram showing a state transition related to access priority control in a DRAM controller.

FIG. 6 is a diagram showing a configuration of a conventional printer interface device.

FIG. 7 is a diagram showing a relationship between print data to be transferred and each interface signal in a conventional printer interface device.

FIG. 8 is a flowchart showing a data transfer operation of a conventional printer interface device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Information processing apparatus, 101 ... Input part, 102 ... Display part, 103 ... Data reading part, 111 ... Information editing part, 11
2. Print data generation unit, 113 CPU, 30 controller, 301 DRAM (Dynamic Random Access Me)
mory), 302 ... DRAM controller, 303 ... DM
AC (Direct Memory Access Controller), 20: copying machine, 201: input timing controller, 202:
Asynchronous FIFO (First-In First-Out)

Claims (10)

[Claims] 1. A printer interface device for controlling transfer of print data from an information processing device to a printer device, wherein the storage device stores the print data, and the storage device stores the print data in response to a print request from the printer device. Transfer control means for accessing the printing device by direct memory access (DMA) to the printer device by performing a plurality of burst transfers of the print data in units of an arbitrary data amount per line; An access priority control unit for controlling access to the storage unit from the transfer control unit during the transfer period. 2. The transfer priority control unit according to claim 1, wherein, during the transfer period of the print data of the one line, the print data of the one line is a transfer acceptable time of the print data of the one line defined by the printer device. Access frequency setting means for setting the access frequency to complete the transfer within, and access for rejecting another access to the storage means until the number of accesses from the transfer control means to the storage means reaches the set value. 2. The printer interface device according to claim 1, further comprising rejection means. 3. A timing control unit, which is provided on the printer device side and issues the print request to the transfer control unit, and a first-in first-out storage for temporarily storing the DMA-transferred print data. 2. The printer interface device according to claim 1, further comprising means. 4. The transfer control means includes page configuration requirement setting means for setting the data amount of one line of the print data and the number of lines of one page prior to the DMA transfer, and the DMA transfer based on the setting information. 2. The printer interface device according to claim 1, wherein the printer interface is executed for each page. 5. The transfer control means includes a line configuration requirement setting means for setting a data amount for one line of the print data prior to the DMA transfer, and executes the DMA transfer on a line basis based on the setting information. 2. The printer interface device according to claim 1, wherein 6. A printer interface control method for transferring print data from an information processing device to a printer device, wherein the print data is stored in a storage device, and the storage device responds to a print request from the printer device. And direct memory access (DMA) transfer of the print data to the printer device by a plurality of burst transfers of an arbitrary data amount unit per line, and during a transfer period of one line of the print data. , The DMA
A printer interface control method, characterized in that access to the storage unit for transfer is controlled so as to be prioritized. 7. During the transfer period of the print data of one line, the transfer of the print data of one line is completed within a transfer acceptable time of the print data of one line specified by the printer device. 7. The access priority control according to claim 6, wherein an access frequency is set, and the access priority control is performed by rejecting another access to the storage unit until the number of accesses to the storage unit reaches the set value. Printer interface control method. 8. The printer device controls the timing at which the print request is issued, and temporarily stores the DMA-transferred print data in a first-in first-out storage unit. 6. The printer interface control method according to 6. 9. The method according to claim 1, wherein a data amount of one line of the print data and a number of lines of one page are set prior to the DMA transfer, and the DMA transfer is performed in page units based on the setting information. 6. The printer interface control method according to 6. 10. The printer interface according to claim 6, wherein a data amount for one line of the print data is set prior to the DMA transfer, and the DMA transfer is executed for each line based on the setting information. Control method.