JP2000035938A - Data transfer method and device and image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the data transfer of high throughput while suppressing the capacity of a memory used as a buffer even in the case that a data transfer speed is different on the transmission side and reception side of data. SOLUTION: In the case of transferring the data from an image input/output device 101 to an image processing device 123, they are temporarily written to the memory of an interface block 116 and they are transmitted to the image processing device. At the time, as the memory, the capacity of Pmax* (1-Tf/Ts) is used. In this case, Pmax is a data amount to be transferred, Tf is the reciprocal of the transfer rate of the image input/output device and Ts is the reciprocal of the transfer rate of the image processing device 123. For both write and read, the memory of the size is repeatedly used. Also, the read on the reception side is started with slight delay from the write in the case that the transfer rate of the transmission side is high and the read is started after full data are temporarily written in the memory in the case that the transfer rate of the reception side is high. Also the slight delay is inserted at the time of writing the next block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for transferring image data between an image input / output device such as a multifunction copying machine and an image processing device such as a PDL or a facsimile.

[0002]

2. Description of the Related Art In a conventional image processing apparatus, an image input / output device and an image processing device generally have the same data transfer rate. Therefore, as shown in FIG. 7, in most cases, the image input / output device and the image processing device are directly connected, and the two transfer data in synchronization with each other (conventional example 1). In the case where the data transfer rates of the image input / output device and the image processing device are different, as shown in FIG. 8, a type in which a page memory is provided between the image input / output device and the image processing device (conventional example 2). )was there. In this type, both could perform data transfer at each timing by the page memory. The conventional example will be described below.

(Conventional Example 1) In FIG. 7, an image input / output device 701 has the following functions.

[0006] The control block 702 includes a CPU, an operation panel, and the like. The mechanism section 703 includes a document reading mechanism and a printing mechanism inside, and also includes a mechanism block such as a transport system, and is controlled by a control block 702 through a bus 705. An image signal 708 from the reading mechanism unit is a read image transfer timing signal 707.
At the same time, it is input to the image processing block 704.

An image signal 709 to the printing mechanism is input from the image processing block 704 together with a write image transfer timing signal 710.

The image processing devices 715 to 717 connected to the image input / output device 701 implement a PDL (page description language) and a facsimile function. Each of these image processing devices has a control block represented by a control block 718. The control block 718 includes a bus 721
It communicates with the control block 702 of the image input / output device 701 through the interface 701, and controls the image processing block 720 through the bus 719.

When reading image data such as a facsimile transmission, image data is read from the mechanism unit 703 under the control of the control unit 702, and the image processing unit 70
After the predetermined processing is performed in step 4, the image data is transferred to the image processing block 720 as image data 712 together with the read image transfer timing signal 711.

When printing image data such as FAX reception or PDL output, image data 714 is transmitted from the image processing block 720 to the image processing block 704 in synchronism with the writing image transfer timing signal 713, where the predetermined data is output. After the above processing is performed, it is sent to the mechanism section 703 and printed out.

(Conventional Example 2) FIG. 8 shows a block diagram of Conventional Example 2. The difference from the first conventional example in FIG. 7 is that a page memory block 816 is added. In the exchange of data between the image input / output device 801 and the image processing device 823, the difference between the image transfer rate of the device and the image transfer rate of the device is absorbed once through the page memory block 816.

When an image is taken in from the mechanism section 806 in the configuration of FIG. 8, the first image transfer is performed between the image processing block 811 and the page memory 816, and then between the page memory 816 and the image processing block 826. The second image transfer is performed. FIG. 9 shows an example of a graph of the amount of data transmitted and received by the memory block. The data transfer rate of the image input / output device (image processing block 811) is represented by θ1, the data transfer rate of the image processing device (image processing block 826) is represented by θ2, and the transfer data amount is represented by Pmax. First, the image processing block 811 sends data to the page memory 816 at the transfer rate θ1, and the page memory 816 stores the data. Next, the image processing block 816 reads data from the page memory at the transfer rate θ2.

In the case of outputting an image in the configuration shown in FIG. 8, the first image transfer from the image processing device 823 to the page memory 816 is performed, and then the second image transfer from the page memory 816 to the image input / output device 801 is performed. Perform a transfer.

[0012]

In the prior art 1, it is an essential condition that the image data transfer rate of the image input / output device and the image data transfer rate of the image processing device connected thereto are the same. Therefore, even if an image processing device developed for a certain image input / output device is to be connected to another image input / output device, it cannot be connected if the image data transfer rates are different.

In the second conventional example, a page memory is provided between the image input / output device and the image processing device, so that devices having different data transfer rates can be connected. However, there is a disadvantage that the cost for the page memory must be increased, and the throughput is reduced because the image data is transferred twice.

SUMMARY OF THE INVENTION The present invention has been made in view of the above conventional example, and a data transfer method and an image processing method capable of transferring data between devices having different transfer rates while suppressing a decrease in throughput and an increase in cost. It is intended to provide a device.

[0015]

In order to achieve the above object, the present invention has the following arrangement. That is, a first interface for inputting an image signal, a second interface means for outputting an image signal, a temporary storage memory, and a second interface for sequentially writing data input from the first interface to the temporary storage memory. 1
Memory control means, a second memory control means for sequentially reading data to be output to the second interface from the temporary storage memory, and an address of the temporary storage memory written by the first memory control means, And a second timing control unit for returning the address of the temporary storage memory read by the second memory control unit to the head, and transferring the data. Assuming that the total data amount is Pmax and the ratio of the time required to transfer a fixed amount of data by the first and second interface means is Tf / Ts, the first and second timing means place the address first. The return timing is when the transfer of data of Pmax * (1−Tf / Ts) is completed.

Alternatively, an image processing apparatus comprising the above data transfer apparatus, wherein the data transfer apparatus transmits or receives image data.

Alternatively, there is provided a data transfer method in which data is transferred from a data transmitting side to a receiving side having a lower transfer rate via a buffer memory. For each block of the size determined based on the transfer rate, data from the transmission side is written to the buffer memory, and after a predetermined time has elapsed from the start of writing data to the buffer memory from the transmission side, the reception To start reading data from the buffer memory to the side.

Alternatively, there is provided a data transfer method in which data is transferred from a data transmitting side to a receiving side having a higher transfer rate via a buffer memory. For each block of the size determined based on the transfer rate, write data from the transmission side to the buffer memory, and immediately after writing the first block from the transmission side to the buffer memory, buffer the buffer to the reception side. Data reading from the memory is started, and after a lapse of a predetermined time, the second and subsequent blocks are written to the buffer memory.

Alternatively, the computer writes data from the transmission side into the buffer memory for each block of a size determined based on the amount of data to be transferred and the transfer rate of each of the transmission and reception. After a lapse of a predetermined time from the start of writing data to the memory, reading of data from the buffer memory to the receiving side is started, and a buffer is transmitted from the data transmitting side to the receiving side having a lower transfer rate. A computer-readable storage medium for storing a program for realizing data transfer for transferring data via a memory.

Alternatively, the computer writes data from the transmission side into the buffer memory for each block of a size determined based on the amount of data to be transferred and the transfer rate of each of the transmission and reception. As soon as the first block has been written to the memory, reading of data from the buffer memory to the receiving side is started, and after a lapse of a predetermined time, the second and subsequent blocks are written to the buffer memory to transmit data. A computer-readable storage medium for realizing a data transfer method for transferring data via a buffer memory from a side to a receiving side having a higher transfer rate.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the present invention based on embodiments, a basic concept will be described. Here, two image input / output devices are defined, and a description will be given for a case where an output with a high transfer rate is received at a low transfer rate and a case where an output with a low transfer rate is received at a high transfer rate.

(1) A case where an output having a low transfer speed is received at a high transfer speed This is applied to a case where a PDL processing section having a low processing speed is connected to a high-speed printer engine. Hereinafter, for convenience of description, the PDL and the engine will be described. PDL is a processing function for generating data suitable for a printer engine from data described in a page description language.

FIG. 6 is a conceptual diagram of the operation. 6, the horizontal axis indicates time, and the vertical axis indicates the amount of transferred data. Line 6
01 indicates image transfer to the engine, and line 602 indicates PDL
Shows the transfer of images from. The transfer rate on the engine side is PD
Since it is higher than the data transfer rate of L, θ1> θ2.

In this case, in order to establish the data transfer from the PDL to the engine, in the present invention, as shown in FIG. 6, the image output from the PDL having the lower transfer rate is started first, and until the time T1. The data is stored in the memory (hereinafter, this operation is referred to as pre-reading), and from time T1, the data is transferred from the memory to the engine in parallel with the image output from the PDL. That is, the PDL writes the data amount Px of the data to be transferred to the memory at the time T1 by the pre-read operation, and after the time T1, the PDL continues to write the data to the memory at a slow rate (slope θ2). Read from the memory at a fast rate (slope θ1). At time T1, the data reading on the engine side is
It is determined that the data transfer ends at time T2 without overtaking the data writing on the side.

The data transfer time of the PDL required to transfer the data Pmax is Tpdl, and the data transfer time of the engine is Tpdl.
It can be seen from FIG. 6 that when eng is used, the phase required time required for the transfer is Tpdl + Teng in the conventional example of FIG. 9 but becomes Tpdl in the present invention.

Next, a method for controlling the memory will be described. In FIG. 6, during the time until time T1, P
Data sent by the DL is sequentially written to the memory.
That is, assuming that storage in the memory starts from address 0, the write address is sequentially incremented from 0, and data is written up to Px. Then, at time T1, the engine starts reading data from address 0. Almost at the same time, the PDL returns the write address to 0 and performs the write operation.

Thereafter, both of them write or read data while incrementing the address until the data transfer is completed, and the data transfer address becomes Px
, The operation of returning the address to 0 is continued. When the address returns to 0, data transfer is repeated from time 0 in FIG. Access to the same address from both at time T1 and T2 will be described later.

As described above, the required memory capacity is not Pmax as in Conventional Example 2, but data transfer is possible if Px is smaller than Pmax.

Here, the time required to transfer the data of the data amount Pmax by the PDL and the engine is Tpd, respectively.
1, Teng. That is, Tpdl = T2-T
1, Teng = T2. Further, the data amounts transferred by the PDL and the engine at a certain time t are Ppdl and Peng, respectively. A graph expressing this as a function of time is the lines 601 and 602 in FIG. Ppd
l and Peng can be expressed as follows.

Ppdl = (Pmax / Teng) t + (Tpdl−Teng) Formula 1 Peng = (Pmax / Tpdl) t Formula 2 The required memory capacity is the maximum memory amount used from time 0 to T2. Px, where Px is t = Te
Since it is the value of Ppdl at the time of ng-Tpdl, Px = Pmax * (1-Teng / Tpdl) Formula 3

That is, the required memory amount Px depends on Teng / Tpdl, which is the ratio of the processing time of the two, and this value is 0
In the case of (1), Px = Pmax as in the conventional method, and Px decreases as the required transfer time on both the transmission side and the reception side approaches, and if they match, Px = 0.

FIG. 13 is a conceptual diagram of the control of the memory, and it is assumed that the ratio of the processing time between the engine and the PDL is 2: 3. That is, from equation 3, Px is Pm
The data amount Px is written into the memory three times by PDL, read out of the memory three times by the engine, and the data amount Pmax is transferred to the engine.

A solid line in FIG. 13 indicates a memory access of the DMA on the PDL side, and a dotted line indicates a memory access of the DMA on the engine side. PDL in the pre-reading time until time T1
Writes data from 0 to Px, and thereafter the engine reads the written data. It can be seen from this figure that the solid and dotted lines do not intersect,
At T1 and T2, if the contention between writing and reading is successfully processed, data transfer is possible.

(2) A case where an output having a high transfer rate is received at a low transfer rate This is applied to a case where an interface board (having no page memory) having a low processing speed is connected to a high-speed scanner engine.

For convenience of explanation, the scanner will be described as SCN and the interface board will be described as IFB.

FIG. 4 shows a conceptual diagram of the operation. In the figure, the horizontal axis indicates time, and the vertical axis indicates the amount of transferred data.

Line 401 indicates SCN image transfer, and line 4
02 indicates an IFB image transfer. Since the transfer rate on the SCN side is higher than IFB, the angles θ1 and θ2 formed by the lines 401 and 402 with respect to the horizontal axis satisfy θ1> θ2.

In order to establish the data transfer in this configuration, unlike the case (1), the image transfer of the SCN and the IFB
At the same time, and the IFB side reads out the data to be written to the memory at a high speed by the SCN side at a low speed.

This operation is performed until time T1 (SCN ends data transfer at T1), and thereafter, only the IFB continues reading data from the memory and ends at T2.

The data transfer time of the SCN is Tscn, IF
Assuming that the data transfer time of B is Tifb, Tscn + Tifb in the conventional example of FIG. 9 is only Tifb in the present invention.

Next, a method of controlling the memory will be described.

In FIG. 4, SCN and IFB simultaneously start data transfer, that is, write data while sequentially incrementing from SCN address 0, and read data while IFB also sequentially increments from address 0.

In this case, since the data transfer on the SCN side is faster, the write side precedes, and the amount of data written and waiting to be read increases gradually. In FIG. 4, the data waiting to be read are indicated by lines 401 and 402.
This is shown as the region between

Assuming that the data transfer time of the scanner in FIG. 4 is Tscn and the data transfer time of the interface board IFB is Tifb, the data amount Pscn transferred by the SCN and the data amount Pifb transferred by the IFB are expressed by the following equations, respectively. It is represented as

Pscn = (Pmax / Tscn) t Equation 4 Pifb = (Pmax / Tpdl) t Equation 5 The amount of data to be stored in the memory is an area between the line 401 and the line 402, and this is the maximum. Is at time T1
Is also apparent from FIG. This value is defined as Py. Here, from the same viewpoint as in (1), it is assumed that the required memory capacity is Py, and the control of the memory address is incremented from 0 in each of writing and reading, and the control is performed by returning to 0 when Py is reached. . In other words, the required memory is not Pmax, which is one page, as in the conventional example, but data can be transferred using a memory having a capacity of Py. Here, Py is a difference in the data transfer amount at the time Tscn, and can be expressed by the following equation.

Py = Pmax * (1-Tscn / Tifb) Equation 6 That is, the required memory amount Py depends on Tscn / Tifb, which is the ratio of the transfer time of the two, and when this value is 0, the same as in the conventional method. Py = Pmax, and the transfer time ratio is 1
Py decreases as it approaches, and if they match, Py
= 0.

FIG. 12 is a conceptual diagram of the memory control. The solid line in the figure indicates the memory access of the DMA on the IFB side, and the dotted line indicates the memory access of the DMA on the SCN side. Further, the ratio of the transfer time between SCN and IFB is set to 2:
3 is shown. In this case, the data amount Px
Is written to the memory three times by the SCN, and read from the memory three times by the IBF, and the data amount Pmax is transferred.

It can be seen from this figure that the solid line and the dotted line do not intersect, and that data transfer is possible if the conflict between writing and reading is successfully processed at the start and T1.

[First Embodiment] FIG. 1 is a block diagram of an image processing system according to the present invention. The image input / output device 101 includes the following functions.

The control block 103 includes a CPU, an operation panel, and the like. The mechanism section 106 includes a document reading mechanism section and a printing mechanism section inside, and also includes a mechanism block such as a transport system, and is controlled by the control block 103 through the bus 102.

The image signal 108 from the reading mechanism is
It is input to the image processing block 111 together with the read image transfer timing signal 107.

The image signal 110 to the printing mechanism is input to the image processing block 111 together with the write image transfer timing signal 119.

The image processing block 111 performs predetermined image processing under the control of the control block 103 via the bus 104, and performs timing signals 112 for the reading system.
Block 1 based on the image signal 113
16 and the write system is a timing signal 22
4 and the image signal 115, the interface block 116
Connected to

The interface block 116 is connected to the control block 103 via the bus 105.

Image processing devices 121, 122, 123
Is an image processing device such as a facsimile or PDL, and has a control block 124 and an image processing block 126, respectively. The control block 124 is connected to a control block 103 inside the image input / output device 101 via a bus 127. The control block 103 controls the image processing block 126 via the bus 125.

The exchange of image signals between the image input / output device 101 and the image processing devices 101 to 103 is performed via the interface block 116.
18 and the read image transfer timing signal 117 are connected to each image processing device, and the writing system is connected to each image processing device by the image signal 120 and the write image transfer timing signal 119.

FIG. 2 is a detailed diagram of the interface block 116 in FIG. Read control block 20
Reference numeral 1 denotes a sub-scanning synchronization signal 112A and a main scanning synchronization signal 112 as read image timing signals from the apparatus side.
B, receives the reference clock 112C.

The sub-scanning synchronization signal 117A,
It outputs a main scanning synchronization signal 117B and a reference clock 117C.

The control block 205 of the writing system receives a sub-scanning synchronization signal 114A, a main scanning synchronization signal 114B, and a reference clock 114C as a writing image timing signal from the apparatus side.

As the image timing signal to be written to the image processing device, a sub-scanning synchronization signal 119A,
It outputs a main scanning synchronization signal 119B and a reference clock 119C.

The control register 203 for performing a series of controls is:
The setting is made from the control block 103 inside the image input / output device 101 through the bus 105, and the control of the reading control block 201 and the writing control block 205 is performed through the buses 202 and 204.

The bus arbitration block 208 is connected to the read control block 201 via the buses 206 and 207, and is connected to the write control block 205 via the buses 209 and 210, and arbitrates memory accesses from the four buses. And connects to the memory devices 212 to 214 through the memory bus 211.

FIG. 3 shows the read control block 20 in FIG.
1 is a detailed view of FIG. 301 is an input control block,
302, an input video timing control block;
03 is an input video data control block, and 304 is an input DMA control block.

The output timing control block 305 generates timing signals 117A to 117C to the device side.

Reference numeral 307 denotes an output control block;
Is an output video timing control block, 309 is an output video data control block, and 310 is an output D
This is the MA control block.

A series of control registers 312 are connected to the input control block 30 by buses 311, 306 and 313, respectively.
1. Connected to output timing control block 305 and output control block 307.

FIG. 5 shows the write control block 20 in FIG.
FIG. 5 is a detailed view of FIG. Reference numeral 501 denotes an output control block,
Reference numeral 502 denotes an output video timing control block.
03 is an output video data control block, and 504 is an output DMA control block.

The input timing control block 505 generates timing signals 119A to 119C for the device.

Reference numeral 507 denotes an input control block.
Is a video timing control block, 509 is an input video data control block, and 510 is an input DMA
It is a control block.

A series of control registers 512 are connected to the input control block 50 by buses 511, 506, and 513, respectively.
1. Connected to output timing control block 505 and output control block 507.

Next, the operation in the following case will be described based on the above configuration. (1) When the data reception speed of the image output device is lower than the data transmission speed of the image processing device (when the output having a higher transfer speed is received at a lower transfer speed) (2) The image input is performed based on the data reception speed of the image processing device When the data transmission speed of the device is slow (when an output with a low transfer speed is received at a high transfer speed) (3) When the data transmission speed of the image input device is faster than the data reception speed of the image processing device (output with a high transfer speed) (4) When the data reception speed of the image output device is faster than the data transmission speed of the image processing device (when the output having a lower transfer speed is received at a higher transfer speed). Each will be described.

(1) When the data transmission speed from the image input device is higher than the data reception speed of the image processing device (when an output with a high transfer speed is received at a low transfer speed:
(Equivalent to FIG. 4) The description will be made under the following conditions.

The image data is 600 dpi on A3 paper, and the effective image is 8 Kdots in main scanning / 9.5 Kdos in sub-scanning.
Assume that the image input / output device reads the data with a multi-level scanner in two seconds, and the image processing device side converts the data into a binary image (which performs a binarization process inside the device) by 2.5.
Processing is performed in seconds (total data amount after binarization is 7.9 MB).

When the power of the apparatus is turned on by a power switch (not shown) in FIG. 1, the control block 103 performs a series of initial processing, recognizes the connected image processing devices 121 to 123, and To acquire information on the functions and transfer rates of image data.

Next, when a job for taking image data into the image processing device 123 is designated by any input means such as an operation panel, the control block 103 causes the bus 127
Control block 1 inside the image processing device 123 through
24 is notified of the job.

The control block 124 receiving the job notification
Sets the image processing block 126 via the bus 125 and notifies the image input / output device of an image transfer request when image input preparation is completed.

Upon receiving the image request, the control block 103 performs a series of image processing settings (shading correction, edge processing, and binarization processing) on the in-device image processing block 111.

The reading setting is performed on the interface block 116 through the bus 105. At this time, the following setting is performed on the reading control block 201 inside the interface block 116.

In the input timing control block 302, the offset of the effective image corresponding to the input image processing with respect to the main and sub timing signals and the number of effective pixels in each of the main scanning and sub scanning directions are set. Note that the directions of the main scanning and the sub-scanning are simply referred to as main and sub.

The input data control block 30 sets that the input image is binary.

For the input DMA control block 304, to secure a memory area used for image transfer, D
Set MA start address and memory size.

The output timing control block 305 is set to generate a timing signal for realizing the transfer rate notified from the device.

In the output timing control block 305, an offset for the main and sub timing signals of the effective image according to the device and the number of main and sub effective pixels are set.

The output data control block 309 sets that the output image is binary.

For the output DMA control block 310, in order to secure a memory area used for image transfer, D
Set MA start address and memory size.

FIG. 11 shows basic image timing.
The main and sub offsets LM and TM are values unique to the image input / output device and the image processing device, respectively, and the number of effective pixels DOT and LINE of the main and sub are basically different between the image input / output device and the image processing device. Set the same value. At the time of data transfer, if necessary, an image can be cut out or a margin can be added. However, the same is used here for simplification of description.

Next, the memory size in the above description will be described. The memory size is Py described in the explanation 2 of the basic concept, and can be expressed by the following equation.

Py = Pmax * (1-Tsca / Tifb) Equation 6 At the time of data transmission, Pmax / Py = Tifb / (Ti
Data transfer is performed by repeating writing to and reading from the memory fb-Tsca) times.

By substituting the assumed number into the above equation, Py
The theoretical value of Py = 7.9 MB * (1-2 / 2.5) = about 1.58 M
B. Write and read to and from this memory
/(2.5-2)=5 repetitions of data transfer.

It should be noted here that the offset from the output of the sub-scanning timing signal is set in both writing to and reading from the memory. The writing to the memory may be started after the time corresponding to the sub-scanning offset has elapsed from the output of the sub-scanning timing signal by setting the sub-scanning offset on the image input / output device side. However, in order to read from the memory to the image processing device at the same time as writing to the memory, the sub-scanning timing signal on the image processing device side starts reading at the same time as writing to the memory after the offset time has elapsed. Must be output as it is. If the transfer speeds of the image processing device and the image input / output device are different, there is a high risk that data read start timing is shifted and a situation occurs in which data is read out before writing.

Therefore, at the theoretical timing of FIG. 4, the start of writing and the start of reading are simultaneous. However, in practice, it is desirable to output the sub-scanning timing signal on the image processing device side after the start of writing. Also, considering the case where the offset on the image processing device side is 0,
It is desirable to output a sub-scanning timing signal to the device after at least one line of writing operation is completed.

That is, in FIG. 11, the effective image data amount Pma
Although x is represented by DOT * LINE, it is actually an amount obtained by adding the sub-scanning offset of the image processing device and the margin. That is, if the margin is three lines, Pmax = DOT * (LINE + TMd + 3) Equation 7 (TMd is a sub-scanning offset of the image processing device, and 3 is a margin).

Returning to the description of the operation. After setting each register in the interface block 201, the control block 103 actually starts an image scanning operation (description of the image reading apparatus is omitted).

Then, in the read control block 201 in the interface block 116, the input data control block 30 reads the effective image after the main / sub offset.
The binary image data read and executed by the S.1 is serial-parallel converted to the width of a memory bus (assumed to be 16 bits) in order to write it into the memory 212, and
6, the memory bus 211 via the bus arbitration unit 208
It is written to the head address (tentatively, 0) of the memory 212 via Thereafter, data converted in parallel in units of 16 pixels is written while the memory address is incremented, and when reading of one line is completed, the bus 311
To the control register 312 via the

The control register 312 instructs the output timing control block 305 via the bus 306 to start data transfer to the image processing device.

Then, the output timing control block 305
Outputs a sub-scanning timing signal on the image processing device side synchronized with the main scanning timing signal on the image processing device side. This signal notifies the image processing device 124 via the bus 117 of the start of image transfer. At the same time, the output control block 307 starts a series of operations for reading and transmitting the contents of the memories 212 to 214.

The above operation is repeated, and the operation of returning the address counter to 0 when the memory address becomes Py is repeated in both reading and writing. If the start address is not 0, the address counter is reset to 0 when the address reaches the start address + Py.

By this operation, the data transfer on the image input / output device side is finished after 2 seconds, and all data transfer is finished about 0.5 seconds later.

FIG. 15 is a diagram showing a state of writing data to the memory (dotted line) and reading data from the memory (solid line) when the memory is secured according to the equation (7). However, the figure shows the case where Pmax / Py = 3.

Py ′ is given by Pmax = D given by equation (7).
This is the memory capacity obtained by applying Expression 6 for OT * (LINE + TMd + 3). That is, when the data size of the effective area is Pmax, Py ′ = (Pmax
+ DOT * (TMd + 3)) * (1-Tsca / Tif
b). Since Py ′> Py, Pmax
/ Py ′ <3, and the number of times of reading / writing from / to the memory for Pmax data transfer is less than three. Further, the delay Ts of the memory read start time with respect to the write start time corresponds to a transfer time of (TMd + 3) lines in the image processing device. Since the amount of data written to the memory does not change at Pmax, the data writing ends at time T1. Since reading of data from the memory is started with a delay of time Ts from writing, the ending time is delayed by Ts from T2 which is a theoretical value. With this delay and extra memory,
It does not happen that the data write address overtakes the data read address and unread data is overwritten with new data.

FIG. 17 shows a flowchart of the above control procedure. First, a necessary memory capacity Py ′ is determined, a memory area is secured, and a head address is determined (step S1701). Next, the data read delay time Ts
Is set in the timer (step S1702). next,
The data to be transmitted is written to the memory in block units (step S1703). It is determined whether the writing of all data to the memory has been completed (step S1704). If the writing has been completed, the writing process ends. If not, the writing of data to the memory is repeated for each block.

When the timer set in step S1702 in FIG. 17 expires, data reading is started according to the procedure in FIG. However, the block size of the data to be read is Py '.

In FIG. 18, first, the start address determined in step S1701 of FIG. 17 is set as the start of the read address (step S1801), and data is read from the memory for each block (step S18).
02). This is repeated until all data is read (step S1803).

By such a procedure, the data transfer as shown in FIG. 15 can be realized.

(2) When the data reception speed of the image output device is higher than the data transmission speed of the image processing device (when an output having a low transfer speed is received at a high transfer speed: equivalent to FIG. 6). I do. Image data is 60 on A3 paper
0 dpi, the effective image is 8 Kdots in main scanning / 9.5 Kdots in sub-scanning, the image input / output device prints out the above data in 2 seconds by a binary printer, and the image processing device outputs the binary image data of the above size. Process in 2.5 seconds (total data amount is 7.9 MB).

When the power of the apparatus is turned on by a power switch (not shown) in FIG.
Performs a series of initial processing, recognizes the connected image processing devices 121 to 123, and acquires information on the function of each image device and the transfer rate of image data.

Next, when a job for outputting an image from the image processing device 123 is designated by any input means such as an operation panel, the control block 103 transmits the control block 124 inside the image processing device 123 through the bus 127.
To notify the job.

The control block 124 receiving the job notification
Sets the image processing block 126 via the bus 125 and notifies the image input / output device of an image transfer request when the image output preparation is completed.

Control block 103 receiving an image transfer request
Performs a series of image processing settings to the image processing block 111 in the image input / output device.

The output is set to the interface block 116 through the bus 105. At this time, the output timing control block 502 in the write control block 201 (FIG. 5) in the interface block 116 is in accordance with the output image processing. The offset of the effective image with respect to the timing signals of main scanning and sub-scanning, and the number of effective pixels in each of the main and sub-scanning directions are set.

An output data control block 503 sets that the output image is binary.

For the output DMA control block 504, a DMA start address and a memory size are set in order to secure a memory area used for image transfer.

To the output timing control block 505,
It is set to generate a timing signal for realizing the transfer rate notified from the image processing device.

To the input timing control block 508,
The offset of the effective image with respect to the timing signal of each of the main and sub scanning according to the image processing device and the number of effective pixels in each of the main and sub directions are set.

An input data control block 509 sets that the input image is binary.

For the input DMA control block 510, a DMA start address and a memory size are set to secure a memory area used for image transfer.

As shown in FIG. 11, the main and sub offsets are unique values, and the number of main and sub effective pixels is basically set to the same value for both input and output. If necessary, it is possible to cut out the image, add a margin, and the like, but they are the same here for simplification of the description.

Next, the memory size in the above description will be described.

The memory size is Px described in the explanation 2 of the basic concept, and can be expressed by the following equation.

Px = Pmax * (1-Tscn / Tifb) Equation 6 'According to the assumption, this value is theoretically calculated as Px = 7.9 MB * (1-2 / 2.5) = about 1.58 M
B. It should be noted here that the image input / output device cannot immediately take in the data after the pre-read operation is completed, and the TM shown in FIG. 11 is required. Therefore, after the pre-read operation is completed, it is necessary to mask the main scanning timing signal to the image processing device so as to make the image processing device wait for data transfer.

In order to start data transfer on the image processing device side again after starting the image input / output device,
Although the masking of the main scanning timing signal is canceled, a time corresponding to a maximum of one line is required because the timings of both are asynchronous.

Actually, after the reading by the image input / output device starts, the main scanning timing signal should be output to the image processing device after the reading operation of at least one line is completed.

That is, in FIG. 11, the effective image Pmax is DO
Although represented by T * LINE, actually, Pmax = DOT * (LINE + 3) Expression 8 (3 is a margin).

Returning to the description of the operation. As described above, after each register setting of the interface block 116 is performed, the control block 103 performs a sheet feeding operation for printing out (the description regarding the printing apparatus is omitted).

The data transfer on the image processing device side is started by the timing control block 505 inside the write control block 205 in the interface block 116.

The input timing control block 508 causes the input data control block 509 to take in an effective image after the offset in each of the main and sub scanning directions. The input binary image data is serial-parallel converted to a memory bus (tentatively 16 bits) width for writing to the memory, and is transferred to the memory 214 via the bus arbitration block 208 via the bus arbitration block 208 and the memory bus 211. At the start address (tentatively, 0). Thereafter, the data converted in parallel in units of 16 pixels is written while the memory address is incremented. When the data of the set size Px is transferred to the memory, the main scanning timing signal is masked to stop the data transfer on the image processing device side. Here, the write address counter is cleared to zero.

Then, the input control block 507 notifies the control register 512 via the bus 513 of the end of the prefetch operation, and further notifies the control block 103 inside the image input / output device 101.

When the control block 103 detects that the pre-reading operation has been completed, it starts the printing operation.

When the printing operation is started, the output control block 501 in the write control block 205 starts the operation via the bus 114, and after a predetermined offset, the bus 20 is turned off.
9, the data is read from the memory via the bus arbitration block 208, the output data control block 503 converts the data from parallel to serial, and outputs the print data to the image processing block 111 via the bus 115.

Thereafter, the data output is continued while incrementing the memory address in units of 16 dots, and when the output of one line is completed, the control register 512 is notified to the control register 512 via the bus 511 of the resumption of the data transfer on the image processing device side. . The control register 512 notifies the timing control block 505 of the fact via the bus 506, and the main scanning timing signal to the image processing device is restarted.

In the above operation, when the memory address in each of the reading and the writing becomes Px, the operation of returning the address counter to 0 is repeated. If the head address of the memory area to be used is not address 0, the address counter is returned to the head address when the address becomes + Px.

By such an operation, the data transfer on the image input / output device side ends after 2 seconds, and the data transfer on the image processing device side ends about one to two lines ahead (by margin 3).

FIG. 16 is a diagram showing how data is written to the memory (solid line) and data is read from the memory (dotted line) when the memory is secured according to the equation (8). P
y ′ is given by Pmax = DOT * (LIN
E + 3) is the memory capacity obtained by applying Equation 6 ′. That is, the data size of the effective area is set to Pmax
, Py ′ = (Pmax + DOT * 3) * (1
−Tsca / Tifb). The delay Td of the memory write start time with respect to the read start time
2 corresponds to a transfer time for three lines in the image processing device. The amount of data written to the memory is Pmax
Therefore, the data writing ends after a delay Td2 from the time T2. On the other hand, the reading of data from the memory is started with a time required for writing (Px′−Px) delayed with respect to FIG. Therefore, the time at which the reading ends is also delayed by Td1 from T2, which is the theoretical value. Here, if the delay Td1 is set to be larger than Td2, it is possible to prevent a situation in which the data read address exceeds the data write address and the same data is read twice.

FIG. 19 shows a flowchart of the above control procedure. First, the necessary memory capacity Px ′ is determined, a memory area is secured, and the start address is determined (step S1901). Next, the data to be transmitted is written in the memory (step S1902). In addition, this writing,
This is performed in block units by DMA transfer. In this case, the size of the block is P except for the last transfer loop.
x 'and the remaining data size in the last transfer loop. Next, it is determined whether writing of all data to the memory has been completed (step S1903).
The writing process ends.

Next, it is determined whether the transferred data is the first block (step S1904). If so, reading is started from the written head address (step S1905), and a timer or the like is used. And waits for the time Td2 (step S1906).
Thereafter, writing of data to the memory is repeated for each block.

The read processing procedure started in step S1905 is as described with reference to FIG.

By such a procedure, data transfer as shown in FIG. 16 can be realized.

If the memory capacity has a margin, the function of not resetting the address counter to 0 even when the memory address becomes Px in the above operation at the time of printing a plurality of copies of the same image is included in the first page. At the end of the transfer, the image for one page is fetched into the temporary storage memory, so that the second and subsequent pages can be output at the image transfer rate of the apparatus regardless of the device side.

(3) When the data transmission speed of the image input device is higher than the data reception speed of the image processing device (when an output with a high transfer speed is received at a low transfer speed: equivalent to FIG. 4). ).

(4) When the data reception speed of the image output device is higher than the data transmission speed of the image processing device (when an output having a low transfer speed is received at a high transfer speed: equivalent to FIG. 6). ).

As described above, according to the configuration of this embodiment,
Image processing devices with different processing capabilities (FAX and PDL
) Can be connected to an image input / output device.

In the case of the memory, Pmax * (1−Td / Ts) where Td is the data transfer time on the device side and Ts is the data transfer time on the device side instead of one page.

The throughput is Ts + Td in the conventional example.
Can be processed only by Td.

When outputting a plurality of parts, the memory address is set to 0.
By prohibiting the operation of returning to, the second and subsequent pages can be output at the original throughput of the apparatus. [Second Embodiment] FIG. 10 is a block diagram of a second embodiment of the present invention, in which an interface block is provided on the image processing device side.

The image input / output device 1001 has the following functions.

A control block 1003 has a CPU inside.
And an operation panel.

The mechanism section 1006 includes a document reading mechanism and a printing mechanism, and also includes a mechanism block such as a transport system.
3 is controlled. Image signal 10 from reading mechanism
08 is input to the image processing block 1011 together with the read image transfer timing signal 1007.

The image signal 1010 to the printing mechanism is connected to the image processing block 1011 together with the write image transfer timing signal 1019.

The image processing block 1011 includes the bus 100
4, a predetermined image processing is performed by the control block 1003, and for the reading system, the timing signal 1012 and the image signal 1013 are converted into image processing devices 1021 to 1022.
Enter 3

Further, the write system includes the timing signal 101
4 and the image signal 1015 are output from the image processing device 1021
To 1023.

The image processing devices 1021 to 1023
An image processing device such as a facsimile or a PDL includes a control block 1024, an image processing block 1026, and an interface block 1016. The control block 1024 is connected to the image input / output device 10 via a bus 1027.
01 is connected to a control block 1003 inside, and controls an image processing block 1026 via a bus 1025. The interface block 1016 is connected to the control block 1024 via a bus 1005, and has an input timing bus 1017, an input data bus 1018,
The output timing bus 1019 and the output data bus 10
At 20, it is connected to an image processing block 1026.

Next, the operation will be described based on the above configuration.

(1) Image Capture When the power of the image input / output device is turned on by a power switch (not shown) in FIG.
Performs a series of initial processing, recognizes connected devices 1021 to 1023, acquires information such as functions of each device, and notifies each device of an image transfer rate of the apparatus.

Next, when a job for taking image data into the image processing device 1023 is designated by some input means such as an operation panel, the control block 1003
A job notification is sent to the control block 1024 inside the image processing device 1023 through 027.

Upon receiving the job notification, the control block 102
4 sets the image processing block 1026 via the bus 1025 and performs predetermined settings on the interface block 1016 via the bus 1005. When the image input preparation is completed, the image input / output device is notified of the image transfer request.

Control block 1003 receiving an image request
Is the image processing block 10 in the image input / output device 1001.
A series of image processing settings (such as shading correction and edge processing) are performed on the image data 11 to perform an image capturing operation. The settings and operations of the interface block 1016 are the same as in the first embodiment, and a description thereof will be omitted.

(2) Output of Image When the power of the apparatus is turned on by a power switch (not shown) in FIG. 10, the control block 1003 executes a series of initial processing, and executes a series of initial processing.
21 to 1023 are recognized, information such as the function of each device is obtained, and the image transfer rate of the device is notified to each device.

Next, when a job for printing and outputting an image is designated from the image processing device 1023 by any input means such as an operation panel, the control block 1003
A job notification is sent to the control block 1024 inside the image processing device 1023 through 027.

The control block 102 which has been notified of the job
4 is an image processing block 1026 through a bus 1025.
Is set, and a predetermined setting is performed on the interface block 1016 via the bus 1005 to perform a prefetch operation.

When the pre-reading operation is completed and the image output preparation is completed, an image transfer request is notified to the apparatus.

Control block 1003 receiving an image request
Performs a series of image processing settings to the in-device image processing block 1011 to perform a print output operation.

The setting and operation of the interface block 1016 are the same as those in the first embodiment, and a description thereof will be omitted.

According to this embodiment, an image processing device (FAX, PDL, or the like) that can be connected to apparatuses having different processing capabilities can be realized.

In the memory, if the data transfer time on the device side is Td and the data transfer time on the device side is Ts instead of one page, Pmax * (1-Td / Ts).

The throughput is Ts + Td in the conventional example.
Can be processed only by Td. [Third Embodiment] FIG. 14 is a block diagram of an image copying apparatus according to a third embodiment of the present invention. This fusing device has a configuration having an interface block between an image input unit and an image output unit.

Image copying apparatus 1401 has the following functions.

The control block 1403 includes a CPU, an operation panel, and the like inside.

The mechanism section 1406 includes a document reading mechanism and a printing mechanism, and also includes a mechanism block such as a transport system.
3 is controlled. Image signal 14 from reading mechanism
08 is connected to the image processing block 1411 together with the read image transfer timing signal 1407.

The image signal 1410 to the printing mechanism is input to the image processing block 1411 together with the write image transfer timing signal 1419.

The image processing block 1411 includes a bus 140
4 performs predetermined image processing on the image data under the control of the control block 1403 through the interface block 1.
416.

When performing copying, the reading system is the data transmitting side and the print output system is the data receiving side. Here, it is assumed that the speeds of the reading system and the printing output system are different, and the operation in this case will be described.

When the power of the apparatus is turned on by a power switch (not shown) in FIG.
3 performs a series of initial processing.

Next, when one copy job is designated by input from the operation panel, control block 1403 is executed.
Performs predetermined settings in the image processing block 1411 via the bus 1404, and performs an image copying operation via the interface block 1416 by the method described in the first embodiment.

The setting and operation of the interface block 1416 are the same as in the first embodiment, and will not be described.

According to this embodiment, it is possible to realize an image copying apparatus in which an image input mechanism and a print output mechanism having different processing capabilities are combined.

In the memory, if the data transfer time on the scanner side is Ts and the data transfer time on the printer side is Tp instead of one page, Pmax * (1-Tp / Ts).

In the conventional example, the throughput is Ts + Td
Can be processed only by Td.

When outputting a plurality of parts, the memory address is set to 0.
By prohibiting the operation of returning to, the second and subsequent pages can be output at the original throughput of the apparatus.

[0179]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to provide a computer (or CPU) of the system or apparatus.
Or MPU) reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program codes, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instructions of the program codes. ) Performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, The case where the CPU of the function expansion board or the function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing.

[0185]

As described above, according to the present invention,
When the data transfer speed is different between the data transmission side and the data reception side, high throughput data transfer is possible while keeping the capacity of the memory used as the buffer small.

By preparing a buffer for one page,
When transferring a plurality of copies, data of the second and subsequent pages can be transferred according to the speed of the receiving side.

By applying the present invention to an image input / output device, it is possible to connect an image processing device of any processing speed.

By applying the present invention to an image processing device, an image input / output device of any processing speed can be connected.

Further, by applying the present invention to data transfer between an image input and an image output in an image copying apparatus, an image input device and an image output device having different speeds can be combined.

[0190]

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing system according to a first embodiment.

FIG. 2 is a detailed view of an interface block 116 in FIG.

FIG. 3 is a detailed diagram of a read control block 201 in FIG. 2;

FIG. 4 is a conceptual diagram of a basic operation when a fast input is output late.

FIG. 5 is a detailed diagram of an output control block 205 in FIG. 2;

FIG. 6 is a conceptual diagram of a basic operation when a slow input is output quickly.

FIG. 7 is a block diagram of Conventional Example 1.

FIG. 8 is a block diagram of a second conventional example.

FIG. 9 is a conceptual diagram of data transfer according to Conventional Example 2.

FIG. 10 is a block diagram of an image processing system according to a second embodiment.

FIG. 11 is a conceptual diagram of a basic image transfer timing.

FIG. 12 is a conceptual diagram of a basic memory control operation when a fast input is output late.

FIG. 13 is a basic conceptual diagram of memory control when a slow input is output quickly.

FIG. 14 is a block diagram of an image copying apparatus according to a third embodiment.

FIG. 15 is a conceptual diagram of memory control in which competition between read and write is prevented when a fast input is output late.

FIG. 16 is a conceptual diagram of memory control in which contention between reading and writing is prevented when a slow input is output quickly.

FIG. 17 is a flowchart of a memory control procedure on the data transmission side when a fast input is output late.

FIG. 18 is a flowchart of a memory control procedure on the data receiving side.

FIG. 19 is a flowchart of a memory control procedure on the data transmission side when a slow input is output quickly.

Claims (12)

[Claims] A first interface for inputting an image signal; a second interface means for outputting an image signal; a temporary storage memory; and data input from the first interface being sequentially transmitted to the temporary storage memory. First memory control means for writing data to the second interface, second memory control means for sequentially reading data output to the second interface from the temporary storage memory, and the temporary storage memory written by the first memory control means. A first timing control means for returning the address of the temporary storage memory to the head; and a second timing control means for returning the address of the temporary storage memory read by the second memory control means to the head. The total amount of data to be transferred is defined as Pmax, and the first and second interfaces Assuming that the ratio of the time required for transferring a fixed amount of data by the source means is Tf / Ts, the timing of returning the address to the head by the first and second timing means is Pmax * (1-Tf / A data transfer device, wherein the transfer of the amount of data of Ts) is completed. 2. The data transfer device according to claim 1, further comprising a selection unit for selecting whether or not to return the address to the head by the timing control unit. 3. An image processing apparatus comprising the data transfer apparatus according to claim 1 and transmitting or receiving image data by said data transfer apparatus. 4. An image processing apparatus further comprising an image input unit and an image output unit.
The image processing apparatus according to claim 3, wherein transmission and reception of image data between the image input unit and the image output unit are performed by the image transfer device. 5. A data transfer method for transferring data from a data transmitting side to a receiving side having a lower transfer rate via a buffer memory, comprising: a data amount to be transferred; For each block of the size determined based on the transfer rate, data from the transmission side is written to the buffer memory, and after a predetermined time has elapsed from the start of writing data to the buffer memory from the transmission side, the reception Starting data reading from the buffer memory to the side. 6. When deciding the block size,
The block size is determined by regarding the amount of data to be transferred to be the amount of data to be transferred, and adding the amount of data corresponding to the offset at the time of reception of data by the receiving side to the amount of data to be actually transferred. The data transfer method according to claim 5, wherein 7. The data transfer according to claim 5, wherein the block size is determined so that data in the buffer memory that has not been read by the receiving side is not overwritten by the transmitting side. Method. 8. A data transfer method for transferring data from a data transmitting side to a receiving side having a higher transfer rate via a buffer memory, comprising: a data amount to be transferred; For each block of the size determined based on the transfer rate, write data from the transmission side to the buffer memory, and immediately after writing the first block from the transmission side to the buffer memory, buffer the buffer to the reception side. A data transfer method comprising: starting reading data from a memory; and writing a second or subsequent block to the buffer memory after a lapse of a predetermined time. 9. When deciding the block size,
9. The data transfer method according to claim 8, wherein the block size is determined by regarding the amount of data to be actually transferred to which a predetermined amount of data has been added as the amount of data to be transferred. 10. The data transfer method according to claim 8, wherein the block size is determined so that the same data is not read twice by a transmission side. 11. A computer writes data from a transmission side to the buffer memory for each block of a size determined based on an amount of data to be transferred and a transfer rate of each of transmission and reception. After a lapse of a predetermined time from the start of writing data to the memory, reading of data from the buffer memory to the receiving side is started, and a buffer is transmitted from the data transmitting side to the receiving side having a lower transfer rate. A computer-readable storage medium for storing a program for realizing data transfer for transferring data via a memory. 12. A computer writes data from a transmission side into the buffer memory for each block of a size determined based on an amount of data to be transferred and a transfer rate of transmission and reception, and transmits the data from the transmission side to the buffer. As soon as the first block has been written to the memory, reading of data from the buffer memory to the receiving side is started, and after a lapse of a predetermined time, the second and subsequent blocks are written to the buffer memory to transmit data. A computer-readable storage medium for realizing a data transfer method for transferring data via a buffer memory from a side to a receiving side having a higher transfer rate.