JPH11183935A - Display elements - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide display elements permitting to exceed limits of contrast and definition caused by the fact that a lot of active elements are formed on a large area substrate. SOLUTION: A silicon integrated chip 3 is formed which has picture elements 2 and a drive signal generating function of the picture elements 2 on a multi- layer wiring substrate 1 on which a multi-layer wiring group 5 is formed on an insulating substrate. Thus, the silicon integrated chip 3 is electrically connected with the picture element electrodes 2 via multi-layer wiring group 5. And, it is possible to achieve liquid crystal display elements with a sharp contrast by providing a liquid crystal layer between the picture element electrodes 2 and an opposed substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display element in which a switching element, that is, an active element is added to each pixel.

[0002]

2. Description of the Related Art A general active active element used for a display element includes a thin film transistor (TFT) when the display element is a liquid crystal display element. There are many documents relating to these, and they are introduced in, for example, Semicon Kansai / Kyoto Technical Seminar 90 lecture proceedings.

Therefore, a conventional liquid crystal display device will be described below as one of the display devices. Here,
A display element having a display area of a certain size or more will be described. For example, consider a diagonal of about 3 inches or more.

Conventionally, a TFT uses, for example, an amorphous hydrogen-silicon alloy formed on an alkali-free glass substrate or hydrogen-treated polycrystalline silicon as a semiconductor constituting a channel. Usually, the processing temperature in the process is about 600 ° C. or less. That the alkali-free glass substrate is amorphous,
From the viewpoint of the substrate cost, setting the processing temperature to about 600 ° C. as an upper limit naturally imposes a strong restriction on the characteristics of the TFT.

[0005]

First, as described above, in the conventional TFT manufacturing process, the process at a processing temperature of about 600 ° C. or less is the upper limit. Therefore, it is difficult to use the silicon integrated circuit technology. Have difficulty.

More specifically, in the above-mentioned silicon integrated circuit technology, since a glass substrate is not used in terms of manufacturing technology, a temperature up to about 1100 ° C. can be used. A gate oxide film can be formed using a simple thermal oxide film, and the channel formation mechanism in a transistor is ideally inverted (inversion).
Mode. On the other hand, TF on a glass substrate
When forming T, the upper limit of the processing temperature at the time of manufacturing is about 600.
Due to the temperature of ° C., a film formed by a deposition process such as a chemical vapor deposition (CVD) method must be used as the gate oxide film, and the denseness and interface characteristics are inferior to the thermal oxide film. . There is also a limitation that the channel formation mechanism must use the aggregation (accumulation) mode.

[0007] Due to the above-mentioned limitations, there is also a limit in the characteristics of the TFT. The first is the ratio of the on-current value to the off-current value. For example, if the number of pixels is 4,000 × 4,0
When aiming at the display of the fidelity of 256 gradations or more in the high-definition display of about 00, the ratio needs to be about 10 ¹⁰ or more. However, in the conventional TFT, it is about 10 ⁷ at most.

Secondly, in the current reliability of the TFT, that is, in the life test of the so-called BT stress application, the change of the threshold value of the field effect transistor (FET) is too large. When the TFTs are used to calculate display signals, shift registers, operational amplifiers, and the like, the design becomes very strict.)

Next, a conventional method of manufacturing a TFT uses an LSI.
As compared with the above process, a transistor is formed inefficiently on a large-sized glass substrate, so that the inspection of TFTs which are sparsely formed on the large-sized substrate becomes inefficient. In addition, although the number of defective TFTs is allowed to some extent, they are considered as products.
If the number of T exceeds the limit, the entire substrate must be discarded, resulting in a great loss. Further, in the related art, it is difficult to increase the level of microfabrication in a photo process or the like by forming a thinly dispersed TFT on a large-area substrate such as glass, which causes a decrease in yield. For example, at the minimum dimension of the pattern, the level of fine processing is about 3 μm.

In addition, it is difficult to form a high-withstand-voltage (for example, operating up to a signal voltage of 60 V) FET with a pattern area that can withstand cost and characteristics in a conventional TFT, and it is very fast. FET (for example, about 30
(Following a 0 MHz clock) is difficult to achieve.
This imposes considerable restrictions on the calculation for applying various corrections for each pixel signal, and in some cases, the so-called point-sequential scanning with a large screen and high definition.

On the other hand, when an organic EL or the like is used as a display medium,
With the current TFT technology, it is extremely difficult to use for driving. This is different from the liquid crystal display, in the case of the organic EL display element, it takes a considerable amount of current (therefore, the transconductance of the FET needs to be large), and it is the best to attach one or two TFTs to each pixel. It is caused by that.

In view of the above problems, the present invention can overcome the limitations of contrast and definition caused by the formation of a large number of active elements on a large-area substrate. It is a main object to provide a simple display element.

[0013]

To achieve the above object, a first display device (transmissive liquid crystal display device) of the present invention is provided.
A multi-layered wiring substrate having a multi-layered wiring group formed on an insulating substrate, a pixel electrode formed on the multi-layered wiring substrate, and a drive signal generation for the pixel electrode formed on the multi-layered wiring substrate. A silicon integrated chip having a function, and a liquid crystal layer provided between the pixel electrode and the counter substrate, wherein the silicon integrated chip is electrically connected to the pixel electrode via the multilayer wiring group. The configuration is characterized by that.

Further, a second display element (reflection type liquid crystal display element) of the present invention comprises a multi-layered wiring substrate having a multi-layered wiring group formed on an insulating substrate, and a reflective display formed on the multi-layered wiring substrate. Pixel electrode, a silicon integrated chip formed on the multilayer wiring substrate and having a function of generating a drive signal for the pixel electrode, and a liquid crystal layer provided between the pixel electrode and a counter substrate. The silicon integrated chip is electrically connected to the pixel electrode via the multilayer wiring group.

Further, a third display element (EL display element) according to the present invention comprises a multi-layer wiring substrate having a multi-layer wiring group formed on an insulating substrate, and a pixel electrode formed on the multi-layer wiring substrate. A silicon integrated chip formed on the multilayer wiring substrate and having a function of generating a drive signal for the pixel electrode, and an organic electroluminescent layer provided between the counter electrode on the pixel electrode, A silicon integrated chip is electrically connected to the pixel electrode via the multilayer wiring group.

More specifically, a pixel region group including pixel electrodes insulated from each other is formed on the main surface of a multilayer wiring substrate having a wiring group insulated from each other, and one of the wirings in the multilayer wiring group is connected to a pixel. A one-to-one correspondence with one of the electrodes, the corresponding wiring and the pixel electrode are electrically connected by via holes, and a silicon integrated chip group having a pixel electrode drive signal generation function is mounted around the multilayer wiring base. A substrate in which one of the pads and one of the wirings is electrically connected through a via hole so that each pad of the silicon integrated circuit chip group corresponds to the pixel electrode at a ratio of 1: 1; A liquid crystal layer and an organic electroluminescent layer are mounted.

According to the above configuration, TF is provided in the vicinity of each pixel.
Since a T or the like is not provided, a group of silicon integrated circuit chips having a centralized operation function and switching function of a signal of a plurality of pixels is provided, and a signal is transmitted to each pixel by a multi-layer wiring technology. Will be. Therefore, the present invention has a structure in which an active element is attached to each pixel equivalently and an electric signal can be applied to each pixel, and a display quality equal to or higher than the conventional one is guaranteed. be able to.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A display device according to an embodiment of the present invention will be described below.

The display element of the present invention comprises a pixel electrode, a multi-layer wiring base having a wiring group for individually transmitting a signal to the pixel electrode, and a silicon integrated device having a centralized function of calculating and switching signals of a plurality of pixels. A circuit chip group is formed separately, and they are electrically connected.

Next, the display element (particularly, the active element) in the present embodiment will be described in detail with reference to the drawings.

FIG. 1 is a perspective view showing a configuration of a display element according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a multilayer wiring substrate, 2 denotes a pixel electrode, 3 denotes a silicon integrated circuit chip, and 4 denotes Bumps 5 formed on the pads indicate wiring groups in the multilayer wiring substrate. The bumps 4 are present between the main surface of the multilayer wiring substrate 5 and the silicon integrated circuit chip 3, and the chip 3 has a face-down form.

FIG. 2A is a sectional view taken along the line AA in FIG.
2B is a cross-sectional view showing the configuration of the multilayer wiring substrate at the portion indicated by '. FIG. 2B is a cross-sectional view showing the configuration of the multilayer wiring substrate at the portion indicated by the cross section BB' in FIG. In FIG. 2, 6 is an insulating base material, 7 is an insulating resin layer, 8 is a silicon integrated circuit chip, 9 is a pixel electrode, 10 is a wiring group, 11
Denotes a conductive via hole connection, 12 denotes a bump formed on a pad having a conductive particle group in the periphery, 13 denotes a conductive via hole connection, and 14 denotes a fixing resin. The conductive particle group is a result of drying the conductive paste. The insulating base 6 may be made of an inorganic material or an organic base. Further, although a resin material is used for the insulating resin layer 7, low-temperature melting glass may be used instead.

Next, a method of manufacturing a display element (particularly, a method of manufacturing an active element) according to the present embodiment shown in FIGS. 1 and 2 will be described with reference to the drawings. In the drawings, the number of pixels is reduced for the sake of simplicity, but in reality, for example, an insulating substrate of about 40 cm square having 2000 × 2000 pixels is used to form a multilayer wiring substrate. Created.

FIG. 3 is a sectional view showing a manufacturing process of a silicon integrated circuit chip having bumps. In FIG. 3, 1
5 denotes a silicon integrated circuit chip, 16 denotes a pad, 17 denotes a photoresist film, 18 denotes a nickel-gold electroless plating film, and 19 denotes a copper electroless plating bump.

First, a MOSIC with a logic design and a mask design on a single crystal silicon wafer according to the 2 μm rule
I made a chip. At this time, in the silicon integrated circuit chip, about 5 μm × about 10 mm
20 × 200 rows of pads are arranged at a pitch of 0 μm (FIG. 3A).

Next, copper bumps 19 are formed on the pads 16 of the silicon integrated circuit chip 15. In this case, first, a negative resist OMR-
With 83, a partial pattern excluding the pad 16 is formed (FIG. 3B).

Thereafter, the side and back surfaces of the chip are also covered with picane, and only nickel pads are formed on the pads 16 by a known method.
Form a gold film. Then, an adsorption film of tin chloride is formed by the treatment liquid, and palladium chloride is reduced to metal palladium by the reducing action of the tin chloride, and is adsorbed on the pad. Further, a nickel-gold electroless plating film is formed on the above-mentioned metal palladium by a heating process using the same electroless nickel plating solution and electroless gold plating solution. The thickness is about 0.3 μm. At this time, a nickel-gold electroless plating film is also deposited on an organic film such as a resist film. Therefore, the organic film is removed with an organic solvent or the like, and the nickel-gold electroless plating film excluding the pad is removed.
Next, a resist pattern having an opening only in the pad portion was formed again by the negative resist OMR-83. Furthermore, O
₍₂₎ The nickel-gold film portion of the pad portion is cleaned by the incinerator (FIG. 3C).

Next, an electroless copper bump 19 is formed on the nickel-gold film portion 18 of the pad portion using a copper sulfate-based solution. The diameter of the pad is about 20 μm, and the height of the bump is slightly more than 10 μm. Finally, when the resist film is peeled off with an organic peeling liquid, a silicon integrated circuit chip that is electrically connected to the multilayer wiring substrate via the bumps is completed (d).

Next, FIG. 4 is a sectional view showing a manufacturing process of a multilayer wiring substrate to which silicon integrated circuit chips are electrically connected. In FIG. 4, 20 is an insulating base material, 21 is a wiring group,
22 is a first insulating resin layer, 23 is a first conductive via hole, 24 is a second insulating resin layer, 25 is a second conductive via hole, 26 is a pixel electrode, 27 is an insulating resin layer, and 28 is conductive. Via hole, 29 is a silicon integrated circuit chip, 30
Denotes a bump and 31 denotes a fixing resin. In FIG. 4, the insulating resin layer 27 indicates the entire first insulating resin layer 22 and the second insulating resin layer 24, and the conductive via hole 28 includes the first conductive via hole 23 and the second conductive resin layer 23. The entire via hole 26 is indicated. In addition, the insulating substrate 20
May be composed of an inorganic material or an organic base material.
Although a resin material is used for the insulating resin layer 22 and the second insulating resin layer 24, a low-melting glass may be used instead.

As shown in FIG. 4, a multilayer wiring substrate was prepared. However, at the same insulating resin layer level, the wiring is about 50μ.
It was formed with a pitch of m and a line width of 15 μm. Each insulating resin layer had a thickness of about 5 μm, and 200 layers were laminated. Needless to say, a wiring layer was formed for each insulating resin layer level, and a long (full day) heat treatment at about 60 ° C. was frequently used to alleviate distortion of the insulating resin layer.

The details of FIG. 4 will be described below. As the insulating base material 20, alkali-free glass # 1373 manufactured by Corning Incorporated was used (FIG. 4A). The insulating base material 20 obtained beforehand was sufficiently flattened by polishing. Next, wiring is formed on the insulating base material 20. Here, a composite film of a titanium film (about 3 nm), an ITO film (about 200 nm), and a titanium film (about 3 nm) is formed on the substrate by sputtering. A wiring group was formed at a temperature of about 120 ° C. and formed by photolithography using a known positive resist and fine processing with dilute hydrofluoric acid or hydroiodic acid (FIG. 4B). The above-described titanium film is transparent.

Thereafter, the insulating substrate 2 on which the wiring group is formed
On the first insulating resin layer 22, a first resistive resin layer 22 (a negative resist OMR-83 manufactured by Tokyo Ohka) was formed, and a via hole was formed in the first insulating resin layer 22 by a usual photolithography method. The diameter was about 15 μm. Then, after exposing this via hole to oxygen plasma, a two-layer film of chromium-gold was deposited by a sputtering method, and the first conductive via hole 23 was formed by a known wet etching.
Note that the thickness of the gold film is set to approximately 400 nm. Further, the wiring group patterned on the first insulating resin layer 22 and the second insulating resin layer 24 are connected to the second conductive via hole 2.
5 is formed by the same method as described above (FIGS. 4C and 4D).

Next, after the transparent pixel electrode 26 is formed of ITO by a known method (FIG. 4E), the bump 30 formed on the silicon integrated circuit chip 29 by the method shown in FIG. A silver paste is applied to the tip as a conductive adhesive, and the silicon integrated circuit chip 29 is bonded face-down so as to match a predetermined via hole of the multilayer wiring substrate. Finally, the silver paste is dried, and an ultraviolet-curing resin is poured into the gap between the silicon integrated circuit chip 29 and the multilayer wiring substrate, and the silicon integrated circuit chip 29 is fixed by irradiating ultraviolet rays. The connected multilayer wiring base is completed.

The following describes three specific display elements using a multilayer wiring substrate to which the silicon integrated circuit chips formed as described above are electrically connected. The display element is completed by forming a display medium layer on the pixel group on the main surface of the multilayer wiring substrate of FIG.

First, a description will be given of a transmission type liquid crystal display element using a multi-layer wiring substrate to which the above-mentioned silicon integrated circuit chip is electrically connected. At this time, a liquid crystal layer is used as a display medium. In FIGS. 1 and 2 described above, for example, polished alkali-free borosilicate glass (# 1373 manufactured by Corning Incorporated) is used for the insulating base material 6. If a transparent resin (for example, a negative resist OMR-83 manufactured by Tokyo Ohka) is used as the insulating resin 7 on the insulating base material 6, it is advantageous for forming via holes. As the wiring group 10 and the pixel electrode 9, a transparent conductive material, tin oxide containing tin (so-called IT
O).

For the liquid crystal layer, an alignment film is formed by a well-known method, a counter substrate (where necessary, a common electrode, a color filter, an alignment film, and the like is provided), and a gap is filled with liquid crystal. Furthermore, outside the counter substrate, if necessary,
A polarizing plate is provided. It should be noted that a light source and, in some cases, a polarizing plate are provided on the back surface side of the multilayer wiring substrate. Thus, twisted nematic liquid crystal display elements, in-plane
A switching liquid crystal display element, an antiferroelectric liquid crystal display element, and the like can be obtained.

Secondly, a description will be given of a reflection type liquid crystal display element using a multi-layer wiring substrate to which the above-mentioned silicon integrated circuit chip is electrically connected. At this time, a liquid crystal layer or a liquid crystal layer containing a dichroic dye is used as a display medium.
In FIGS. 1 and 2, as the insulating base material 6, for example,
A polished alumina substrate, a polished glass epoxy substrate, and an alkali-free borosilicate glass (such as # 1373 manufactured by Corning Incorporated) are used. As the insulating resin 7 on the insulating base material 6,
Transparent resin (for example, Tokyo Ohka negative resist OMR-
83 etc.) are easy to use. Although slightly colored, using Toray's photosensitive polyimide photonice is convenient for fine processing. The wiring group 10 may be made of a metal, for example, tungsten, tantalum, zircon, titanium, chromium, an alloy of these with aluminum, or ITO.
The pixel electrode 9 is desirably reflective, and aluminum or an aluminum alloy is selected. Further, in the reflection characteristics of the pixel electrode 9, a diffuse reflection characteristic is desirable, and therefore, the surface shape of the pixel electrode 9 may be modified.

For the liquid crystal layer, an alignment film is formed by a well-known method, a counter substrate (where necessary, a common electrode, a color filter, an alignment film, etc. is provided), and the gap is filled with liquid crystal. Further, a polarizing plate and a refractive index anisotropic film are provided outside the opposing substrate as needed.

Third, an organic EL display element using a multilayer wiring substrate to which the above-mentioned silicon integrated circuit chip is electrically connected will be described. At this time, a composite layer of an organic EL layer and a charge transfer layer is used as a display medium. These technologies are described in the "Proceedings of
Society Of Information Di
spray, 1997 "from Idemitsu Petrochemical. 1 and 2, as the insulating base material 6,
For example, polished alkali-free borosilicate glass (# 1373 manufactured by Corning Incorporated) is used. When a transparent resin, for example, a negative resist OMR-83 manufactured by Tokyo Ohka, is used as the insulating resin 7 on the insulating base material 6, it is advantageous for forming via holes. The wiring group 10 and the pixel electrode 9 are preferably made of a transparent conductive material and tin oxide containing tin (so-called ITO). This is also desirable for ease of electron injection into the charge transfer layer. The counter electrode is preferably made of aluminum containing lithium metal in order to minimize the hole injection barrier.

Although the display element of the present invention has been described with the embodiments, the effects of the present invention will be described in detail below.

According to the present invention, a multi-layer wiring base having a pixel electrode, a wiring group for individually transmitting a signal to the pixel electrode, and a silicon integrated device having a centralized function of calculating and switching signals of a plurality of pixels. Since a display element is formed by individually forming a circuit chip group and then electrically connecting them, a large-area insulating substrate (a glass substrate in the case of a liquid crystal display element) as in the related art is used. It is not necessary to form active active elements in discrete states.

Accordingly, the multi-layer wiring substrate and the silicon integrated circuit chip group can be easily manufactured by the established integrated circuit process, and each of the silicon integrated circuit chips has an inspection function. By including it, accurate and quick inspection becomes possible. Thus,
Defective multi-layer wiring substrates and defective silicon integrated circuit chips can be eliminated individually, so that, for example, when a number of element failures exceeding an allowable range occur, the cost of the substrate is greatly reduced as compared with the conventional case where the substrate is defective. Occurs.

Next, while the conventional FET group is formed on an amorphous substrate such as glass, the FET group according to the present invention is formed on a single crystal silicon wafer by silicon integrated circuit technology (IC technology). The effect of the present invention resulting from realization will be described.

According to the present invention, instead of forming active active elements on a glass substrate, in terms of manufacturing technology,
Since silicon integrated circuit technology will be used, about 11
Because a temperature up to around 00 ° C. can be used, a well-known ideal thermal oxide film can be formed to form a gate oxide film, and a channel formation mechanism in a transistor can be changed to an ideal inversion mode. can do.

As a result, first, according to the FET according to the present invention, the ratio of the on-current value to the off-current value can be about 10 ¹¹ or more.
In a high-definition display of about 4,000, it is possible to easily display a fidelity of 256 gradations or more. Second, in the current reliability of the TFT, that is, in the life test under the so-called BT stress application, the threshold value of the field effect transistor (FET) hardly changes, and the calculation of the display signal, the shift register, the operational amplifier, etc.
Can also be configured.

In contrast, in the prior art, a group of thinly dispersed TFTs is formed on a large area substrate such as glass, whereas in the present invention, a group of FETs are densely formed on a silicon single crystal wafer. Because it is obtained, it is formed by a normal IC process, and is diced into chips, so that the pattern can be processed to a minimum dimension of 1 μm or less, if necessary, even at the minimum dimension. Further, in the present invention, a high withstand voltage (for example,
To form an FET that operates up to a signal voltage of 60V)
Very fast FETs (eg, following a clock of about 300 MHz) can also be achieved.

This opens up the possibility of performing calculations to apply various corrections to each pixel signal, and possibly performing so-called point-sequential scanning on a large screen and high definition. . Further, the video / RAM memory and the like are formed on the same chip, and the CPU is stopped for a still image or the like, so that power consumption can be reduced.

Further, when an organic EL or the like is used as a display medium, it is necessary to take a current or to continue to supply a current corresponding to a signal voltage for one frame. Although impossible, according to the present invention,
It is possible to supply a group of FETs capable of taking a large amount of current (thus, the transconductance of the FET needs to be large), and further satisfy the need to use a large number of FETs to control each pixel.

As a display element, a black-and-white transmissive liquid crystal display element was formed on a main surface pixel group of a multilayer wiring substrate by a known method as described above. It was excellent at about 500: 1. Although a similar display element using a conventional TFT cannot be realized (the size of the manufacturing apparatus is limited), the simulation estimates that the charging time of the gate capacitance is not sufficient, and the contrast is about 140: It will be about 1. Also,
The number of defective pixels was also reduced by one digit from the defect rate assumed when a conventional TFT substrate was used. When a defective pixel occurs, it is relatively easy to correct it.

[0050]

According to the present invention, there is provided a multi-layered wiring substrate having a pixel electrode, a wiring group for individually transmitting a signal to the pixel electrode, and a silicon integrated device having a centralized operation function and a switching function for signals of a plurality of pixels. Since the circuit chip group is formed separately and they are electrically connected, it is possible to easily form an active active element having higher reliability and integration degree than the conventional one. High value.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a configuration of a display element according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a display element according to an embodiment of the present invention.

FIG. 3 is a sectional view of a manufacturing process of a silicon integrated circuit chip used for a display element according to the embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the display element according to the embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 multilayer wiring substrate 2 pixel electrode 3 silicon integrated circuit chip 4 bump formed on pad 5 wiring group in multilayer wiring substrate 6 insulating base material 7 insulating resin layer 8 silicon integrated circuit chip 9 pixel electrode 10 wiring group 11 conductive Conductive via hole connection 12 Bump formed on pad having conductive particle group around 13 Conductive via hole connection 14 Resin for fixing 15 Silicon integrated circuit chip 16 Pad 17 Photoresist film 18 Nickel-gold electroless plating film 19 No copper Bump by electrolytic plating 20 Insulating base material 21 Wiring group 22 First insulating resin layer 23 First conductive via hole 24 Second insulating resin layer 25 Second conductive via hole 26 Pixel electrode 27 Insulating resin layer 28 Conductive via hole 29 Silicon integrated circuit chip 30 Bump 31 Fixing resin

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Takeshi Karasawa 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Mariko Kawaguri 1006 Kazuma Kadoma Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A multi-layer wiring substrate having a multi-layer wiring group formed on an insulating substrate, a pixel electrode formed on the multi-layer wiring substrate, and a pixel electrode formed on the multi-layer wiring substrate and having a A silicon integrated chip having a drive signal generation function, and a liquid crystal layer provided between the pixel electrode and a counter substrate, wherein the silicon integrated chip is electrically connected to the pixel electrode via the multilayer wiring group. A display element which is connected. 2. A multi-layer wiring substrate having a multi-layer wiring group formed on an insulating substrate, a reflective pixel electrode formed on the multi-layer wiring substrate, and a multi-layer wiring substrate formed on the multi-layer wiring substrate. A silicon integrated chip having a function of generating a drive signal for a pixel electrode, and a liquid crystal layer provided between the pixel electrode and a counter substrate, wherein the silicon integrated chip is connected to the pixel electrode via the multilayer wiring group. A display element which is electrically connected. 3. A multi-layer wiring base having a multi-layer wiring group formed on an insulating substrate, a pixel electrode formed on the multi-layer wiring base, and a pixel electrode formed on the multi-layer wiring base and having a A silicon integrated chip having a driving signal generation function, and an organic electroluminescent layer provided between the pixel electrode and a counter electrode, wherein the silicon integrated chip is connected to the pixel electrode via the multilayer wiring group. A display element which is electrically connected.